JPS6130300B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory module system with improved data processing capability.

In general, memory module systems for electronic computers, microcomputers, and other applied products are
It has a configuration as shown in FIG. That is, for the address/data bus B output from the CPU module C, which has a central processing function, the main memory module M1 and the auxiliary memory module M
2 and DMA (Direct Memory Access) module D, etc., there are input/output modules A1, A2, etc. for various interfaces and various controllers, etc.
…AN is connected.

By the way, the DMA module D speeds up the processing in the CPU and main memory, thereby contributing to the efficiency of data transmission between the peripheral devices (not shown) connected to the input/output modules A1 to AN, etc. In other words, the CPU is the main memory module M
1 and auxiliary memory module M2 to input/output modules A1 to AN.
When the CPU gives a certain command to the DMA module D, the DMA module D takes control of the data processing and executes it, and sends a completion signal to the CPU module C after completing the data processing. be. Therefore, not only the CPU, main memory, and auxiliary memory, but also the DMA form the backbone of electronic computers. As a result, the processing capacity of computers and the like is effectively determined by the processing speed of the core components and the number of DMA connectable channels. Especially this kind of
When transmitting and receiving data using DMA, the main memory module M1 and each of the input/output modules A1 to AN are in a paired relationship, so a certain input/output module monopolizes the DMA module D to process data. while other input/output modules are DMA
There is a problem where module D cannot be used. Therefore, for example, if the number of transmitted words is large or the speed of peripheral equipment is somewhat slow, the time each input/output module A1 to AN exclusively uses DMA module D will be longer, and during this time other input/output modules A1
~Data processing in the AN was delayed, and the overall system's processing capacity was undeniably reduced.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide an input/output module with a part of the main memory function, and to use a cycle steal method to link the CPU module and the input/output module. The purpose of the present invention is to provide a memory module system that reduces data transmission between devices, increases the processing capacity of the entire system, and makes the core part unaware of the limitations of data processing.

An embodiment of the present invention will be described below with reference to FIG. In this modular system
CPU module C, main memory module M
1. Auxiliary memory module M2 and DMA module D are connected to address/data bus B;
It performs almost the same functions as before.

What is particularly different about the memory module system of the present invention is that the input/output modules A11 to A1N, such as various interfaces and controls, have the characteristics of buffers that can be written to and continuously output, and the system as a whole has the main memory. A dual port memory M3, which is used as a form of storage, is mounted, and an I/O processor P is also mounted. This memory M3 has two entrances and exits (dual ports) and is of the cyclosteal type that can be accessed simultaneously from the CPU module C and the I/O processor P. Further, the dual port memory M3 is configured to serve as a relay function during data transmission between the CPU module C and peripheral devices.

In the memory module system configured as described above, when transmitting processing data to a peripheral device (not shown), first, the data of the main memory module M1 and the auxiliary memory module M2 are input/output according to the program. After moving to module M3, CPU module C is moved to I/O processor P.
When you give a command to perform a predetermined process,
The I/O processor P uses, for example, file number F1 (see FIG. 3) of the main memory module M1 to process data and transmit it to a peripheral device (not shown). At this time, the CPU module C can read and input the program data from the main memory M1 to the file number F2 of the dual port memory M3. In other words, since the dual port memory M3 is a cycle steal method, the CPU can access the dual port memory M3 when executing a predetermined program by the I/O processor P or when executing another process. .

Next, when inputting data, the data is stored from a peripheral device (not shown) to file numbers F1, F2, etc. of the dual port memory M3;
When the second class is full, the I/O processor P
Request data reading to CPU module C,
Processing for transferring data to the main memory module M1 and the auxiliary memory module M2 can be performed. Such processing can only be realized if the dual port memory M3 has a role as a main memory and is a cycle steal method.

Note that the present invention is not limited to the above embodiments. For example, in this system, each input/output module A11 to A1N has a part of the main memory as a dual port memory. A1
1 to A1N can also have intelligence. In this way, each module A11
All data related to A1N can be calculated and edited by each I/O processor P, and the functionality of the entire system can be significantly improved.

As detailed above, according to the present invention, each input/output module is equipped with a dual port memory and an I/O processor, and this dual port memory is used as part of the main memory of the entire system, so that the CPU Data processing can be performed even when data is stored in a portion of the dual port memory. This can shorten the time required to transfer data from the dual port memory to the main memory module, and can speed up data processing. In addition, since a portion of the main memory is built into the input/output module itself, each module can process itself without relying on the DMA module. In addition, the cycle steal method is used only when the CPU accesses the dual port memory, and the access frequency is low, making it possible to provide a memory module system that can realize high-speed data processing.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional system, FIG. 2 is a configuration diagram showing an embodiment of a memory module system according to the present invention, and FIG. 3 is a diagram showing an example of the configuration of the dual port memory shown in FIG. 2. It is. C...CPU module, M1...Main memory module, M2...Auxiliary memory module,
A11~A1N...Input/output module, M3...
Dual port memory, P...I/O processor, F1~FN...File number.

Claims (1)

[Claims] 1 In a memory module system in which input/output modules such as various interface modules and control modules are connected in addition to the main memory module and auxiliary memory module to the address bus that inputs and outputs to the CPU module,
In the input/output module, there is a dual port memory that functions as a part of the main memory, and an I/O
A processor is provided for the CPU module.
A memory module system characterized in that a CPU and an I/O processor can freely access the dual port memory as main memory.