JPS6347867A - Inter-dual cpu communication system - Google Patents

Abstract

PURPOSE:To attain the transmission/reception of a large capacity of data at a high speed and low cost, by writing a transmission data on a RAM in parallel through a data bus, by a CPU on a transmission side, and reading out a written data by the CPU on a reception side. CONSTITUTION:A first CPU, when the transmission data being generated, confirms the nonuse of the RAM4 by a second CPU2 based on whether the controlled output 9 of the second CPU2 becomes active or not, and outputs the transmission data to the data bus 8. In this way, the transmission data from the CPU1 is written on the RAM4 through a switching control circuit 3. Also, the second CPU2 confirms the nonuse of the RAM4 by the first CPU1 based on whether the controlled output 5 of the CPU1 becomes active or not, and reads the transmission data from the CPU1 stored in the RAM4.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a dual CPU (processor) in which two CPUs (processors) share processing while transmitting and receiving data to each other.
It relates to circuits, and particularly to communication methods between CPUs.

[Conventional technology]

Conventionally, this type of inter-chieral communication method has been a method of serially transmitting and receiving data using a serial port of a CPU, or a method of transmitting and receiving data between CPUs via a data bus.
(First-1n-first-out) is placed,
The method is to send and receive data in parallel.

Problems to be Solved by Invention C] In the conventional CPU-to-CPU communication method described above, the method of serially transmitting and receiving data using the CPU serial port has a limited transfer speed, so it is difficult to handle large amounts of data. There was a problem with not being able to send and receive data at high speed.

Also: The method of placing FIFOs between CPUs via a data bus and transmitting and receiving data in parallel has the problem of not being able to transmit and receive large amounts of data all at once because the number of FIFO stages is limited, and the bit cost is high. There was a problem.

The present invention solves the above-mentioned problems, and its purpose is to enable high-speed transmission and reception of large amounts of data at low bit costs.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention aims to solve the following problems. Second
In a dual CPU circuit in which the CPUs share processing while transmitting and receiving data to and from each other, a RAM and a RAM; a switching control circuit for controlling whether or not the address bus, data bus, and status bus of the second CPU are connected to the RAM; When the second CPU sends data ε, the second CPU determines whether the control output of the other CPU is active or not, and if it determines that it is not active, it activates its own control output and again controls the control output of the other CPU. Determine whether the control output is active or not, and then determine that it is not active again to write transmission data to the RAM using the address bus, data bus, and status bus, and when receiving data,
It is determined whether the control output of the other CPU is active or not, and when it is determined that it is not active, its own control output is activated, and the control output of the other CPU is activated again.
has a configuration in which the received data written in the RAM is read out using the address bus, data bus, and status bus by determining whether the control output of the controller is active or not, and determining that the control output is not active again. and the switching control circuit is connected to the first switching control circuit. Among the address bus, data bus, and status bus of the second CPU, the address bus, data bus, and status bus of the CPU whose control output is active are connected to the RAM.

[For production]

To transmit and receive data, the CPU on the sending side writes the sending data to RAM in parallel via the data bus, and the CPU on the receiving side writes the sending data in parallel to the RAM.
is performed by reading data written in RAM. Therefore, it becomes possible to transmit and receive large amounts of data at high speed. Furthermore, when transmitting and receiving data, that is, when accessing RAM, the CPU determines whether the control output of the other CPU is active, and if it determines that it is not active, activates the control output of its own CPU. The first step is to access the RAM by determining again whether the control output of the other party is active or distorted and determining that it is not active again. This prevents the second CPU from accessing the RAM at the same time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
When accessing, control output 5 is activated (“1”)
When accessing the first CPUI and RAM4,
It is composed of a second CPU 2 which makes the control output 9 active, and a switching control circuit 3. In addition, RAM4 is cp
The first one used when transferring data from ut to CPU2.
It has an area and a second area used when transferring data from the CPU 2 to the CPUI.

Also, in the same figure, 6.10.13 is an address bus,
7.11.14 is a status bus, and 8.12.15 is a data bus.

FIG. 2 is a block diagram showing an example of the configuration of the switching control circuit 3, which includes three-state buffers B1 to B8 that become active when the control signal becomes 11'', and a status with the control output 5 as one input. AND gate Al whose other input is a predetermined bit of bus 7, and control output 9.
an AND gate A2 which has one input as input and a predetermined bit of status bus 11 as the other input; an inhibit gate 11 with control output 5 as one input and a predetermined bit of status bus 7 as the other input; It consists of an inhibit gate 2 which has the output 9 as one input and a predetermined bit of the status bus 11 as the other input.

Note that the predetermined bits of the status bus 7.11 are RAM
When writing data to RAM 4, it becomes "1°," and when reading data from RAM 4, it becomes "01." Therefore, when the CPUI writes data to the RAM4, the three-speed buffer B1. B3. When B5 becomes active and the CPU 2 writes data, the three-state buffer B2. B4. B7 becomes active,
When the CPU 2 reads data from the RAM 4, three-state buffers B1, B3, and B6 become active, and when the CPU 2 reads data from the RAM 4, the three-state buffers B2. B4. B8 becomes active.

Next, the operation will be described by taking as an example the case where data is transmitted from the first CPU 1 to the second CPU 2.

As shown in the flowchart of FIG. 3, the first CPU 1 activates the control output 9 of the CPU 2 to determine whether or not the second CPU 2 is using the RAM 4 when transmission data is generated (step S1). (step S2), and when it is confirmed that the second CPU 2 is not using the RAM 4, the first CPU 2
PU1 activates its own control output 5 (step 53).Next, in order to prevent a conflict between the use request for RAM4 with the second CPU2, the first CPU again checks the control output 9 of CPU2 (step 53). S4), if the control output 9 is inactive, outputs the write address to the address bus 6, outputs status information indicating that writing is to be performed to the status bus 7, and outputs the write address to the data bus 8.
(step S5), thereby causing the three-state buffer Bl in the switching control circuit 3 to output transmission data to the switching control circuit 3.

B3. Only B5 becomes active, address bus 6 and address bus 13 are connected, and status bus 7
and the status bus 14 are connected, and the data bus 8 and the data bus 15 are connected, so that transmission data from the first CPUI is written into the first area of the RAM 4. Then, when the sending of the transmission data is completed, the CPU
"1" is stored as a flag in the predetermined location #A of the area (step S6), and then the process moves to other control steps.

Incidentally, if the determination result in step S2 is YES, that is, if the second CPU 2 is accessing the RAM 4, after performing the waiting process for a certain period of time (step S8), the process in step S2 is performed again. If the determination result in step S4 is YES, the control output 5 is made inactive (step S7), and after a predetermined time waiting process (step S8), the process in step S2 is executed again.

Further, as shown in the flowchart of FIG. 4, when the second CPU 2 comes to check the presence or absence of received data (step 511), the first CPU 2 checks the RAM 4.
It is determined whether the RAM 4 is being used or not based on whether the control output 5 is activated (step 512). When it is confirmed that the first CPU 1 is not using the RAM 4, the second CPU 2 Activate its own control output 9 (step 313), then the CPU
Step 2 is to check the control output 5 of the CPU again in order to prevent a conflict between the usage request for the RAM 4 and the CPU (step 514), and if it is inactive, check whether there is received data in the first area of the RAM 4. Specified location #A
The determination is made based on whether the flag F stored in the flag F is 11'' (step 315).

If it is determined that there is received data, the CPU 2 outputs the subsequent address to the address bus 10, and outputs status information indicating that reading is to be performed to the status bus 11 (step 316). Three-state buffer 1B2. B4. Since B8 becomes active, the transmission data from the first CPUI stored in the first area of RAM4 is transferred to the second CPU
It will be read into PU2. Then, when all the data sent from the CPUI is read, that is, when the reception is completed,
The CPU 2 sets the flag F stored in the predetermined location #A of the first area of the RAM 4 to 0'' (step 517), and then moves to other control steps.

Further, if the determination result in step 312 is YES, that is, if the CPUI is accessing the RAM 4, after performing the waiting process for a certain period of time (step 519), the process in step S2 is performed again, and the process in step S314 is performed. If the determination result is YES, the control output 9 is returned to non-active (step 318), and after a predetermined time waiting process (step 519), the process of step S12 is executed again.

In addition, in the embodiment described above, from the first CPUI to the second CPU
Although we have explained the case where data is sent to U2,
A similar operation is performed when data is sent from the CPU 2 to the first CPUI. Further, in the above-described embodiment, when accessing the RAM 4, the control output of the other party's CPU is checked twice, but the control output is not limited to this, as long as the control output is checked multiple times.

〔Effect of the invention〕

As explained above, in the present invention, the CPU on the sending side writes the sending data to the RAM in parallel via the data bus,
Data is sent and received between the CPUs by the CPU on the receiving side reading the data written in the RAM, so it has the advantage of being able to send and receive large amounts of data at high speed and with low bit cost. . Furthermore, when accessing the RAM, the present invention determines whether or not the control output of the other party's CPU is active, and by determining that it is not active, activates the control output of the own CPU. The first step is to determine whether the control output of the other party is active or not, and access the RAM by determining that the control output is not active again. There is also the advantage that the second CPU can be prevented from accessing the RAM at the same time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the configuration of a switching control circuit, Fig. 3 is a flowchart showing a part of the processing contents of the CPU It is a flowchart which shows a part of processing contents. In the figure, 1.2...CPU, 3...Switching control circuit, 4...RAM, 6.10.13...Address bus, 7゜11, 14...Status bus, 8 .12
．． 15...Data bus, 81-B8...Three-state buffer, AI. A2...And gate, 11.12...Inhibit gate.

Claims (1)

[Scope of Claims] In a dual CPU circuit in which a first and second CPU share processing while transmitting and receiving data to and from each other, a RAM, an address bus, a data bus, and a data bus of the first and second CPUs are provided. and a switching control circuit that controls whether or not to connect a status bus to the RAM, and the first and second CPUs determine whether the control output of the other CPU is active or not when transmitting data. Then, by determining that it is not active, it activates its own control output, and again determines whether or not the control output of the other CPU is active, and by determining that it is not active again, it activates the control output of the other CPU. Write transmission data to the RAM using a bus and a status bus, and when the first and second CPUs receive data, the first and second CPUs
determines whether the control output of the other CPU is active, and by determining that it is not active activates its own control output, and again determines whether the control output of the other CPU is active, and again The switching control circuit reads the received data written in the RAM using the address bus, data bus, and status bus by determining that it is not active, and the switching control circuit reads the received data written in the RAM using the address bus, data bus, and status bus, and A dual CPU communication system characterized in that, among buses and status buses, an address bus, a data bus, and a status bus of a CPU whose control output is active are connected to the RAM.