JPH0535693A - Data transfer device - Google Patents

Abstract

PURPOSE:To perform the data transfer between CPUs without increasing the parts and the wiring. CONSTITUTION:When the data transfer is performed from a CPU 3 to a CPU 4, the CPU 3 writes the data in a shared memory 5 and writes the identifier of a shared memory 6 of a transfer destination and the number of the data transfer in a special address. A data transfer circuit 1 reads the content from the special address of the shared memory 5 corresponding to the CPU 3 to receive the data transfer request. The data transfer circuit 1 outputs a waiting signal 111 to a CPU 2 and performs the data transfer between shared memories 5 and 6 in accordance with the content of the special address. The CPU 4 reads the data from the shared memory 6 and completes the data transfer from the CPU 3 to the CPU 4.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a data transfer device, and more particularly to a data transfer method between three or more CPUs (central processing units).

[0002]

2. Description of the Related Art Conventionally, in a data transfer method between CPUs, a shared memory (DPM: Dual Port Memory) is provided for each CPU.
y) is provided, and data transfer between CPUs is performed using this shared memory.

In such a conventional data transfer method, C
Since a shared memory is required for each section where data transfer is required between PUs, there is a drawback in that the number of parts and wiring is increased.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and is a data transfer device capable of transferring data between CPUs without increasing the number of parts and wiring. For the purpose of providing.

[0005]

A data transfer apparatus according to the present invention comprises first and second shared memories connected to a first central processing unit, and a second central processing unit connected to the first shared memory. A third central processing unit connected to the second shared memory, and a transfer written in the first shared memory when transferring data from the second central processing unit to another central processing unit Read means for reading the destination, and transfer means for transferring the data of the first shared memory to the second shared memory when the transfer destination read by the read means is the third central processing unit. It is characterized by having.

[0006]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, CPU2 is a CPU bus 100
To a shared memory (DPM) data transfer circuit (hereinafter referred to as a data transfer circuit) 1 and shared memories 5 and 6, a CPU 3 is connected to a shared memory 5 via a CPU bus 101, and a CPU 4 is a CPU bus. It is connected to the shared memory 6 via 102.

That is, the CPUs 2 to 4 share the shared memory 5,
The point-to-multi is connected to the CPU 6, and the CPU 2 on the point side and the CPUs 3 and 4 on the multi side are connected to the shared memories 5 and 6, respectively.

FIG. 2 is a block diagram showing the configuration of the data transfer circuit 1 of FIG. In the figure, a data transfer circuit 1 is a bus management unit 10 that monitors the usage status of the CPU bus 100.
And data transfer request signals 131, 141 from the CPUs 3, 4
And a data transfer request receiving unit 11 for receiving the transfer destination and the number of data transfers from the shared memories 5 and 6, and a data transfer unit 13 for transferring data between the shared memories 5 and 6. Has been done.

The operation of the embodiment of the present invention will be described with reference to FIGS. 1 and 2. CPU2 is CPU3
4 is written in the shared memories 5 and 6 from the CPU 2 via the CPU bus 100. After that, the CPUs 3 and 4 read out the data from the shared memories 5 and 6, and the CPUs 2 and 3 and 4
Data transfer between the two.

When the CPUs 3 and 4 transfer data to the CPU 2, the CPUs 3 and 4 are connected to the CPU bus 10 respectively.
The data is written to the shared memories 5 and 6 via 1 and 102, and the transfer destination C is written to a specific address of the shared memories 5 and 6.
Write the identifier of PU2, and send the data transfer request signals 131, 14
1 is output to the data transfer circuit 1.

In the data transfer circuit 1, the data transfer request receiving section 11 causes the data transfer request signal 131 from the CPUs 3 and 4 to be sent.
, 141 is received, the CPU requesting data transfer
3 and 4 are notified to the transfer instruction reading unit 12. When the bus management unit 10 detects that the CPU bus 100 is not used, the transfer instruction reading unit 12 detects the CPU address from the specific addresses of the shared memories 5 and 6 corresponding to the CPUs 3 and 4 notified by the data transfer request receiving unit 11. Read the contents. When the transfer command reading unit 12 detects that the data transfer request from the CPUs 3 and 4 is to the CPU 2 according to the content, it notifies the CPU 2 via the CPU bus 100.

When the CPU 2 recognizes from the notification from the data transfer circuit 1 that the data written in the shared memories 5 and 6 is for its own device, the data is transferred from the shared memories 5 and 6 via the CPU bus 100. Read. As a result, data transfer from the CPUs 3, 4 to the CPU 2 is performed.

On the other hand, for example, when the CPU 3 transfers data to the CPU 4, the CPU 3 writes the data to the shared memory 5 via the CPU bus 101, and the shared memory 6 of the transfer destination is written to a specific address of the shared memory 5. The identifier and the data transfer number are written, and the data transfer request signal 131 is output to the data transfer circuit 1. At this time, after outputting the data transfer request signal 131, the CPU 3 can move to another process without waiting until the data transfer is completed.

In the data transfer circuit 1, when the data transfer request accepting section 11 accepts the data transfer request signal 131 from the CPU 3, the transfer instruction reading section 12 is notified of the CPU 3 which has made the data transfer request. When the bus management unit 10 detects that the CPU bus 100 is not used, the transfer command reading unit 12 reads the content from the specific address of the shared memory 5 corresponding to the CPU 3 notified from the data transfer request receiving unit 11. .. The transfer instruction reading unit 12 notifies the data transfer unit 13 that there is a data transfer request from the CPU 3 to the shared memory 6 based on the content.

The data transfer unit 13 includes a transfer command reading unit 12
Data is transferred between the shared memories 5 and 6 in accordance with the notification from. When the data from the shared memory 5 is written in the shared memory 6, the CPU 4 reads the data from the shared memory 6 via the CPU bus 102. This allows the CPU
Data transfer from 3 to the CPU 4 is performed. During this period, the data transfer unit 13 controls the CP by the data transfer unit 13 so that the CPU bus 100 does not conflict between the data transfer circuit 1 and the CPU 2.
While the U-bus 100 is in use, the bus management unit 10 to C
The wait signal 111 is output to PU2. Incidentally, CPU4
When data is transferred from the shared memory 6 to the CPU 3, the data is transferred from the shared memory 6 to the shared memory 5 by the same process as described above.

In this way, when data is transferred from the CPU 3 to the CPU 4, the identifier of the shared memory 6 corresponding to the transfer destination CPU 4 is written in a specific address of the shared memory 5 corresponding to the CPU 3 and the shared memory is written. By performing data transfer between the shared memories 5 and 6 according to the contents of the specific address 5
Data can be transferred between the CPUs 3 and 4 without providing a shared memory between the CPUs 4, that is, without increasing the shared memory. Therefore, data can be transferred between the CPUs 3 and 4 without increasing the number of parts and wiring.

[0018]

As described above, according to the present invention, the second and third central units independently connected to the first and second shared memories respectively connected to the first central processing unit. In the processing device, when data is transferred from the second central processing device to another central processing device, a transfer destination is written in the first shared memory, and when the transfer destination is the third central processing device. By transferring the data in the first shared memory to the second shared memory, it is possible to transfer data between the CPUs without increasing the number of parts and wiring.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

2 is a block diagram showing a configuration of a data transfer circuit between shared memories of FIG. 1. FIG.

[Explanation of symbols]

 1 shared memory data transfer circuit 2 to 4 CPU 5, 6 shared memory 10 bus management unit 11 data transfer request acceptance unit 12 transfer instruction read unit 13 data transfer unit

Claims (1)

Claims: What is claimed is: 1. A first and a second shared memory respectively connected to a first central processing unit, a second central processing unit connected to the first shared memory, and A third central processing unit connected to the second shared memory; and a transfer destination written in the first shared memory when data is transferred from the second central processing unit to another central processing unit. Read means for reading, and transfer means for transferring the data of the first shared memory to the second shared memory when the transfer destination read by the read means is the third central processing unit. A data transfer device characterized by the above.