JPH02133856A - Data transfer device - Google Patents

Abstract

PURPOSE:To improve the data transfer efficiency by using a means to receive the data from a system bus based on the output of a multi-address detecting means as well as the output of an individual access detecting means. CONSTITUTION:An individual address comparator 13 compares the output of an individual address setting circuit 12 with a higher rank bit of a system address bus 9. A multi-address setting circuit 14 decides the multi-address of the resources in a module, while a multi-address comparator 15 compares the output of the circuit 14 with a higher rank bit of the bus 9. Then an intra- module resource access detecting circuit 16 checks the outputs of both comparators 13 and 15 and detects the accesses given to its own module from the bus 9, a system data bus 10, and a system control bus 11. Thus it is possible to obtain a data transfer device having the excellent transfer efficiency of data.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data transfer device, and particularly to a multi-CPU system in which a plurality of modules including a CPU, etc. are connected via a system bus. The present invention relates to a data transfer device suitable for transferring data between modules in a computer.

(Prior Art) Conventionally, data transfer between multiple modules connected via a system bus, such as a multi-CPU system where a CPU board, an I10 board, etc. are connected, has been performed as follows. Ta. That is, when accessing resources in other modules, such as memory in the I10 board, first obtains the right to use the system bus and outputs address signals and control signals, and then in the case of data write, data is added to those signals. Output including the signal. Addresses on the system bus for resources within each module are uniquely determined, and access to resources within the own module is known by an address decoding circuit within each module.

In this case, two separate I
To transfer the same data to the memory of 10 modules,
First, data is transferred from the CPU module to the memory of one module, and then the exact same data is transferred to the memory of another module.

(Problem to be Solved by the Invention) Since the conventional data transfer device is configured as described above, when transferring the same data to the memory of a plurality of other modules, it is necessary to transfer the same data as many times as there are modules. There is a problem that the process has to be repeated and the efficiency of data transfer is very low.

The present invention has been made in view of the above, and its purpose is to incorporate the concept of broadcasting into data transfer so that when the same data is transferred to memories in multiple modules, the data transfer is completed in one go. An object of the present invention is to provide a data transfer device that can improve the efficiency of data transfer.

[Structure of the invention]

(Means for Solving the Problems) The data transfer device of the present invention has an individual address that designates a specific module among a plurality of modules and a broadcast address that designates all modules in a specific area of a system bus. selectively transmitting means; individual address setting means provided in the plurality of modules for setting individual addresses for each module; individual access detection means for detecting that individual accesses are being made to its own modules; broadcast address setting means provided in the plurality of modules for setting broadcast addresses; broadcast detection means for detecting that a broadcast access to its own module is being made to the system bus by comparing the set address of the broadcast address setting means; and means for receiving data from the system bus to a corresponding module based on the output.

(Function) By sending an individual address or broadcast address from a master module connected to the system bus to a specific area of the system bus, a specific module or all modules are selected from among multiple modules.
Data may be transferred to a specific module or broadcast to all modules.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

The drawing is a block diagram of a data transfer device according to an embodiment of the present invention. As shown in the figure, a plurality of modules have a system address bus 9 and a system data bus 10.
and are commonly connected via the system control bus 11. On the other hand, in each module, local C
A PUI is connected in a separate module via an address bus 3, a data bus 4 and control signals 5 to a local memory 2 which is accessed only by the CPUI. The CPU further includes an address buffer 6 connected to a system address bus 9, a data transceiver 7 connected to a system data bus 10, a system bus access controller 8 connected to a system control bus 11, and a shared memory. The shared memory access controller 17 is connected to the shared memory access controller 18 . On the other hand, the individual address setting circuit 12 determines individual addresses for intra-module resources in the system space. The individual address comparator 13 compares the output of the individual address setting circuit 12 with the upper bits of the system address bus 9. The broadcast address setting circuit 14 determines the broadcast address of sources within the module. The broadcast address comparator 15 is
The output of the broadcast address setting circuit 14 and the upper bits of the system address bus 9 are compared.

The intra-module resource access detection circuit 16 inspects the output of the individual address comparator 13 and the output of the broadcast address comparator 15, and determines whether the system address bus 9,
It detects access to its own module from the system data bus 10 and system control bus 11.

The shared memory 18 is accessed from the local CPUI and system address bus 9, system data bus 10, and system control bus 11 through the shared memory access controller 17 based on the output of the intra-module resource access detection circuit 16. It is.

In this configuration, its operation will be explained next.

Broadcast transfer of data from a master module to memories in a plurality of other modules is performed as follows.

That is, after the master module acquires the right to use the system bus, the master module writes all the upper bits of the broadcast address, for example, "
1” and starts data transfer.

In other modules other than the master module, the output of the broadcast address setting circuit 14 and the upper bit data of the system address bus 9 are connected to the broadcast address comparator 15.
, and the results are transmitted to the intra-module resource access detection circuit 16. When the intra-module resource access detection circuit 16 detects an access to its own module, it notifies the shared memory access controller 17 of the access, and enables the shared memory 18 to be accessed. When writing from the system data bus 10 to the shared memory 18 is completed, the shared memory access controller 17 uses the system control bus 11 to notify the end of the transfer.

Next, a method for transferring data to shared memory 18 within a specific module will be described. In this case, the individual address setting circuit 12 holds a unique address corresponding to each module. Each module compares the output of the individual address setting circuit 12 with the upper bits of the system address bus 9 using an individual address comparator 13. If they match, the result is transmitted to the intra-module resource access detection circuit 16. When the intramodule resource access detection circuit 16 detects an access to its own module, it notifies the shared memory access controller 17 of the access, and enables the shared memory 18 to be accessed. When data has been written from the system data bus 10 to the shared memory 18, the shared memory access controller 17
uses the system control bus 11 to notify the end of the transfer.

As described above, whether data is transferred to a specific module among multiple modules or data is transferred to all modules, the system address bus 9
It is possible to transfer data to a specific module or to all modules in a single data transfer, simply by determining whether the address to be set is an individual address or a broadcast address.

With such a configuration, even when a bridge connecting LANs is configured with a multi-CPU system, it is possible to efficiently perform data broadcast transfer.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to transfer data from a master module connected to a system bus to memories in multiple other modules at once, resulting in highly efficient data transfer. You can get data transfer.

[Brief explanation of the drawing]

The drawing is a block diagram of a data transfer device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... CPU, 2... Local memory, 3... Address bus, 4... Data bus, 5... Control signal, 6... Address buffer, 7... Data transceiver, 8... System bus access controller, 9... System address bus, 10... System data bus, 11... System control bus, 12... Individual address setting circuit, 13... Individual address comparator , 14...Broadcast address setting circuit, 15...Broadcast address comparator, 16.
...Resource access detection circuit in Mogenir, 17...
- Shared memory access controller, 18... shared memory.

Claims (1)

[Claims] means for selectively transmitting an individual address for specifying a specific module among the plurality of modules and a broadcast address for specifying the broadcasting of all the modules to a specific area of the system bus; an individual address setting means for setting an individual address of the system bus, and an individual address setting means for detecting that individual accesses to the own module are being made to the system bus by comparing a specific area of the system bus with an address set by the individual address setting means. access detection means; broadcast address setting means provided in the plurality of modules for setting broadcast addresses; broadcast detection means for detecting that a module is being accessed for broadcast; and data from the system bus is received by the corresponding module based on the output of the individual access detection means and the output of the broadcast detection means. A data transfer device comprising: means.