JPS63149748A - Storage device - Google Patents

Abstract

PURPOSE:To easily obtain a duplexed memory by using a part of an address signal different from a module address to form a new specification bit. CONSTITUTION:When module addresses defined by a part of address signals are differently applied, all modules execute writing, reading and the transfer of prescribed information to a bus, and when the same module address is applied to n modules >2, (n-1) modules distinguished by a part of address signals different from the module address are constituted so as not to transfer all information to the bus at the time of writing and reading operation. Consequently, the duplexed memory can be easily obtained and a memory device with high reliability can be constituted. In addition, only a part of the memory device can be duplexed in accordance with the contents of the used memory and effective utilization of a memory resource can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device in an information processing device, and particularly to a storage device consisting of a plurality of modules.

[Conventional technology]

Conventionally, in this type of storage device consisting of a plurality of modules, each module has been assigned a unique module address corresponding to a physical address. Each module reads or writes when the read or write address matches the module address. Furthermore, in addition to response signals, data and error signals are transferred to the request source when reading, and error signals are transferred when writing. Each module aborted the -off operation when the read or write address did not match the module address.

[Problem that the invention seeks to solve]

In the above-mentioned conventional storage device, a module that executes reading or writing is defined only by the module address, so it is difficult to realize a dual memory using a plurality of modules. Therefore, there is a drawback that it is impossible to construct a highly reliable memory device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a storage device that can easily realize a dual memory and configure a highly reliable memory device.

[Means for solving problems]

The present invention provides a method for connecting a plurality of modules (
(i) in a storage device consisting of a memory module)
When different module addresses defined by part of the address signal are given, all modules write or read and transfer specified information to the bus, and (ii) 2 or more n modules When the same module address is given, n that is distinguished from this module address by a part of the address signal is different from this module address.
- One module is configured so that some information is not transferred onto the bus during write and read operations.

Therefore, when the same module address is given to 2 or more n modules, one module performs a write or read operation and transfers predetermined information to the bus, and another module performs only a write or read operation and transfers the specified information to the bus. By selectively obtaining n-1 modules that do not perform some information transfer operations, a duplex memory can be easily realized and a highly reliable memory device can be constructed. Furthermore, depending on the memory contents used, only a portion of the memory device can be made into a dual memory, thereby making effective use of memory resources.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a system connection diagram showing an embodiment of a storage device according to the present invention.

In the figure, an address/data bus 1 is connected to a storage device 2 and other processors, such as a central processing unit (CP[J) 3,
This is for connecting to an input/output control device (IOP) 4. Note that the address bus and data bus may be separate buses.

The first memory module 6-1 to the Nth memory module 6-N constitute the storage device 2.

FIG. 2 is a bit arrangement diagram showing the address bits of the address/data bus (hereinafter simply referred to as bus) 1 in FIG. 1. The bits consist of a standby priority designation bit, a module address bit, and a chip address bit.

Here, the module address bits and chip address bits are the same as in the prior art, and in the example of this figure, IGB
(Kigabytes) can be specified. The standby priority designation bit is a bit for a dual memory device. In normal usage, when each memory module is given an individual module address and performs reading or writing, the standby priority designation bits in the address bits for each memory module are, for example, all "0". In this example, the wait priority designation bit is 2 bits, but it can be changed as necessary.

Next, the case of configuring a duplex memory device will be described. Now, hypothetically, the first memory module 6-1 and the second memory module 6-2 constitute a duplex memory, and the
Assume that the memory module Fi-N of is another unique memory. In this case, each address is given as follows. Here, the rXJ mark indicates that it is arbitrary.

First memory module 6-1 Second memory module 6-2 010QOOOOOOOOXX...×Nth memory module 5-N 00000000001xX...×Now, if
When transferred from the CPU 3 to the storage device 7 via the bus 1, the first memory module 6-1 executes a read or write operation and also transfers a response signal onto the bus 1 if necessary. Furthermore, during reading, read data and error signals are transferred onto bus 1. On the other hand, the second
Since the memory modules 6-2 have the same module address, they execute read and write operations, but because their wait priority designation bits are different, some signals, including response signals, are not transferred onto the bus 1. That is, it plays the role of standby memory in the duplex memory device.

On the other hand, since the Nth memory module 6-N has different module address bits, even if the address is transferred from the CPLI 3, it completely ignores this and does nothing.

From the above explanation, it is easy to provide a plurality of memory modules as standby memory.

Now, if the first memory module 6-1 were to fail, the CPU 3 would detect this and transfer the address bits 01000000000XX . . . in the next access. This allows the second memory, which was previously the standby memory, to
The memory module 6-2 is the first memory module 6.
-1 backup is performed and the system does not interrupt the job. Therefore, the reliability of the system is maintained high.

As can be seen from the above explanation, a memory module that defines a standby priority designation bit, which is different from the module address bit of the conventional technology, in the address bit, and performs a read or write operation and a transfer operation on bus l according to the designation of this bit. By selectively obtaining memory modules that perform only read and write operations and do not perform some transfer operations on bus l, it is possible to easily realize duplex memory and configure a highly reliable memory device. can.

〔Effect of the invention〕

As described above, according to the present invention, by providing a new designation bit in a part of the address signal different from the module address, it is possible to easily realize a duplex memory, thereby configuring a highly reliable memory device. be able to.

Further, according to the present invention, by taking advantage of the characteristics of the module memory, only a portion of the storage device can be duplicated depending on the memory contents to be used, which is very useful for effectively utilizing memory resources.

[Brief explanation of the drawing]

Fig. 1 is a system connection diagram showing one embodiment of the present invention;
This figure is an address bit arrangement diagram of the address/data bus shown in FIG. 1. ■・・・Address/data bus, 2・・・・・・
Storage device, 3...Central processing unit (CPU), 6-1 to 6-
N...Memory module. Applicant: NEC Corporation Representative

Claims (1)

[Claims] In a storage device consisting of multiple modules connected on the same bus, if different module addresses defined by part of the address signal are given, all the modules can write or read data and send a specified message to the bus. When information is transferred and the same module address is given to 2 or more n modules, the n-1 modules that are distinguished by a part of the address signal different from the module address will perform write and read operations. A storage device characterized in that it is configured so that some information is not transferred onto a bus during operation.