JPS61184645A - Interruption control system - Google Patents

Abstract

PURPOSE:To improve the processing capacity and reliability of the whole of the system by controlling the corresponding terminal by a CPU only which can read up to the interruption classification, out of the CPU which receives the interruption starting from plural terminals. CONSTITUTION:When the first interruption occurs from an input output terminal 1-1, the interruption signal INT1 is inputted to interruption circuits 5-1-5-3, of CPU3-1-3-3. The CPU3-1, which completes earliest the instruction, is connected with an internal local bus 7-1 and a global bus 8, the bus 8 is occupied by the interruption access, interruption information A1 from an input output terminal 1-1 is read, interruption confirming information B1 is sent and the interruption processing of the terminal 1-1 is executed. At such a time, the CPU3-2, after the bus 8 is occupied, executes the usual internal processing after the spurious action timing. The CPU3-3 also occupies the bus 8 after the bus 8 is occupied, and executes the interruption processing of an input output terminal 1-2. When the second interruption of the terminal 1-1 occurs, the CPU3-2 occupies the bus 8, and the information A1 is read from the terminal 1-1 and the interruption processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for input/output terminals in a multi-CPU system, and particularly to an interrupt control method for linking one CPU and one terminal.

[Conventional technology]

Conventionally, in this type of interrupt control method, interrupt signal lines from multiple terminals are condensed to a dedicated panel, and a specific CPU reads information from that dedicated panel and issues a command to one of the other CPUs. A commonly used method is to access the input/output terminal of the CPU and perform interrupt processing.

[Problem that the invention seeks to solve]

In the conventional interrupt control method in the multi-CPU system described above, the CPU functions are divided into management and execution, and there is a panel for concentrating interrupt signals, so it is vulnerable to failures in the concentrator and the management CPU. In addition, the process is performed in two stages, which has the disadvantage of lowering efficiency.

The purpose of the present invention is to prevent the above-mentioned CPU function dispersion,
An object of the present invention is to provide an interrupt control method that improves the processing capacity and reliability of the entire system. CP of
All U's are connected to the same level by the interrupt signal line and the bus, and only the CPU that detects the interrupt signal earliest monopolizes the bus and performs interrupt control.

That is, the present invention provides an interrupt signal line used for wire-ORing interrupt signals from each of a plurality of terminals and sending it to a plurality of CPUs, and an It is equipped with a bus used for exchanging interrupt type information and interrupt confirmation information, and when one of the terminals sends interrupt type information along with an interrupt signal, the CPU finishes its internal processing first. The CPU reads this interrupt type information and
It is characterized in that it occupies the bus, sends interrupt confirmation information to the terminal, and performs interrupt processing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system diagram to which an embodiment of the interrupt control method according to the present invention is applied. Interrupt control circuits 2-1 to Z-n provided in each of a plurality of (n in this embodiment) input/output terminals 1-1 to 1-n are connected to a common global bus 8, respectively. , are connected to a common interrupt signal line 9.

In this case, the interrupt signals INT, ~INTn from each of the input/output terminals 1-1 to 1-n are wired-OR (w
ired OR) and enters the interrupt signal line 9.

On the other hand, a plurality of (eight in this embodiment) CPUs 8-1 to 8
-8 are respectively input to the central processing units 4-1 to 4-B and the interrupt signals INT, to I, which are input via the interrupt signal line 9.
NTn is input to each central processing unit 4-1 to 4-3.
interrupt circuits 5-1 to 5-3, buffer circuits 6-1 to 6-s connected to global bus 8, central processing units 4-1 to 4-8, and buffer circuits 6-1 to 6-6. -3 are provided with local buses 7-1 to 7-8 for signal transmission.

FIG. 2 is a diagram showing an example of interrupt control timing,
The interrupt control method will be explained below in conjunction with FIG. 1.

First, when the first interrupt occurs from the input/output terminal 1-1, the interrupt signal lNT1 is sent to the CP via the interrupt signal line 9.
Interrupt circuits 5-1 to 5- of U 3-1 to 8-3, respectively
The CPU 8-1 that completed the instruction (INST) operation earliest among the operating CPUs connects the gate of its buffer circuit 6-1 with the internal local bus 7-1 and the global bus 8, and connects the gate of the buffer circuit 6-1 with the global bus 8. bus 8
is occupied by the interrupt access (INTA) operation, and the interrupt type information A is read from the input/output terminal 1-1, and the output of the interrupt signal line 9 of the input/output terminal 1-1 is returned to its original state, i.e. , sends interrupt confirmation information B1, and input/output terminal 1-
1 interrupt processing is executed. At this time, the CPU 8-11 performs the INTA operation when its own INST operation is completed, and occupies the global bus 8 after the CPU 8-IK finishes occupying the global bus 8. However, interrupt type information A is received from the input/output terminal 1-1.

cannot be read, the global bus 8 is relinquished and normal internal processing (
INST operation) is resumed. Similarly for CPU8-8
When the CPU 3-s finishes occupying the global bus 8, it attempts to occupy the global bus 8 and read the interrupt type information. At this time, an interrupt signal INT is generated at the input/output terminal 1-s, and in response to the INTA operation of the CPU 8-8, the input/output terminal 1-3 transmits the interrupt type information 4 to the CP.
In order to cause the U 8-II to read the data, the CPU 8-8 executes interrupt processing for the input/output terminal 1-s.

When the second interrupt occurs from the input/output terminal 1-1, the CPU 8-1 completes the INST operation earliest compared to other CPUs, so it occupies the global bus 8 and executes the INTA operation. The interrupt type information A is read from the input/output terminal 1-1 and the corresponding interrupt processing is executed.

〔Effect of the invention〕

As explained above, in the present invention, only the CPU that can read the interrupt type in response to an interrupt activation from multiple terminals controls the terminal, thereby only distributing the CPU load in a multi-CPU system. - This has the effect of improving the throughput and reliability of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a system to which an embodiment of the interrupt control method according to the present invention is applied, and FIG. 2 is a diagram showing an example of interrupt control timing. 1-1 to l-n... Input/output terminals. g-1-2-n...Interrupt control circuit. 3-1 to 8-8...CPU. 4-1~←8...Central processing unit. 5-1 to 5-8... Interrupt circuit. 6-1 to 6-8...Buffer circuit. 7-1 to 7-8...Local bus. 8 ・・・・・・・・・Global bus. 9 ...... Interrupt signal line. lNT1 to INTn...Interrupt signal. A, ~ An... Interrupt type information. B1 ~ B,...Interruption confirmation information.

Claims (1)

[Claims] An interrupt signal line used for wire-ORing interrupt signals from each of a plurality of terminals and sending it to a plurality of CPUs, and between the plurality of terminals and the plurality of CPUs. a bus used for exchanging interrupt type information and interrupt confirmation information, and when any of the terminals sends the interrupt type information together with the interrupt signal, one of the CPUs Interrupt control characterized in that a CPU that finishes internal processing earliest reads the interrupt type information, occupies the bus, sends the interrupt confirmation information to the terminal, and performs interrupt processing. method.