JPH02249054A - Data processor - Google Patents

Abstract

PURPOSE:To successively execute an interruption processing from a central processing unit whose priority order is decided by installing arbitration circuits in respective central processing units. CONSTITUTION:The arbitration circuits 101-108 are installed in respective central processing units 11-18, and respective lines of data buses 201-208 are allocated and are respectively connected. Then, selection signals are outputted from the arbitration circuits which have simultaneously received interruption requests from outside and the interruption requests for the arbitration circuit which does not have received the interruption request is locked. The priority order is decided in the arbitration circuits 101-108 which have simultaneously received the interruption requests, and the arbitration circuit whose priority order is decided outputs an interruption command to interruption start circuits 21-28 belonging to the central processing unit, and outputs interruption information to the standby bit of an interruption register through an allocated route. Thus, the interruption processing is executed from the central processing unit whose priority is decided even if the interruption requests are simultaneously generated from outside to plural central processing units 11-18 so as to attain the interruption processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device composed of a plurality of central processing units.

[Conventional technology]

FIG. 2 is a system diagram showing the electrical circuit connection system of a conventional data processing device disclosed in, for example, Japanese Unexamined Patent Publication No. 63-26421. 21 to 2n are interrupt activation circuits that output an interrupt activation signal and an interrupt activation prohibition signal in response to an interrupt command; 31 to 3n are interrupt activation signal lines; 41 to 4n;
51 to 5n are logic gates that perform AND operations; 61 to 6n are interrupt registers that have a specific bit that sets the binary signal output from this logic gate; and other reserved bits; 71 to 7n are specific bits of this interrupt register, and 81 to 8n are specific bits 71 to 8n of this interrupt register.
This interrupt processing section is activated and executes interrupt processing when a binary signal of 1 is set to 7n.

Next, the operation will be described. As an example, a case will be described in which the central processing unit 11 issues an interrupt to the other central processing units 12 to In. First, the interrupt activation circuit 21 is activated by an external interrupt command, and outputs an interrupt activation signal and an interrupt activation prohibition signal. The former is the interrupt activation signal line 31
In addition, the latter is input to the logic gate 51 via the interrupt activation inhibit signal line 41, performs AND, and sets the binary signal 0 to the specific bit 71 of the interrupt register 61, while also inputting it to the other central processing unit. 12 to 1n logic gates 52
- Input to 5n. Since the six interrupt activation circuits 22 to 2n of the other central processing units 12 to 1n do not output an interrupt activation signal or an interrupt activation prohibition signal, the logic gates 51 to 1n output no interrupt activation signal or interrupt activation inhibit signal.
5n performs logical AND and converts the binary signal 1 to specific bits 72 to 7n of respective interrupt registers 62 to 6n.
Set to . The interrupt processing unit 81 of the central processing unit 11 does not start because the specific bit 71 of its interrupt register 61 is set to 0, and the interrupt processing units 82 to 8n of the other central processing units 12 to 1n do not start up the interrupt processing unit 81 of the central processing unit 11. 6n
Since 1 has been set in the specific bits 72 to 7n, the CPU is activated and executes interrupt processing. In this way, the central processing unit 11 issues an interrupt to the other central processing units 12 to 1n. The same applies to the case where the central processing unit 12 issues an interrupt to the other central processing units 11.13 to 1n.

[Problem to be solved by the invention]

Since the conventional data processing device is configured as described above, a single central processing unit, for example, the central processing unit 1 that receives an interrupt command,
1 can issue an interrupt to the other central processing units 12 to 1n, but if multiple central processing units receive an interrupt command at the same time, it is impossible to issue an interrupt to the other central processing units, which is a problem to be solved. there were.

This invention was made in order to solve the above-mentioned problem, and the priority order is determined by a plurality of central processing units that receive interrupt requests simultaneously from the outside, and the central processing unit that has decided on the priority interrupts the other central processing units one after another. An object of the present invention is to obtain a data processing device that can interrupt a central processing unit of the computer and execute interrupt processing.

[Means to solve the problem]

The data processing device according to the present invention includes an interrupt activation circuit that outputs an interrupt activation signal and an interrupt activation prohibition signal in response to an interrupt command, and performs a logical product with the interrupt activation signal as an affirmative input and the interrupt activation prohibition signal as a negative input, and a binary signal. A logic gate that outputs 0 or 1, an interrupt register that has a specific bit that sets a binary signal of 0 or 1, and other reserved bits, which is activated when a binary 1 is set to a specific bit, and sets the reserved bit to In a device consisting of a plurality of central processing units each equipped with an interrupt processing unit that executes interrupt processing in response to set interrupt information, each central processing unit is provided with an arbitration circuit to allocate each line of the data bus. The arbitration circuits that received interrupt requests from the outside at the same time output selection signals to lock the external interrupt requests to the arbitration circuits that did not receive the interrupt requests, and the arbitration circuits that received interrupt requests at the same time output selection signals. A circuit exchanges step signals through each line, determines the priority of the step signal according to a predetermined priority for each line, and an arbitration circuit for the prioritized step signal generates an interrupt belonging to the central processing unit. At the same time as outputting an interrupt command to the startup circuit, interrupt information is output to the reserved bit of the interrupt register through the assigned line.

[Effect]

In this invention, when the arbitration circuit receives interrupt requests simultaneously from the outside, it outputs a selection signal, locks the external interrupt requests to the arbitration circuits that have not received the interrupt request, and also outputs the selection signal through each line of the data bus. When the signals are exchanged and the step signal priority is determined according to the predetermined priority for each line, the step signal arbitration circuit that has determined the priority outputs an interrupt command to the interrupt activation circuit belonging to the relevant central processing unit. at the same time,
Interrupt information is output to the reserved bits of the interrupt register through the assigned line.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 11-18.21-28.31-38.4
1-48.51-58.61-68.71-7B, 81
88 are the same as the conventional data processing device described above. Arbitration circuits 101 to 108 output a selection signal and a step signal when receiving an interrupt request from the outside, and also receive step signals from other arbitration circuits that received an interrupt request at the same time to determine a predetermined priority order. The priority order is determined according to the priority order, and when the priority is determined, an interrupt command is output. 2
01-208 is a data bus consisting of 8 lines, 30
1 to 308 are selection signal lines.

This embodiment consists of eight central processing units.

Next, the operation will be explained. For example, when two central processing units 11 and 13 receive an interrupt request from the outside at the same time,
A case will be described in which the central processing unit 11 issues an interrupt with priority over the central processing unit 13 and executes interrupt processing.

First, when the central processing unit [1.13] simultaneously receives an interrupt request from the outside, the arbitration circuits 101 and 103 confirm that there is no selection signal on the selection signal line 301 and 308, output a selection signal, and receive the interrupt request. Arbitration circuit 102.
Arbitration circuits 101 and 103 lock interrupt requests from the outside for data buses 104 to 108, and arbitrate circuits 101 and 103 among the eight tree lines from bit 1 to bit 8 of data buses 201 to 208.
Step signals are exchanged through the bit 7 line and the bit 3 line respectively assigned to .

Arbitration circuits 101 to 10 are arranged on eight lines of data buses 201 to 208, with priority determined from the one with the largest number of bits.
8, each arbitration circuit 101-108 determines the priority depending on whether or not there is a step signal on a line with a larger number of bits than the assigned line.

Since there is no step signal on the bit 8 line, the arbitration circuit 101 determines priority and outputs an interrupt command to the interrupt starting circuit 21, and also outputs an interrupt command to the data buses 201 to 208 (7) 8.
Interrupt information is set in reserved bits of interrupt registers 61-68 through wooden lines.

Since there is a step signal on the bit 7 line, the arbitration circuit 103 yields priority to the arbitration circuit 101 and selects the selection signal line 3.
The output of the selection signal to bit 3 of the data bus 203 and the step signal to the line of bit 3 of the data bus 203 are stopped. after that,
The arbitration circuit 103 is in a standby state until there is no selection signal on the selection signal line 303.

The interrupt activation circuit 21 receives an interrupt command and outputs an interrupt activation signal and an interrupt activation prohibition signal, the former as a positive input via the interrupt activation signal line 31, and the latter as a negative input via the interrupt activation prohibition signal line 41. logic gate 51
, and performs logical AND to set the binary signal 0 to the specific bit 71 of the interrupt register 61. Further, the interrupt activation signal outputted from the interrupt activation circuit 21 is sent to each logic gate 5 as a positive input via interrupt activation signal lines 31 to 38.
However, since the interrupt activation circuits 22 to 28 are not outputting either an interrupt activation signal or an interrupt activation inhibit signal, each logic gate 52 to 58 performs an AND operation to convert the binary signal to 1. Specific bit 7 of interrupt registers 62-68
Set to 2-78.

The interrupt processing unit 81 selects specific bit 7 of the interrupt register 61.
Since 1 is set to 0, the interrupt processing corresponding to the interrupt information set in that reserved bit is not executed.
Since the specific bits 72-78 of the interrupt registers 62-68 are set to 1, the interrupt processing units 82-88 execute interrupt processing corresponding to the interrupt information set in the child bit.

When the interrupt processing is finished, the arbitration circuit 101 selects the selection signal line 301.
The selection signal to the interrupt activation circuit 21, the interrupt command to the interrupt starting circuit 21, and the output of interrupt information to each line of the data bus 201 are stopped, and the interrupt processing executed by the central processing bag @11 with priority over the central processing unit 13 is executed. Complete.

Next, the arbitration circuit in the standby state]03 is the selection signal line 3
Since there is no longer a selection signal in 01, the arbitration circuit 1 outputs a selection signal to the selection signal line 303 and completes the interrupt processing.
01 and the arbitration circuit 102.10 that did not receive an interrupt request.
4 to 108 are locked against external interrupt requests, and a step signal is output to the bit 3 line assigned to the arbitration circuit 103.

Since there is no step signal on each line from bit 4 to bit 8, the arbitration circuit 103 outputs an interrupt command to the interrupt activation circuit 23 and also outputs an interrupt command to the data buses 201 to 8 of the data buses 201 to 208.
Interrupt information is set in reserved bits of interrupt registers 61-68 through wooden lines.

The interrupt activation circuit 23 receives an interrupt command and outputs an interrupt activation signal and an interrupt activation prohibition signal. The signal is input to the logic gate 53 as an input, and a logical AND operation is performed to set the binary signal 0 to the specific bit 73 of the interrupt register 63. Further, the interrupt activation signal outputted from the interrupt activation circuit 23 is input to each logic gate 51.52.54-58 as a positive input via the interrupt activation signal lines 31-38. Since neither the interrupt start signal nor the interrupt start inhibit signal is output from 5, each logic gate 5
1.52. Execute the logical product at 54 to 58 to convert the binary signal to 1.
are set in specific bits 7], 72, 74-78 of interrupt registers 61, 62, 64-68.

The interrupt processing unit 83 selects specific bit 7 of the interrupt register 63.
3 is set to O, so the interrupt processing corresponding to the interrupt information set in that reserved bit is not executed.
Interrupt processing units 81.82.84-88 use specific bits 71.72.74 of interrupt registers 61.62.64-68.
Since 1 is set in .about.78, interrupt processing corresponding to the interrupt information set in the reserved bit is executed.

When the interrupt processing is finished, the arbitration circuit 103 selects the selection signal line 303.
stop outputting the selection signal to the interrupt starting circuit 23, the interrupt command to the interrupt starting circuit 23, and the interrupt information to each line of the data 203;
The central processing unit 13 also completes the interrupt processing.

In the above embodiment, it is assumed that eight central processing units are used, and the data bus is made up of eight lines. Although the bit 3 line is assigned, it goes without saying that this is not limited to this.

〔Effect of the invention〕

As described above, according to the present invention, each of the plurality of central processing units is provided with an arbitration circuit, each line of the data bus is assigned and interconnected, and each of the arbitration circuits receives an interrupt request from the outside at the same time. A signal is output to lock external interrupt requests to arbitration circuits that have not received an interrupt request, and at the same time, step signals are exchanged through each line in the arbitration circuit that received an interrupt request, and step signals are set in advance for each line. The arbitration circuit for the step signal that has determined the priority outputs an interrupt command to the interrupt activation circuit belonging to the central processing unit, and at the same time outputs the interrupt command to the interrupt register via the assigned path. Since interrupt information is output to bits, even if multiple central processing units receive interrupt requests from the outside at the same time, the priority is determined, and the central processing unit that has determined the priority will interrupt the other central processing units one after another. This has the effect of being able to execute interrupt processing.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing a connection system of electric lines in an embodiment of the present invention, and FIG. 2 is a system diagram showing a connection system of electric lines in a conventional data processing device. In the figure, 11 to 1n are central processing units, 21 to 2n are interrupt activation circuits, 31 to 3n are interrupt activation signal lines, and 41
~4n are interrupt activation inhibit signal lines, 51~5n are logic gates, 61~6n are interrupt registers, 71~7n are specific bits, 81~8n are interrupt processing units, 201~208 are data buses, 301~308 are This is a selection signal line. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] An interrupt activation circuit outputs an interrupt activation signal and an interrupt activation prohibition signal in response to an interrupt command, and performs logical product with the interrupt activation signal as an affirmative input and the interrupt activation prohibition signal as a negative input, and a binary signal of 0 or 1. A logic gate that outputs, an interrupt register that has a specific bit that sets the binary signal to 0 or 1, and other reserved bits, which is activated when the binary number 1 is set to the specific bit, and sets the reserved bit. In a device consisting of a plurality of central processing units, each of which is equipped with an interrupt processing unit that executes interrupt processing in response to interrupt information received, each central processing unit is provided with an arbitration circuit, and each line of the data bus is assigned. The arbitration circuits connected to each other and receiving interrupt requests from the outside at the same time output selection signals to lock interrupt requests from the outside to the arbitration circuits that did not receive an interrupt request, and simultaneously received interrupt requests. The arbitration circuit exchanges step signals through each of the lines, determines the priority order of the step signals according to a predetermined priority order for each line, and the arbitration circuit of the step signal that has determined the priority. A data processing device characterized in that, at the same time as outputting the interrupt command to the interrupt activation circuit belonging to the central processing unit, outputting the interrupt information to a spare bit of the interrupt register through the assigned line.