CN110875867A

CN110875867A - Bus access arbitration device and method

Info

Publication number: CN110875867A
Application number: CN202010062269.8A
Authority: CN
Inventors: 张威龙; 邓廷; 李鹏; 钟书鹏
Original assignee: Nanjing Lingu Chuang Chuang Electronics Co Ltd
Current assignee: Nanjing Lingu Chuang Chuang Electronics Co Ltd
Priority date: 2020-01-20
Filing date: 2020-01-20
Publication date: 2020-03-10
Anticipated expiration: 2040-01-20
Also published as: CN110875867B

Abstract

The invention discloses a bus access arbitration device, which comprises a plurality of stages of arbitration modules, wherein each arbitration module comprises two request acceptance units, an authorization arbitration unit and an access control unit; the request receiving unit is used for generating an idle state signal of the slave device according to the fed back authorization state signal and whether the slave device is idle or not and sending the idle state signal to the corresponding master device when receiving a command address request sent by the connected master device or the arbitration module; the authorization arbitration unit is used for sending an authorization state signal to the access control unit and the request receiving unit according to the priority; the access control unit is used for allowing the authorized main equipment to perform command address access and data access according to the authorization state signal. The invention also discloses a bus access arbitration method. The invention can realize zero-lag arbitration.

Description

Bus access arbitration device and method

Technical Field

The invention relates to a microcontroller technology, in particular to a bus access arbitration device and a bus access arbitration method.

Background

Microcontroller design is a broad field of digital integrated circuit design. Generally, a microcontroller will include at least one Central Processing Unit (CPU) for a series of operations such as basic arithmetic operations, instruction access, program branch jump control, interrupt response, and special flag bit maintenance, and the CPU is the main control unit of the entire microcontroller. The central processing unit accesses various storage resources and peripheral modules in the microcontroller through the bus, and is used as a master device on the bus, and is responsible for initiating an access command, transmitting written data and receiving read-back data, and needs to process abnormal error feedback and the like on the bus. In many microcontroller designs, however, there may be more than one bus master. Typically, a direct memory access controller (DMAController) may also initiate various access operations on the bus without the intervention of a central processor. Even some microcontrollers or systems on a chip (SoC) have multiple central processing units. When a plurality of masters access a slave (such as a peripheral module or a storage device) at the same time, due to the limited acceptance capability of the bus interface of the accessed slave or the limited throughput rate of the accessed slave, the system design needs to determine which master can currently obtain the access right according to a certain priority, and other masters accessing in the same period need to be informed of waiting until the access of the preferred master is finished, that is, access arbitration. However, the current access arbitration processing speed is slow and the delay is large.

Disclosure of Invention

The purpose of the invention is as follows: the invention provides a bus access arbitration device and a bus access arbitration method aiming at the problems in the prior art, and realizes zero delay of main equipment arbitration access.

The technical scheme is as follows: the bus access arbitration device of the present invention is a device through which buses of a plurality of masters are connected to a slave, characterized in that: the device comprises a plurality of levels of arbitration modules, wherein every two main devices are connected to one level of arbitration module, every two level of arbitration modules are connected to one level of arbitration module, and the rest of the arbitration modules with the highest levels are connected to slave devices; each arbitration module comprises two request receiving units, an authorization arbitration unit and an access control unit, each request receiving unit is connected with a main device or an arbitration module, the authorization arbitration unit is connected with the two request receiving units, and the access control unit is connected with the authorization arbitration unit;

the request accepting unit is used for generating an idle state signal of the slave device according to the authorization state signal fed back by the authorization arbitration unit and whether the slave device is idle or not when receiving a command address access request sent by the connected master device or the arbitration module, and sending the idle state signal to the corresponding master device; the authorization arbitration unit is used for sending an authorization state signal to the access control unit and the request receiving unit according to the priority; the access control unit is used for allowing the authorized main equipment to perform command address access and data access according to the authorization state signal. And if the number of the main devices is singular, connecting the last remaining main devices as an arbitration module.

Further, the request accepting unit is specifically configured to:

when receiving a command address access request signal sent by the connected master device or the arbitration module at the lower level:

if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave device idle state signal sent by the slave device is idle, sending the slave device idle state signal with the idle state to the connected master device or arbitration module in the current bus period, generating an access request signal and sending the access request signal to the authorization arbitration unit, and in the next bus period, generating the access request signal and sending the access request signal to the authorization arbitration unit when the state of the bus idle state signal corresponding to the master device is idle, otherwise, waiting until the state of the bus idle state signal is idle;

if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave equipment idle state signal sent by the slave equipment is busy, sending the slave equipment idle state signal with the busy state to the connected master equipment or arbitration module;

if the state of the command access authorization state signal fed back by the authorization arbitration unit is unauthorized, a slave device idle state signal with a busy state is sent to the connected master device or arbitration module;

and each bus cycle sends a bus idle state signal to the connected grant arbitration unit indicating the bus state of the corresponding master device.

Further, the grant arbitration unit is specifically configured to:

when only receiving an access request signal sent by a first request receiving unit connected with the request receiving unit, sending a command access authorization state signal with an authorized state to the request receiving unit, and sending a command access authorization indication signal to an access control unit, wherein the command access authorization indication signal indicates that a main device corresponding to the request receiving unit is authorized to be accessed by a command address;

when only receiving an access request signal sent by a second connected request receiving unit, sending a command access authorization state signal with an authorized state to the request receiving unit, and sending a command access authorization indication signal to an access control unit, wherein the command access authorization indication signal indicates that a main device corresponding to the request receiving unit is authorized to be accessed by a command address;

when access request signals sent by a first request accepting unit and a second request accepting unit which are connected are received simultaneously, a command access authorization state signal with an authorized state is sent to the request accepting unit corresponding to the master device with higher priority, a command access authorization indicating signal is sent to an access control unit, and the command access authorization indicating signal indicates that the master device with higher priority is accessed by an authorized command address;

when the access request signal of any request accepting unit is not received, the state of the command access authorization state signal of the first request accepting unit is maintained as authorization by default;

when the access request signal of the request accepting unit is received again after the command address access of the main device corresponding to the first request accepting unit is finished, if the state of the bus idle state signal sent by the request accepting unit is idle at the moment, sending a data access authorization indication signal to the access control unit, wherein the data access authorization indication signal indicates that the main device corresponding to the request accepting unit is authorized to access data, otherwise, the state of the bus idle state signal is idle;

when the access request signal of the request accepting unit is received again after the command address access of the main device corresponding to the second request accepting unit is finished, if the state of the bus idle state signal sent by the request accepting unit is idle at this time, a data access authorization indication signal is sent to the access control unit, the data access authorization indication signal indicates that the main device corresponding to the request accepting unit is authorized to access data, and if not, the state of the bus idle state signal is idle.

Further, the access control unit is specifically configured to:

when receiving a command access authorization indication signal of an authorization arbitration unit, allowing a corresponding master device in the command access authorization indication signal to send a bus command address access signal to a slave device or a higher-level arbitration module, wherein the bus command address access signal comprises a command address access request signal and a bus idle state signal which are sent by the corresponding master device;

when receiving the data access authorization indication signal of the authorization arbitration unit, the corresponding master device in the data access authorization indication signal is allowed to send a bus data access signal to the slave device.

Further, the request accepting unit specifically includes a data selector, a D flip-flop, an and gate, an or gate and an inverter, wherein a command access authorization state signal input terminal of the request accepting unit is externally connected with an authorization arbitration unit, a control terminal of the internally connected data selector, an authorization arbitration unit externally connected from an equipment idle state signal input terminal, an access control unit internally connected with an address 1 input terminal of the data selector, a command address access request signal input terminal is externally connected with a master or a lower level arbitration module, an address 0 input terminal of the data selector is internally connected through the inverter, and a first input terminal of the and gate or the and gate is respectively connected, an authorization arbitration unit externally connected from an equipment idle state signal output terminal of the equipment with the master or the lower level arbitration module, an output terminal of the internally connected data selector, and an access control unit externally connected with the master or the lower level arbitration module from a bus idle state signal input terminal, the internal bus idle state signal output end and the second input end of the AND gate are simultaneously connected, the bus idle state signal output end is externally connected with the authorization arbitration unit, the output end of the AND gate is connected with the D end of the D trigger, the Q end of the D trigger is connected with the second input end of the OR gate, the output end of the OR gate is connected with the access request signal output end, and the access request signal output end is externally connected with the authorization arbitration unit.

Further, the authorization arbitration unit specifically includes a first data selector, a second data selector, a D flip-flop, and three inverters, where a first access request signal input terminal of the authorization arbitration unit is externally connected to the first request accepting unit, a control terminal of the first data selector is internally connected to the first data selector, a first bus idle state signal input terminal is externally connected to the first request accepting unit, a 1 address input terminal of the second data selector is internally connected to the second access request signal input terminal, a second request accepting unit is externally connected to the second access request signal input terminal, a 0 address input terminal of the first data selector is internally connected to the first bus idle state signal input terminal through one inverter, a second request accepting unit is externally connected to the second bus idle state signal input terminal, a 0 address input terminal of the second data selector is internally connected to the second bus idle state signal input terminal through one inverter, and a request accepting unit of a slave device or a higher-level arbitration module is externally connected to the device idle state signal input, the first slave device idle state signal output end and the second slave device idle state signal output end are internally connected, the first slave device idle state signal output end and the second slave device idle state signal output end are respectively externally connected with the first request receiving unit and the second request receiving unit, the 1 address input end of the first data selector inputs a priority signal representing the priority of the master device through an inverter, the output end of the first data selector is simultaneously connected with the command access authorization indication signal output end, the control end of the second data selector and the first command access authorization state signal output end, the second command access authorization state signal output end is also connected through an inverter, the command access authorization indication signal output end is externally connected with the access control unit, the output end of the second data selector is connected with the D end of the D trigger, and the Q end of the D trigger is connected with the data access authorization indication signal output end, the data access authorization indication signal output end is externally connected with the access control unit.

Further, the access control unit specifically includes a first data selector and a second data selector, the command access authorization indication signal input end of the access control unit is externally connected with the authorization arbitration unit, the control end of the first data selector is internally connected with the control end of the access control unit, the data access authorization indication signal input end is externally connected with the authorization arbitration unit, the control end of the second data selector is internally connected with the control end of the access control unit, the 1 address input end of the first data selector inputs the bus command address access signal sent by the first master device, the first master device is the master device corresponding to the first request accepting unit connected with the authorization arbitration unit, the 0 address input end of the first data selector inputs the bus command address access signal sent by the second master device, the second master device is the master device corresponding to the second request accepting unit connected with the authorization arbitration unit, the output end of the first data selector is connected with a bus command address access signal output end, the bus command address access signal output end is externally connected with a slave device or a request accepting unit of a higher-level arbitration module, the 1 address input end of the second data selector inputs a bus data access signal sent by the first master device, the 0 address input end of the first data selector inputs a bus data access signal sent by the second master device, the output end of the first data selector is connected with a bus data access signal output end, and the bus data access signal output end is externally connected with the slave device.

Furthermore, each signal input end and each signal output end of each unit in the arbitration module are valid when the signal is at a high level, namely 1, and correspondingly indicate that the signal state is a request, idle or authorized state, and are invalid when the signal is at a low level, namely 0, and correspondingly indicate that the signal state is a no-request, busy or unauthorized state.

The bus access arbitration method of the invention is based on the bus access arbitration device, and comprises the following steps:

when the request receiving unit receives a command address access request sent by the connected main equipment or the arbitration module, the request receiving unit generates an idle state signal of the slave equipment according to the authorization state signal fed back by the authorization arbitration unit and whether the slave equipment is idle or not, and sends the idle state signal to the corresponding main equipment;

the authorization arbitration unit sends an authorization state signal to the access control unit and the request receiving unit according to the priority;

the access control unit allows the authorized master device to perform command address access and data access according to the authorization status signal.

Further, the method specifically comprises the following steps:

s1, the main device sends command address access request signals to the request receiving unit of the connected first-level arbitration module;

s2, the two request receiving units of the first-level arbitration module respectively execute the following steps:

if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave equipment idle state signal sent by the slave equipment is idle, sending the slave equipment idle state signal with the idle state to the connected master equipment or a lower-level arbitration module, generating an access request signal and sending the access request signal to the authorization arbitration unit;

if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave equipment idle state signal sent by the slave equipment is busy, sending the slave equipment idle state signal with the busy state to the connected master equipment or a lower-level arbitration module;

if the state of the command access authorization state signal fed back by the authorization arbitration unit is unauthorized, sending a slave device idle state signal with a busy state to the connected master device or a lower-level arbitration module;

sending a bus idle state signal representing the bus state of the corresponding main equipment to a connected authorization arbitration unit;

s3, the authorization arbitration unit of the first-level arbitration module executes the following steps:

when the authorization arbitration unit only receives an access request signal sent by a first request receiving unit connected with the authorization arbitration unit, a command access authorization state signal with an authorized state is sent to the request receiving unit, and a command access authorization indication signal is sent to the access control unit, wherein the command access authorization indication signal indicates that a main device corresponding to the request receiving unit is authorized to be accessed by a command address;

s4, the access control unit of the first-level arbitration module executes the following steps:

s5, the request accepting unit, the authorization arbitration unit and the access control unit of the second-level arbitration module execute according to the steps S2-S4 until the arbitration module at the highest level sends a bus command address access signal to the slave device and carries out command address access;

s6, the request accepting unit of the first-level arbitration module executes the following steps:

when the state of the bus idle state signal corresponding to the main equipment is idle, generating an access request signal and sending the access request signal to an authorization arbitration unit, otherwise, waiting until the state of the bus idle state signal is idle;

s7, the authorization arbitration unit of the first-level arbitration module executes the following steps:

when the request accepting unit access request signal is received again, if the state of the bus idle state signal sent by the request accepting unit is idle at the moment, sending a data access authorization indication signal to the access control unit, wherein the data access authorization indication signal indicates that the main equipment corresponding to the request accepting unit is authorized to access data, and if not, the state of the bus idle state signal is idle;

s8, the access control unit of the first-level arbitration module executes the following steps:

when receiving the data access authorization indication signal of the authorization arbitration unit, the corresponding master device in the data access authorization indication signal is allowed to send a bus data access signal to the slave device for data access.

Has the advantages that: compared with the prior art, the invention has the following remarkable advantages: the invention realizes zero delay of arbitration access of the main equipment, and adopts a few combinational circuits to realize zero delay function on the realization circuit, thereby reducing the cost.

Drawings

FIG. 1 is a system block diagram of one embodiment of a bus access arbitration device provided by the present invention;

FIG. 2 is a circuit diagram of FIG. 1;

FIG. 3 is a circuit diagram of the request accepting unit of FIG. 2;

FIG. 4 is a circuit diagram of the grant arbitration unit of FIG. 2;

FIG. 5 is a circuit diagram of the access control unit of FIG. 2;

FIG. 6 is a system block diagram of another embodiment of a bus access arbitration device provided by the present invention;

FIG. 7 is a connection diagram of FIG. 6;

fig. 8 is a system block diagram of another embodiment of the bus access arbitration device provided by the present invention.

Detailed Description

Example 1

The present embodiment provides a bus access arbitration apparatus, in the present embodiment, there are two main devices, which are respectively a main device 0 and a main device 1, as shown in fig. 1, buses of the two main devices are connected to a slave device through the bus access arbitration, the bus access arbitration apparatus includes an arbitration module, the two main devices are connected to the arbitration module, and the arbitration module is connected to the slave device; the arbitration module comprises two request receiving units, an authorization arbitration unit and an access control unit, wherein each request receiving unit is connected with one master device, the authorization arbitration unit is connected with the two request receiving units, and the access control unit is connected with the authorization arbitration unit arbitration module and is used for selecting one master device from the two master devices to establish connection with the slave devices. Each unit is described in detail below.

As shown in fig. 2 and 3, two request accepting units, namely, a request accepting unit 0 and a request accepting unit 1, are shared, the request accepting unit 0 is connected to the master 0, the request accepting unit 1 is connected to the master 1, and the two units have the same configuration except that the connected masters are different, and therefore, the request accepting unit 0 will be described as an example. The request receiving unit 0 is configured to generate a slave idle state signal according to the grant state signal fed back by the grant arbitration unit and whether the slave is idle when receiving the command address access request sent by the master 0, and send the slave idle state signal to the master 0. The method specifically comprises the following steps: when receiving a command address access request signal sent by the master device 0: if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave device idle state signal sent by the slave device is idle, sending the slave device idle state signal with the idle state to the master device 0 in the current bus cycle, generating an access request signal and sending the access request signal to the authorization arbitration unit, and in the next bus cycle, generating the access request signal and sending the access request signal to the authorization arbitration unit when the state of the bus idle state signal of the master device 0 is idle, otherwise, waiting until the state of the bus idle state signal is idle; if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave device idle state signal sent by the slave device is busy, sending the slave device idle state signal with the busy state to the master device 0; if the state of the command access authorization state signal fed back by the authorization arbitration unit is unauthorized, a slave device idle state signal with a busy state is sent to the connected master device 0; and sending a bus idle state signal indicative of the bus state of master 0 to the connected grant arbitration unit each bus cycle. The above functions are realized by using circuits, and the request receiving unit 0 specifically includes a data selector mux1, a D flip-flop FF1, an and gate, an or gate and an inverter, wherein the command access authorization state signal input terminal of the request receiving unit 0 is externally connected to an authorization arbitration unit, the control terminal of the data selector is internally connected, the idle state signal input terminal of the slave device is externally connected to an authorization arbitration unit, the 1 address input terminal of the data selector is internally connected, the command address access request signal input terminal is externally connected to the master device 0, the 0 address input terminal of the data selector is internally connected through the inverter, and the first input terminals of the and gate and the or gate are respectively connected, the idle state signal output terminal of the slave device is externally connected to the master device 0, the output terminal of the data selector is internally connected, the bus idle state signal input terminal is externally connected to the master device 0, and the bus idle state signal output terminal and the second input terminal of, the bus idle state signal output end is externally connected with the authorization arbitration unit, the output end of the AND gate is connected with the D end of the D trigger, the Q end of the D trigger is connected with the second input end of the OR gate, the output end of the OR gate is connected with the access request signal output end, and the access request signal output end is externally connected with the authorization arbitration unit. When the signal of the command address access request signal and the signal of the access request signal are high level 1, the signal indicates that the request signal exists, when the signal is low level 0, the signal indicates that the request does not exist, when the signal of the slave device idle state signal and the signal of the bus idle state signal are high level 1, the signal indicates that the state is idle, when the signal of the slave device idle state signal and the signal of the bus idle state signal are low level 0, the signal indicates that the state is busy, when the signal of the command access authorization state signal is high level 1, the signal indicates that the state is authorized, and when the signal of the command access authorization. Some buses, such as AHB buses, command access and data access are separated into two bus cycles, so that the arbitration module needs to record the arbitration record of the previous cycle in order to correctly process the subsequent data access. Therefore, the request accepting unit uses one D flip-flop to record the bus request state of the previous cycle.

The operating principle of the request receiving unit circuit is as follows: when receiving a command address access request signal sent by the master device 0, the input end of the command address access request signal is at a high level 1, and at this time, there are three situations: (1) if the command access grant state signal input terminal is high 1, i.e. master 0 is granted, and the slave idle state signal input terminal is high 1, i.e. slave idle, the data selector mux1 directly outputs high 1 indicating that slave is idle to master 0 without waiting; in addition, because the input end of the command address access request signal is high level 1, the high level 1 is directly generated through an OR gate and is sent to the authorization arbitration unit, and the command address access request is sent; in the next bus cycle, if the bus of the master device 0 is idle, that is, the bus idle state signal input end inputs a high level 1, the high level signal 1 of the D flip-flop FF1 is sent to the authorization arbitration unit to indicate that a data access request signal is sent, if the bus is busy, the input is a low level 0, the D flip-flop FF1 does not generate a high level, and the bus idle state signal is waited until the state is idle; (2) if the input end of the command access authorization state signal is high level 1, that is, the master device 0 is authorized, and the input signal of the input end of the slave device idle state signal is low level, that is, the slave device is busy, the data selector mux1 directly outputs low level 0 indicating that the slave device is busy to the master device 0 without waiting; (3) if the command access grant status signal input is low 0, i.e., master 0 is not authorized, the data selector mux1 outputs low 0 indicating that the slave is busy directly to master 0 without waiting. The request accepting unit transmits a bus idle state signal indicating the bus state of the master 0 to the connected grant arbitration unit every bus cycle.

As shown in fig. 2 and 4, the grant arbitration unit is configured to send a grant status signal to the access control unit and the request receiving unit according to the priority, specifically: when receiving only the access request signal transmitted from the request reception unit 0, transmitting a command access authorization status signal indicating that the status is authorized to the request reception unit 0, and transmitting a command access authorization instruction signal indicating that the master device 0 is authorized to access the command address to the access control unit; when receiving only the access request signal transmitted from the request reception unit 1, transmitting a command access authorization status signal indicating that the status is authorized to the request reception unit 1, and transmitting a command access authorization instruction signal indicating that the master 1 is authorized to access the command address to the access control unit; when receiving access request signals sent by the request accepting unit 0 and the request accepting unit 1 at the same time, sending a command access authorization state signal of which the state is authorized to a request accepting unit corresponding to a master device with higher priority, in this embodiment, the master device 1 with higher priority sends a command access authorization indication signal indicating that the master device with higher priority is accessed by an authorized command address to an access control unit; when the access request signal of any request accepting unit is not received, the state of the command access authorization state signal of the request accepting unit 0 is maintained as authorization by default; when the main device 0 finishes command address access and receives an access request signal of the request acceptance unit 0 again, if the state of the bus idle state signal sent by the request acceptance unit 0 is idle at this time, a data access authorization indication signal of the main device 0 which is authorized to access data is sent to the access control unit, otherwise, the state of the bus idle state signal is idle; when the request accepting unit 1 receives the access request signal again after the access of the command address of the master device corresponding to the request accepting unit 0 is finished, if the state of the bus idle state signal sent by the request accepting unit 1 is idle at this time, a data access authorization indication signal indicating that the master device 1 is authorized to access data is sent to the access control unit, otherwise, the state of the waiting bus idle state signal is idle. The above functions are realized by using circuits, and the authorization arbitration unit specifically includes a data selector mux2, a data selector mux3, a D flip-flop FF2 and three inverters, a first access request signal input terminal of the authorization arbitration unit is externally connected to the request accepting unit 0, a control terminal of the internally connected data selector mux2, a first bus idle state signal input terminal is externally connected to the request accepting unit 0, a 1 address input terminal of the internally connected data selector mux3, a second access request signal input terminal is externally connected to the request accepting unit 1, a 0 address input terminal of the data selector mux2 is internally connected by one inverter, a second bus idle state signal input terminal is externally connected to the request accepting unit 1, a 0 address input terminal of the data selector mux3 is internally connected by one inverter, and slave devices are externally connected from the device idle state signal input terminal, the first slave idle state signal output end and the second slave idle state signal output end are internally connected, the first slave idle state signal output end and the second slave idle state signal output end are respectively externally connected with the request receiving unit 0 and the request receiving unit 2, the 1 address input end of the data selector mux2 inputs a priority signal representing the priority of the master device through an inverter, specifically, when the priority of the master device 1 is higher and the master device 1 sends an access request signal, the priority signal is high level 1, otherwise, the priority signal is 0, the output end of the data selector mux2 is simultaneously connected with the command access authorization indication signal output end, the control end of the data selector mux3 and the first command access authorization state signal output end, and is also connected with the second command access authorization state signal output end through an inverter, the command access authorization indication signal output end is externally connected with the access control unit, the output end of the data selector mux3 is connected with the D end of the D trigger, the Q end of the D trigger is connected with the data access authorization indication signal output end, and the data access authorization indication signal output end is externally connected with the access control unit.

The operation principle of the authorization arbitration unit is as follows: (1) when only the master device 0 sends a command address access request, that is, when the first access request signal input terminal inputs a high level 1 and the second access request signal input terminal inputs a low level 0, the 1 address input terminal of the data selector mux2 is a high level 1, the data selector mux2 outputs a high level 1, then a high level is output to the command access authorization indication signal output terminal, a high level 1 is output to the first command access authorization state signal output terminal, which indicates that the master device 0 is authorized to access the command address, and the high level 1 outputs a low level 0 to the second command access authorization state signal output terminal through an inverter, which indicates that the master device 1 is not authorized to access the command address; when the command address access of the master device 0 is finished, the access request signal is received again, namely the input end of the first access request signal inputs high level 1 again, the data access request is represented at this time, if the input end of the first bus idle state signal is high level 1, namely idle, the data selector mux3 outputs high level 1, the D trigger FF2 sends high level, namely the data access authorization indication signal is high level, the master device 0 is authorized to perform data access, otherwise the state of the waiting bus idle state signal is idle; (2) when only the master device 1 sends a command address access request, that is, when the second access request signal input terminal inputs a high level 1 and the first access request signal input terminal inputs a low level 0, the 0 address input terminal of the data selector mux2 is a low level 0, and the data selector mux2 outputs a low level 0, then the low level 0 is output to the command access authorization indication signal output terminal, which indicates that the master device 1 is authorized to perform command address access, and the low level 0 is output to the first command access authorization state signal output terminal, and the low level 0 outputs a high level 1 to the second command access authorization state signal output terminal through an inverter, which indicates that the master device 0 is not authorized to perform command address access, and the master device 1 is authorized to perform command address access; when the master device 1 commands the address access to be finished, the access request signal is received again, that is, the second access request signal input end inputs high level 1 again, which represents the data access request, if the second bus idle state signal input end is high level 1, that is, idle, and inputs low level 0 to the address input end of the data selector mux30 through the inverter, the data selector mux3 outputs low level 0, the D flip-flop FF2 sends low level 0, that is, the data access authorization indication signal is low level, which represents that the master device 1 is authorized to perform data access, otherwise, the state of waiting for the bus idle state signal is idle; (3) when the access request signals sent by the request accepting unit 0 and the request accepting unit 1 are received simultaneously, namely when the first access request signal input end inputs high level 1 and the second access request signal input end inputs high level 1, the 1 address input end of the data selector mux2 is low level 0, the data selector mux2 outputs low level 0, then low level is output to the command access authorization indication signal output end, and low level 0 is output to the first command access authorization state signal output end, namely, the master 1 is authorized, the master 0 is not authorized, and the following is the same as in (2); (4) when no access request signal is received from any request accepting unit, that is, when the input terminal of the first access request signal inputs low level 0 and the input terminal of the second access request signal inputs low level 0, the address input terminal 1 of the data selector mux2 is high level 1, that is, the state of the command access authorization state signal of the request accepting unit 0 is maintained as authorization by default, and the following is the same as in (1).

As shown in fig. 2 and 5, the access control unit is configured to allow an authorized master device to perform command address access and data access according to the authorization status signal. The method specifically comprises the following steps: when a command access authorization indication signal of an authorization arbitration unit is received, allowing a corresponding master device in the command access authorization indication signal to send a bus command address access signal to a slave device, wherein the bus command address access signal comprises a command address access request signal and a bus idle state signal which are sent by the corresponding master device; when receiving the data access authorization indication signal of the authorization arbitration unit, the corresponding master device in the data access authorization indication signal is allowed to send a bus data access signal to the slave device. The above functions are realized by using a circuit, the access control unit specifically includes a data selector mux4 and a data selector mux5, the command access authorization indication signal input end of the access control unit is externally connected with an authorization arbitration unit, the control end of the internally connected data selector mux4 is externally connected with an authorization arbitration unit, the control end of the internally connected data selector mux5 is connected with a bus command address access signal sent by the master device 0 at the 1 address input end of the data selector mux4, the bus command address access signal sent by the master device 1 is input at the 0 address input end of the data selector mux4, the output end of the data selector mux4 is connected with a bus command address access signal output end, the bus command address access signal output end is externally connected with a slave device, the bus data access signal sent by the master device 0 is input at the 1 address input end of the data selector mux5, the 0 address input end of the data selector mux4 inputs the bus data access signal sent by the master 1, the output end of the data selector mux4 is connected with the bus data access signal output end, and the bus data access signal output end is externally connected with the slave.

The working principle of the access control unit is as follows: when receiving the command access grant indication signal from the grant arbitration unit, if the signal is at high level 1, indicating that the master 0 command address access is allowed, the data selector mux4 sends the bus command address access signal sent by the master 0 to the slave, and if the signal is at low level 0, indicating that the master 1 command address access is allowed, the data selector mux4 sends the bus command address access signal sent by the master 1 to the slave; when receiving the data access grant indication signal from the grant arbitration unit, if the signal is at high level 1, indicating that the data access of the master device 0 is allowed, the data selector mux5 sends the bus data access signal sent by the master device 0 to the slave device, and if the signal is at low level 0, indicating that the data access of the master device 1 is allowed, the data selector mux5 sends the bus data access signal sent by the master device 1 to the slave device.

The present embodiment further provides a bus access arbitration method, which is based on the foregoing apparatus, and specifically includes: when the request receiving unit receives a command address access request sent by the connected main equipment or the arbitration module, the request receiving unit generates an idle state signal of the slave equipment according to the authorization state signal fed back by the authorization arbitration unit and whether the slave equipment is idle or not, and sends the idle state signal to the corresponding main equipment; the authorization arbitration unit sends an authorization state signal to the access control unit and the request receiving unit according to the priority; the access control unit allows the authorized master device to perform command address access and data access according to the authorization status signal.

The above steps are described in detail, specifically:

s1, the main device sends command address access request signals to the request receiving units of the connected arbitration modules;

s2, the two request accepting units of the arbitration module respectively execute the following steps:

if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave equipment idle state signal sent by the slave equipment is idle, sending the slave equipment idle state signal with the idle state to the connected master equipment, generating an access request signal and sending the access request signal to the authorization arbitration unit;

if the state of the command access authorization state signal fed back by the authorization arbitration unit is authorization and the state of the slave equipment idle state signal sent by the slave equipment is busy, sending the slave equipment idle state signal with the busy state to the connected master equipment;

if the state of the command access authorization state signal fed back by the authorization arbitration unit is unauthorized, a slave device idle state signal with a busy state is sent to the connected master device;

s3, the authorization arbitration unit of the arbitration module executes the following steps:

when the authorization arbitration unit receives only the access request signal transmitted by the request reception unit 0, it transmits a command access authorization status signal indicating that the status is authorized to the request reception unit, and transmits a command access authorization instruction signal indicating that the master device 0 is authorized to access the command address to the access control unit;

when receiving only the access request signal transmitted from the connected request receiving unit 1, transmitting a command access authorization status signal indicating that the status is authorized to the request receiving unit, and transmitting a command access authorization instruction signal indicating that the master 1 is authorized to access the command address to the access control unit;

when receiving access request signals sent by a request receiving unit 0 and a request receiving unit 1 which are connected, sending a command access authorization state signal of which the state is authorized to a request receiving unit 1 corresponding to a master device 1 with higher priority, and sending a command access authorization instruction signal of which the master device 1 is authorized to access by a command address to an access control unit;

when the access request signal of any request accepting unit is not received, the state of the command access authorization state signal of the request accepting unit 0 is maintained as authorization by default;

s4, the access control unit of the arbitration module executes the following steps:

when a command access authorization indication signal of an authorization arbitration unit is received, allowing a corresponding master device in the command access authorization indication signal to send a bus command address access signal to a slave device, wherein the bus command address access signal comprises a command address access request signal and a bus idle state signal which are sent by the corresponding master device; and performing command address access;

s5, the request accepting unit of the arbitration module executes the following steps:

s6, the authorization arbitration unit of the arbitration module executes the following steps:

when the request accepting unit access request signal is received again, if the state of the bus idle state signal sent by the request accepting unit is idle at the moment, sending a data access authorization indication signal which indicates that the master device corresponding to the request accepting unit is authorized to access data to the access control unit, otherwise, waiting for the state of the bus idle state signal to be idle;

s7, the access control unit of the arbitration module executes the following steps:

Example 2

The present embodiment provides a bus access arbitration apparatus, in which the number of masters is four, i.e. master 0, master 1, master 2 and master 3, respectively, and as shown in fig. 6, the buses of the four masters connect the slaves through the bus access arbitration, the bus access arbitration apparatus includes three arbitration modules, specifically, two first-level arbitration modules (arbitration module (0/1) and arbitration module (2/3)) and one second-level arbitration module (0/1/2/3)), master 0 and master 1 are connected to arbitration module (0/1), master 2 and master 3 are connected to arbitration module (2/3), arbitration module (0/1) and arbitration module (2/3) are connected to higher-level arbitration module (0/1/2/3), the arbitration module (0/1/2/3) is the highest level, connecting the slaves. The arbitration modules have the same internal structure, and as in embodiment 1, include two request accepting units, one grant arbitration unit, and one access control unit, each request accepting unit is connected to one main device or a lower level arbitration module, the grant arbitration unit is connected to two request accepting units, and the access control unit is connected to the grant arbitration unit. The function of the arbitration module is either one, namely, one master device is selected from two master devices to establish connection with the slave device, the arbitration module (0/1) is selected from one of the

master devices

0 and 1, the arbitration module (2/3) is selected from one of the master devices 2 and 3, and the arbitration module (0/1/2/3) is selected from one of the master devices selected from the arbitration module (0/1) and the arbitration module (2/3), and finally only one master device is connected with the slave device to perform access.

As shown in fig. 7, each unit of each arbitration module in this embodiment is the same as the internal structure and function in embodiment 1, but different from the external port connection, the request accepting unit of the arbitration module (0/1) and the arbitration module (2/3) is connected to a master, the bus command address access signal output terminal of the access control unit is connected to the command access request signal input terminal and the bus idle state signal input terminal of the request accepting unit of the higher-order arbitration module (0/1/2/3) rather than the slave, and the bus command address access signal issued by the access control unit of the arbitration module (0/1) and the arbitration module (2/3) includes the command access request signal and the bus idle state signal of the master selected as the alternative. The arbitration module (0/1/2/3) serves as the highest level, the access control unit of which is connected to the slave device. Accordingly, the principle and function of each unit in the arbitration module are different from those of embodiment 1 in that: according to the connection relation, the flow direction of the output signal is different, and the other can be obtained by the same method.

The embodiment also provides a bus access arbitration method, which is based on the device and comprises the following specific steps:

when the authorization arbitration unit only receives the access request signal sent by the first request receiving unit connected with the authorization arbitration unit, the authorization arbitration unit sends a command access authorization state signal of which the state is authorized to the request receiving unit, and sends a command access authorization instruction signal which indicates that the main equipment corresponding to the request receiving unit is authorized to be accessed by the command address to the access control unit;

when only receiving an access request signal sent by a second connected request receiving unit, sending a command access authorization state signal with an authorized state to the request receiving unit, and sending a command access authorization instruction signal which indicates that a main device corresponding to the request receiving unit is authorized to be accessed by a command address to an access control unit;

when receiving access request signals sent by a first request receiving unit and a second request receiving unit which are connected, sending a command access authorization state signal of which the state is authorized to a request receiving unit corresponding to a master device with higher priority, and sending a command access authorization indication signal which indicates that the master device with higher priority is accessed by an authorized command address to an access control unit;

Example 3

This embodiment provides a bus access arbitration apparatus, in which 3 masters in total are respectively a master 0, a master 1, and a master 2, and as shown in fig. 8, buses of the 3 masters are connected to the slaves through the bus access arbitration, the bus access arbitration apparatus includes two arbitration modules, specifically, a first-stage arbitration module (0/1) and a second-stage arbitration module (0/1/2)), the master 0 and the master 1 are connected to the arbitration module (0/1), the master 2 is used as an arbitration module, and is connected to the arbitration module (0/1/2) together with the arbitration module (0/1), the arbitration module (0/1/2) is the highest stage, the internal structures of the connection slaves are the same, as in embodiment 1, the system comprises two request receiving units, an authorization arbitration unit and an access control unit, wherein each request receiving unit is connected with a master device, the authorization arbitration unit is connected with the two request receiving units, and the access control unit is connected with the authorization arbitration unit. The arbitration module (0/1) selects one of the

master devices

0 and 1, and the arbitration module (0/1/2) selects one of the master device and the master device 3 selected by the arbitration module (0/1), and finally only one master device is connected with the slave device for access. The internal structure and function of each unit of each arbitration module in the embodiment are the same as those in embodiment 1, but the difference is that the external port connection is different, the request accepting unit of the arbitration module (0/1) is connected with the master device, the bus command address access signal output end of the access control unit is connected with the command access request signal input end and the bus idle state signal input end of the request accepting unit of the higher-level arbitration module (0/1/2) but not the slave device, and the bus command address access signal sent by the access control unit of the arbitration module (0/1) includes the command access request signal and the bus idle state signal of the master device selected by the alternative. The arbitration module (0/1/2) serves as the highest level, the access control unit of which is connected to the slave device. Accordingly, the principle and function of each unit in the arbitration module are different from those of embodiment 1 in that: according to the connection relation, the flow direction of the output signal is different, and the other can be obtained by the same method.

This embodiment further provides a bus access arbitration method, which is based on the foregoing apparatus, and the method is the same as that in embodiment 2, and therefore, the details are not repeated.

Further, the same reasoning can be made for the configurations and the circuit connection relationships when the number of the master devices is arbitrary according to embodiments 1 to 3.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention.

Claims

1. A bus access arbitration apparatus through which buses of a plurality of masters are connected to a slave, characterized in that: the device comprises a plurality of levels of arbitration modules, wherein every two main devices are connected to one level of arbitration module, every two level of arbitration modules are connected to one level of arbitration module, and the rest of the arbitration modules with the highest levels are connected to slave devices; each arbitration module comprises two request receiving units, an authorization arbitration unit and an access control unit, each request receiving unit is connected with a main device or an arbitration module, the authorization arbitration unit is connected with the two request receiving units, and the access control unit is connected with the authorization arbitration unit;

the request accepting unit is used for generating an idle state signal of the slave device according to the authorization state signal fed back by the authorization arbitration unit and whether the slave device is idle or not when receiving a command address access request sent by the connected master device or the arbitration module, and sending the idle state signal to the corresponding master device; the authorization arbitration unit is used for sending an authorization state signal to the access control unit and the request receiving unit according to the priority; the access control unit is used for allowing the authorized main equipment to perform command address access and data access according to the authorization state signal.

2. The bus access arbitration device according to claim 1, wherein: and if the number of the main devices is singular, connecting the last remaining main devices as an arbitration module.

3. The bus access arbitration device according to claim 1, wherein: the request accepting unit is specifically configured to:

when a command address access request signal sent by a connected main device or an arbitration module at a lower level is received, the following processing is executed:

4. The bus access arbitration device according to claim 1, wherein: the grant arbitration unit is specifically configured to:

5. The bus access arbitration device according to claim 1, wherein: the access control unit is specifically configured to:

6. The bus access arbitration device according to claim 1, wherein: the request receiving unit specifically comprises a data selector, a D trigger, an AND gate, an OR gate and an inverter, wherein a command access authorization state signal input end of the request receiving unit is externally connected with an authorization arbitration unit, a control end of an internally connected data selector, an authorization arbitration unit is externally connected with an idle state signal input end of a slave device, an address 1 input end of the internally connected data selector, an access control unit of a main device or a lower-level arbitration module is externally connected with a command address access request signal input end, an address 0 input end of the data selector is internally connected through the inverter, and the first input ends of the AND gate and the OR gate are respectively connected, an idle state signal output end of the slave device is externally connected with an authorization arbitration unit of the main device or the lower-level arbitration module, an output end of the internally connected data selector, and an idle state signal input end of a bus is externally connected with an access control unit of the main device or the lower-level arbitration, the internal bus idle state signal output end and the second input end of the AND gate are simultaneously connected, the bus idle state signal output end is externally connected with the authorization arbitration unit, the output end of the AND gate is connected with the D end of the D trigger, the Q end of the D trigger is connected with the second input end of the OR gate, the output end of the OR gate is connected with the access request signal output end, and the access request signal output end is externally connected with the authorization arbitration unit.

7. The bus access arbitration device according to claim 1, wherein: the authorization arbitration unit specifically comprises a first data selector, a second data selector, a D trigger and three inverters, wherein a first access request signal input end of the authorization arbitration unit is externally connected with a first request receiving unit, a control end of the first data selector is internally connected with the first data selector, a first bus idle state signal input end is externally connected with the first request receiving unit, a 1 address input end of the second data selector is internally connected with the second request receiving unit, a second access request signal input end is externally connected with the second request receiving unit, a 0 address input end of the first data selector is internally connected with the first bus idle state signal input end through one inverter, the second bus idle state signal input end is externally connected with the second request arbitration unit, a 0 address input end of the second data selector is internally connected with the second bus idle state signal input end through one inverter, and a request receiving unit of a slave device or a higher-level module is externally connected with the device idle state signal input end, the first slave device idle state signal output end and the second slave device idle state signal output end are internally connected, the first slave device idle state signal output end and the second slave device idle state signal output end are respectively externally connected with the first request receiving unit and the second request receiving unit, the 1 address input end of the first data selector inputs a priority signal representing the priority of the master device through an inverter, the output end of the first data selector is simultaneously connected with the command access authorization indication signal output end, the control end of the second data selector and the first command access authorization state signal output end, the second command access authorization state signal output end is also connected through an inverter, the command access authorization indication signal output end is externally connected with the access control unit, the output end of the second data selector is connected with the D end of the D trigger, and the Q end of the D trigger is connected with the data access authorization indication signal output end, the data access authorization indication signal output end is externally connected with the access control unit.

8. The bus access arbitration device according to claim 1, wherein: the access control unit specifically comprises a first data selector and a second data selector, wherein a command access authorization indication signal input end of the access control unit is externally connected with an authorization arbitration unit, a control end of the first data selector is internally connected, a data access authorization indication signal input end is externally connected with an authorization arbitration unit, a control end of the second data selector is internally connected, a 1 address input end of the first data selector inputs a bus command address access signal sent by a first master device, the first master device is a master device corresponding to a first request acceptance unit connected with the authorization arbitration unit, a 0 address input end of the first data selector inputs a bus command address access signal sent by a second master device, the second master device is a master device corresponding to a second request acceptance unit connected with the authorization arbitration unit, and an output end of the first data selector is connected with a bus command address access signal output end, the bus command address access signal output end is externally connected with a slave device or a request accepting unit of a higher-level arbitration module, the 1 address input end of the second data selector inputs a bus data access signal sent by the first master device, the 0 address input end of the first data selector inputs a bus data access signal sent by the second master device, the output end of the first data selector is connected with the bus data access signal output end, and the bus data access signal output end is externally connected with the slave device.

9. An arbitration method of the bus access arbitration device according to claim 1, comprising:

10. The method of claim 9, wherein: the method specifically comprises the following steps: