KR940010807B1 - Bus system for use with information processing apparatus and ic device for information processing bus system controller - Google Patents

Abstract

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Description

Bus system for information processing device and IC device for information processing bus system controller

1 is a schematic diagram showing the configuration of a first embodiment of a bus system according to the present invention;

2 and 3 schematically show the configuration of a bus system of the prior art.

4 exemplarily shows one embodiment of a third connection controller in the first embodiment of the present invention shown in FIG.

5 and 6 are block diagrams each showing an embodiment of a data path switch and a bus-memory connection controller in the embodiment of the third lane connection controller of FIG. 4 used in the first embodiment of the present invention.

7 schematically shows the configuration of a second embodiment of a bus system according to the present invention;

8 schematically shows the configuration of a third embodiment of a bus system according to the present invention;

9 is a diagram showing a correspondence relationship between a data path control signal to be decoded by a decoder of the data path switch of FIG. 5 according to the present invention and a decoding operation result.

10 through 15 show data path control signals DT_CNT and processor / main memory read, processor / main memory write, processor / system bus device read, processor / sysbus device write, DMA read and DMA write operations. Figures show the relationship between different signals in the various stems of the state transitions.

FIG. 16 is a transition diagram showing an example of a state transition of a sequencer in the bus-memory connection controller of FIG.

17 and 18 are signal timing diagrams showing an example of a data transfer operation associated with FIGS.

19 is a diagram showing the connection of the signals of FIGS. 17 and 18 between the third lane connection controller and the respective buses of FIG.

The present invention relates to a bus system used in an information processing apparatus such as a workstation, a personal computer, a word processor, and an IC device for an information processing bus system controller.

The bus system disposed in the information processing apparatus is conventionally reported in Report "EISA", pp. L.Brett Glass. Like the bus systems described in 417-424 OF "BYTE", Volume 14, Number 12 (1989), the memory bus and the system bus are respectively connected to the processor bus, or the processor bus and the memory bus are respectively connected to the system bus. It was in a constitution.

In the former configuration, since the processor bus cannot operate independently during the interlocking operation of the system bus and the memory bus, so-called direct memory access (DMA), the use efficiency of the processor bus becomes poor. On the other hand, in the latter configuration, there is a problem that the system bus cannot be operated independently when the processor bus and the memory bus are interoperated, and so-called main memory accesses, so that the use efficiency of the system bus becomes poor.

The construction and problems of these conventional bus systems will be described in detail with reference to the following drawings.

An object of the present invention is to provide a bus system for an information processing apparatus and an IC device for an information processing bus system controller that maximizes the use efficiency of each bus.

Another object of the present invention is to provide an IC device for a bus system and an information processing bus system controller capable of simultaneously performing interlocking operations of a processor bus and a memory bus and independent operations of the system bus.

Still another object of the present invention is to provide an IC device for a bus system and an information processing bus system controller capable of simultaneously performing interlocking operations of a system bus and a memory bus and independent operations of the processor bus.

Still another object of the present invention is a bus system and information for an information processing apparatus that maximizes the efficiency of use of each bus when three types of buses, a system bus, a memory bus, and a processor bus are interconnected between at least three buses. To provide IC devices for processing bus system controllers.

In order to achieve the above object, in the present invention, three types of buses of processor bus, memory bus, and system bus are connected in at least a third shape, and any other two types of buses of three types of buses are interlocked. One type of bus can be operated independently.

That is, in the present invention, a bus system for an information processing apparatus includes a processor, a processor bus connected with one processor, a main memory device, a memory bus connected with the main memory device, a connected device, a system bus connected with the connected device, a processor bus, and a memory. Three types of buses such as a bus and a system bus are connected in a third shape, and when the processor bus and the memory bus are connected, the transfer operation between the processor bus and the memory bus and the transfer operation on the system bus can be executed in parallel. When connecting the memory bus and the system bus, the transfer operation between the memory bus and the system bus and the transfer operation on the processor bus can be executed in parallel so that each of the three buses can be physically independently operated. Configure the third-order connection controller to run

In this invention, this tertiary connection controller is connected to a connection controller means for outputting a data path control signal when the transfer operation is a transfer operation via multiple buses, and connected to respective data buses of two types of buses. A data switch means for instructing bus-to-bus connection of two data buses among three bus types in accordance with the data bus signal inputted from the means.

Preferably, the data switch means and the bus-memory connection control means are each configured alone or integrally on one integrated circuit.

In order to achieve the above object, the IC device for information processing bus system controller according to the present invention uses three types of buses: a processor connected to a processor bus, a memory bus connected to a main memory device, and a system bus connected to a connected device. It has a connection part connected in the third shape, and when the processor bus and the memory bus are connected via the connection part, it controls so that the transfer operation between the processor bus and the memory bus and the transfer operation on the system bus can be executed in parallel. When the system bus is connected through the connection part, the control operation can be performed in parallel between the transfer operation between the memory bus and the system bus and the transfer operation on the processor bus. To a third-level connection controller that performs bus-to-bus connections It is sex.

In addition, in the present invention, each type of bus is not limited to one, that is, in the case where any one of the three types of buses is plural, a connection controller can be similarly configured to enable interconnection of these buses. Can be.

In the above-described configuration of the present invention, the three types of buses of the processor bus, the memory bus, and the system bus are interconnected in at least a third shape, for example, to access the main memory on the memory bus from the processor on the processor bus. In the case of processor / main memory access, data is transferred only over the processor bus and the memory bus, ie no system bus is used for data transfer. Thus, the system bus can operate independently. On the other hand, in the case of DMA accessed from a connection device on the system bus to the main memory on the memory bus, data is transferred only through the system bus and the memory bus. In other words, the processor bus can operate independently since it does not pass through the processor bus for data transmission. As a result, the use efficiency for each of the three types of buses can be maximized. Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the drawings.

First, the first embodiment of the present invention will be described with reference to FIGS. 2 and 3 show the configuration of the bus system in the prior art, which will be described in detail here for comparison with the present invention.

Each of FIGS. 1 to 3 includes N processors 101 (where N is an integer), a cache memory system 102, a main memory 104, and M (where M is an integer) system bus connection devices. Is arranged. The system bus connection device 105 represents so-called I / O devices, such as a disk file controller, a drawing display controller, a network communication controller, and the like. (111), (112), and (113) represent a processor bus and a memory bus, respectively. And system bus. Reference numeral 103 in FIG. 1 is a third connection controller. 201 and 301 in Figs. 2 and 3 are bus connection controllers, respectively, and 202 and 302 are memory connection controllers.

In the conventional bus system shown in Figs. 2 and 3, in Fig. 2, the system bus 113 and the memory bus 112 are connected to the processor by the bus connection controller 201 and the memory connection controller 202, respectively. It is connected to the bus 111 independently. In FIG. 3, the processor bus 111 and the memory bus 112 are independently connected to the system bus 113 via the bus connection controller 301 and the memory connection controller 302, respectively.

2, in the DMA operation of transferring data between the connection device 105 on the system bus 113 and the main memory on the memory bus 112, the data is sent via the processor bus 111. FIG. Lose. Therefore, independent operation of the processor bus 111 such as data transfer between the processor 101 and the cache 102 or between several processors 101 cannot be executed simultaneously with the DMA operation. On the other hand, in the configuration of FIG. 3, the data passes through the system bus 113 in the access of the so-called processor / main memory, which transfers data between the processor 101 and the main memory 104. FIG. Therefore, independent operation of the system bus l13, such as data transfer between several system bus connection devices 105, cannot be executed simultaneously with processor / main memory access.

On the other hand, in the bus system of FIG. 1, which is the first embodiment of the present invention, three types of buses of the processor bus 11, the memory bus 112, and the system bus 113 are connected by the third connection controller 103. They are connected to each other in a third shape. Therefore, in the case of the DMA operation, since data does not pass through the processor bus 111, the independent operation of the processor bus 111 can be executed simultaneously with the DMA operation. In the case of processor / main memory access, the independent operation of the system bus 113 can be executed simultaneously with the processor / main memory access because it is not via the system bus 113. As a result, even in the case of DMA operation and processor / main memory access, the use efficiency of each of the three types of buses can be maximized.

Hereinafter, one example of the performance evaluation of the bus system of the first embodiment of the present invention shown in FIG. 1 and the conventional bus system shown in FIGS. 2 and 3 will be described. The effect of an Example is demonstrated quantitatively.

In the bus system of FIGS. 1 to 3, it is assumed that the maximum data throughput of the processor bus 111, the memory bus 112, and the system bus 113 is 400, 400, and 200 megabytes per second (MB / s). do. In addition, the percentage of main memory accesses in the processor bus 111 is 40%, the percentage of DMAs in the system bus 113 is 70%, and the maximum bus capture ratios of the bus connection controllers 201 and 301 are shown. Assume that 50%. Under the above conditions, when both of the processor bus 111 and the system bus 113 operate at the maximum data throughput, the performance evaluation of each bus system is as follows.

First, in the conventional bus system of FIG. 2, when the system bus 113 intends to operate at a maximum throughput of 200MB / s, a request of 140MB / s of DMA equivalent to 70% of 200MB / s is directed to the bus connection controller 201. Is sent. The bus connection controller 201 can acquire a bus up to 200MB / s, which is 50% of 400MB / s with respect to the processor bus 111. Thus, all of the DMA requests of 140 MB / s are obtained. As a result, the system bus 113 can operate at a transfer rate of 200 MB / s, while the processor bus 111 receiving a DMA request can operate out substantially at a transfer rate of (400-140) -260 MB / s. none. At this time, processor / main memory access is 104 MB / s, which is 40% of 260 MB / s. Therefore, a request for a transmission rate of (140 + 104) = 244 MB / s is sent to the memory bus 112, and the memory bus 112 can respond to this request as described above. In short, the use efficiency for each of the three types of buses in the conventional bus system of FIG. 2 is achieved as follows. That is, 260/400 × 100 = 65% for the processor bus 111, 254/400 × 100 = 63.5% for the memory bus 112, and 200/200 × 100 = 100% for the system bus 113. do.

Next, in the conventional bus system shown in FIG. 3, when the processor bus 111 intends to operate at the maximum throughput of 400 MB / s, the main memory access request of 160 MB / s, which is 40% of the throughput, is the bus connection controller ( 301). However, the bus connection controller 301 may operate up to 100 MB / s, which is 50% of 200 MB / s with respect to the system bus 113. Thus, processor / main memory access is handled only at transfer rates up to 100MB / s. As a result, the processor bus 111 can only operate at a transfer rate of up to 250MB / s (100MB / s becomes 40% of 250MB / s). In this case, the system bus 113 operates at a throughput of substantially 200 to 100 MB / s. Thus, the DMA request is 70 MB / s, which is 70% of 100 MB / s. As a result, the request to the memory bus 112 is (100 + 70) = 170 MB / s, and the memory bus 112 can respond to this request as described above. In summary, the bus utilization efficiency for each of the three types of buses in the conventional bus system of FIG. 3 is 250/400 × 100 = 62.5% for the processor bus 111 and for the bus system 112. 170 / 400x100 = 42.5% and 100 / 200x100 = 50% with respect to the system bus 113.

On the other hand, in the bus system of FIG. 1 which is the first embodiment of the present invention, if the processor bus 111 intends to operate at a transmission speed of 400 MB / s, the main memory access of 160 MB / s, which is 40% of 400 MB / s, is accessed. The request is sent to the connection controller 103 in the third order. In addition, when the system bus 113 intends to operate at 200 MB / s throughput, a DMA request with a transmission speed of 140 MB / s, which is 70% of 200 MB / s, is sent to the connection controller 103 in the third order. Accordingly, the tertiary connection controller 103 sends a transfer request including a processor / main memory access request and a DMA request to the memory bus 112 at a transfer rate of (160 + 140) = 300 MB / s. The memory bus 112 can respond to this request. Therefore, the processor bus 111 and the system bus 113 may operate at 400MB / s and 200MB / s, respectively. That is, the bus utilization efficiency for each of the three types of buses in the bus system which is the first embodiment of the present invention shown in FIG. 1 is obtained as follows. That is, 400/400 × 100 = 100% for the processor bus 111, 300/400 × 100 = 75% for the memory bus 112, and 200/200 × 100 = 100% for the system bus 113. do.

The above results are shown in Table 1. As is clear from Table 1, it can be seen that the use efficiency of three types of buses is maximized in the bus system of FIG. 1 according to the present invention.

TABLE 1

Prior to describing an embodiment showing a specific configuration of the present invention, a bus system as a second and third embodiment of the present invention will be described using FIGS. 7 and 8.

7 and 8, 701 and 703 are standalone processors that can be connected to separate cache memory systems, and 801 are 1 to N multi-type processors that can be connected to separate cache memory systems. to be. Reference numerals 711 and 712 are processor buses that connect the processors 701 and 703 to the fourth connection controller 705, respectively. The fourth lane connection controller 705 connects the processor buses 711, 712, the memory bus 111, and the system bus 113 with each other. 702, 704, and 802 are cache memory systems that are individually connected to the processors 701, 703, and 801, respectively. The connection device 105 connected to the system bus 113 is the same as the I / O device of the above embodiment.

In the second embodiment of the present invention shown in FIG. 7, three types of four buses, two processor buses 711, 712, a memory bus 112, and a system bus 113, are four lanes. The connection controller 705 is connected in a quadrature shape. Processors 701 and 703 are standalone processors capable of connecting cache memory systems 702 and 704, respectively. For this reason, the processors 701 and 703 can directly access the separate cache memories 702 and 704 without using the processor bus, but cannot share the processor bus.

In FIG. 7, the fourth lane connection controller 705 executes connection control between three types of four buses, for example, to communicate communication between the processor 701 and 703 in parallel with the DMA operation. It is possible to execute such operations as executing the main memory access by the processor 701 and the system bus access by the processor 702 in parallel. Thereby, also in this embodiment, the use efficiency of three types of four buses can be maximized similarly to the above embodiment.

In FIG. 8, three types of buses of the processor bus 111, the memory bus 112, and the system bus 113 are connected by the third connection controller 103 similarly to the first embodiment shown in FIG. It is connected in the shape of a car. 801 is a multi-type processor capable of connecting separate cache memory systems 802. Thus, each of the processors 801 can access the separate cache memory 802 without going through the processor bus 111. In addition, the processor bus 111 can be shared. In the bus system of FIG. 8 which is the third embodiment of the present invention, similarly to the embodiment of FIG. 1, the DMA operation and the independent operation of the processor bus 111 are executed in parallel or the main memory device from the processor bus 111 is executed. Operation such as access and operation of the system bus 113 can be executed in parallel. As a result, as in the first embodiment, the efficiency of use of three different types of three buses can be maximized.

Subsequently, specific embodiments of the main part of the embodiment according to the present invention described above will be described in detail with reference to FIGS. 4 to 6. In particular, the detailed configuration of the third lane connection controller 103 of the first and third embodiments shown in FIGS. 1 and 8 will be described, but the fourth lane connection controller 705 shown in FIG. It can be configured similarly.

In this regard, FIG. 4 shows the configuration of a tertiary connection controller 103 having two integrated circuits. In FIG. 4, the processor bus 111, the memory bus 112, and the system bus 113 are connected to the 3rd road connection controller 103. As shown in FIG. These buses are composed of address buses 411, 414, 417, control buses 412, 415, 481, data buses 413, 416, 419, respectively. In this embodiment, the tertiary connection controller 103 is constituted by two integrated circuits, that is, the bus-memory connection controller 401 and the data path switch 402. However, the third connection controller 103 may be configured by one or several integrated circuits.

The data path switch 402 connects three types of data buses of the processor data bus 413, the memory data bus 416, and the system data bus 419 in a third shape. The data path switch 402 connects, disconnects, and buses three data buses 413, 416, and 419 in accordance with the data path control signal 420 output from the bus-memory connection controller 401. Control the data I / O direction on the image.

On the other hand, the bus-memory connection controller 401 is connected to the processor address bus 411, the processor control bus 412, the system address bus 417, and the system control bus 418 so that the processor bus 111 and the system bus ( Monitor the status of 113). In addition, the bus-memory connection controller 401 outputs the signals of the memory address bus 414 and the memory control bus 415 and the data path control signal 420 to provide the main memory 104 and the data path switch 402. To control. The data path control signal 420 will be described in detail later.

The bus-memory connection controller 401 operates the system bus 113 independently by interlocking the processor bus 111 and the memory bus 112 when processor / main memory access is requested from the processor bus 111. When the DMA operation is requested from the system bus 113, the system bus 113 and the memory bus 112 are interlocked to operate the processor bus 111 independently. In addition, when there is an access request from the processor bus 111 to the system bus 113 or an access request from the system bus 113 to the processor bus 111, the bus-memory bus connection controller 401 is the processor bus 111. ) And the system bus 113 to operate in conjunction. When there is a conflict between a request from the processor bus 111 and a request from the system bus 113, for example, when there is a memory access request on both sides at the same time, the bus-memory connection controller 401 uses a bus ( It has a function of executing adjustment control such as performing a standby operation to either of the buses 111) and 113).

FIG. 5 is a diagram showing the internal structure of one embodiment of the data path switch 402 shown in FIG. 5, data path switch 402 is a data input / output driver 507, 508, 509 connected to processor data bus 413, memory data bus 416, and system data 419, respectively. Data latch circuits 501, 502, 503, data selectors 504, 505, and 506. The decoder 510 decodes the data path control signal 420 output from the bus-memory connection controller 401 to output the output enable signal 511 of each of the data input / output drivers 507, 508, and 509. , 512, 513 and data selectors 504, 505, 506 are arranged to generate respective selection signals 514, 515, 516, respectively.

The data latches 501, 502, and 503 are arranged to store input data from the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively. The selectors 504 to 506 are used to select the output data to the processor data bus 413, the memory data bus 416, and the system data bus 419 from input data from two different data buses, respectively. The control operation is executed as follows. That is, input data from any one of the three types of data buses is output to the other two types of buses, and the input data is passed only to one of the other buses. Therefore, the data path control signal 420 enables the three types of data buses to execute all the interlocking operations or any two kinds of the interlocking operations among the three.

FIG. 6 is a diagram showing one embodiment of the internal configuration of the bus-memory connection controller 401. As shown in FIG. In FIG. 6, reference numeral 401 denotes an I / O driver 601 to 604, a latch circuit 605 to 608, a decoder circuit 609, 610, an encoder circuit 611, 612. ), A sequencer 613 which is a logical operator, a memory control signal generator 616, and a data path control signal generator 617.

Input signals from the processor address bus 411, the processor control bus 412, the system address bus 417, and the system control bus 418 are respectively input / output drivers 601, 602, 603, Via 604, they are latched into latch circuits 605, 607, 606, and 608, respectively. The addresses input from the two types of address buses and latched in the latch circuits 605 and 606 are decoded by the decoder circuits 609 and 610, respectively. This decode operation result is processed together with the data of the latch circuits 607 and 608 which are input signals from the two types of control buses 412 and 418. That is, the encoder circuits 611 and 612 encode these inputs to generate signals representing the states of the processor bus 111 and the system bus 113, respectively. As a result, the bus-memory connection controller 401 can monitor the states of the processor bus 111 and the system bus 113, respectively.

Status signals encoded by the encoder circuits 611 and 612 with respect to the processor bus 111 and the system bus 113, respectively, are input to the sequencer 613 which is a logical operator. The sequencer 613 calculates the correspondence to each bus in accordance with the status signals of the two types of buses 111 and 113, determines the operation of the memory bus 112, and outputs it as code information. The sequencer 613 is composed of a general purpose microprocessor or a dedicated hardware configuration.

The code information output from the sequencer 613 is decoded by the decoder circuit 614, and respective output enable signals 618 to 621 to the I / O drivers 601 to 604, and the selection circuit ( The memory control code 623 and the data path control code 624 to the selection signal 622 of the 615, the memory control signal generator 616 and the data path control signal generator 617, and the I / O driver 602, respectively. Are output as control output signals 625 and 626 to the processor control bus 412 and the system control bus 418, respectively.

When the I / O driver 601 is requested to access the processor bus 111 from the system bus 113, the I / O driver 601 outputs the I / O address from the system address bus 417 to the processor address bus 411. The I / O driver 602 also outputs a control output signal 625 determined by the specifications of the processor bus 111 to the processor control bus 412. On the other hand, when the I / O driver 603 is requested to access the system bus 113 from the processor bus 111, the I / O driver 603 transfers the I / O address from the processor address bus 411 to the system address bus 417. Output The I / O driver 604 also outputs the control output signal 626 determined by the specifications of the system bus 113 to the system control bus 418.

When the address is input from the processor address bus 411 and the system address bus 417, and the access to the memory bus 112 is requested, the selection circuit 615 selects one of the input addresses and memory. The selected address is output to the address bus 414. The memory control signal generator 616 functions as a code conversion circuit, converts the memory control code 623 output from the decoder circuit 614 into a memory control signal determined by the specifications of the memory bus 112, and then stores the memory control bus 415. Output this signal with). The data path control signal generator 617 also functions as a code conversion circuit, converts the data path control code 624 output from the decoder circuit 614 into a data path control signal 420 for the data path switch 402, and The signal 420 obtained is output.

As described above, the bus-memory connection controller 401 in the third path connection controller 103 can execute control operations such as connection, disconnection, and standby operations of three types of buses.

In addition, an embodiment of various data and signals processed in the third connection controller 103 will be described in detail with reference to Figs.

9 shows a data path control signal 420 outputted from the memory access controller 401 to the data path switch 402, and an I / O driver decoded by the decoder 510 corresponding to the control signal 420, respectively. Enable signals 511, 512, 513 of 507, 508, 509 and selection signals 514, 515 of data selectors 504, 505, 506 , An example of the relationship of (516) is shown. In the same figure, each column of the uppermost master, slave and read / write indicates whether the master, slave and data transfer of the data transfer are read transfer or write transfer from master to slave. In the remainder of the uppermost stage, signal names corresponding to the signals 511 to 516 of FIG. 5 are described. In particular, the DT_CNT in the rightmost column at the top represents the data path control signal 420. This signal DT-CNT is represented by 3 bits in this embodiment. In the idle state where no data is transmitted, DT_CNT 420 is set to 0 ("0").

Each enable signal (DIR_P, DIR_M, DIR_S) 511, 512, and 513 is " 0 " when the I / O drivers 507, 508, and 509 are inputs, respectively. "1". The selection signal SEL_P 514 is "0" when the selector 504 selects the memory bus 112 side and "1" when selecting the system bus 113 side. The selection signal SEL_M 515 is " 0 " when the selector 505 selects the processor bus 111 side, and " 1 " when the system bus 113 side is selected. The selection signal SEL_S 516 is " 0 " when the selector 506 selects the processor bus 111 side, and " 1 " when selecting the memory bus 112 side. According to this figure, the selectors 504 to 506 and I / O drivers 507 to (in the data path switch 402) are input by the DT CNT 420 input to the decoder 510 of the data path switch 402. 509 can be controlled to enable connection direction control of three types of buses.

Next, the structure of FIG. 19 and the signal of FIG. 17 and FIG. 18 which show in detail the bus connected to the 3rd connection controller 103 of FIG. 4 for operation | movement of the 3rd connection controller 103 in this invention. It demonstrates using a timing chart.

In these figures, the same code | symbol as 1st and 4th figure has shown the same thing. 1910 and 1911 denote DMA master I / O devices and slave I / O devices respectively corresponding to the connection devices 105 connected to the system bus 113 described above. In FIG. 19, the arcnoise signal (ACK) 1902 is a response signal to the processor 101, which indicates the confirmation of data or the acquisition of data during a read or write operation, respectively.

The low address strobe signal (RAS) 1903, the column address strobe signal (CAS) 1904, and the write enable signal WE 1905 are respectively controlled to be controlled by the memory control bus 415 of the main memory 104. Part of the signal. The address multiplex signal AD_MPX is an internal signal of the bus-memory connection controller 401, and is set to a high state or a low state to output a low address or a column address, respectively. The system bus grant signal (S_GNT) 1906 permits the use of the system bus 113 to an I / O device 1910 that can be a bus mastership, that is, one of the access devices 105 and also become a DMA master. It is used. As a result, the I / O device 1910 is operable as a DMA mast. The address / data strobe signal (S_STB) 1907 is output from the system bus master. When in DMA access or processor I / O access, this signal 1907 is output to DMA master I / O device 1910 or bus-memory connection controller 401, respectively. During the read or write operation, an address or an assert period of address and data is output, respectively. The system bus slave arc snoop signal (S_ACK) 1908 is a response signal from the system bus slave. When it is a DMA access or processor system I / O access, this signal 1908 is output from the bus-memory connection controller 401 or slave I / O device 1911, respectively. System Bus Arc Surge Signal (S_ACK) 1908 Indicates assertion of data in read operation and acquisition of data in write operation. Signals S_GNT 1906, S_STB 1907, S_ACK 1908 and signal S_READ 1909 indicating the identification between the read and write operations belong to the control output signal 626 to be sent to the system control bus 418. The system bus address S_ADD is supplied to the system address bus 417. In addition, the system bus read / write signal S READ 1909 represents a read when it is high (H).

FIG. 16 shows one embodiment of the state transition of the sequencer 613 of the bus-memory connection controller 401. As shown in FIG. 10 to 15 are diagrams showing signals output at various stages of the state transition of each transfer operation, respectively. The processor / main memory read, the processor / main memory write, the processor / system bus device read, and the processor / Corresponds to the system bus device write, DMA read, and DMA write operations. In this figure, " O " represents the assertion of the signal, for example, " H " and " L " of S_READ 1909 represent the high state and the low state of the signal value, respectively. In addition, the bar (-) described above the signal name means that the signal is negative logic.

In FIG. 16, in S2, which is a step of the processor / system bus device read corresponding to FIG. 12, the standby operation is performed on the data assert of the system bus slave. In step S3 of the processor / system bus device write corresponding to FIG. 13, the write operation with respect to the write response is shown. In step S1 of the DMA read corresponding to FIG. 14, the standby operation is performed for the reception of S_STB, and then the transition to the next step S2 is determined in accordance with the read / write determination in the reception of the S_STB. In step S8 of the DMA read and step S5 of the DMA write, the standby operation is performed on the negate of the signal S_STB from the DMA master.

In the signal timings of FIGS. 17 and 18 related to the signal transmission defined by FIGS. 9 to 16, indicated by () is an output source of each signal. That is, (BMCC) indicates that a signal is output from the bus-memory connection controller (BMCC) 401, and (I / O) indicates the DMA master I / O device 1910 or processor system bus I / O access. A slave I / O device 1911 that becomes a slave is shown.

The latch circuits 501 and 502 of the data path switch 402 shown in FIG. 5 are constituted by edge trigger flip-flops, i.e., the latch operation of each latch circuit is shown in FIGS. The rising edge of the clock signal CLK shown in the figure is executed. In this regard, the start signal START 1901 is a transfer start signal. That is, while the start signal is output, the address used for the next operation is latched at the rising edge of the clock CLK. Further, the signal M_ADD represents a memory address to be sent to the memory address bus 414, and the signals P_DATA, M_DATA, and S_DATA represent data sent to the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively. Indicates.

The signals P_LATCH, M_LATCH, and S_LATCH represent data latched in the latch circuits 501, 502, and 503, respectively.

As can be seen from FIG. 16, step S3 of the processor / system bus device write shown in FIG. 13 includes one cycle of the standby operation for the assert of the signal S_ACK. In addition, in step S2 of the processor / system bus device read shown in FIG. 12, two cycles of the standby operation for the assert of the signal S_ACK 1408 are included.

Step S1 of the DMA read shown in FIG. 14 includes one cycle of standby operation for the assert of the signal S_STB 1407. In step S3, one cycle of standby operation is performed for the negate of the signal S_STB 1497. It is included.

In Fig. 18, in step S1 of the DMA write, one cycle of the wait operation is included for the assert of the S_STB 1407, but the wait for the negate in step S5 is executed only by the execution of the wait operation.

As described above, the bus-memory connection controller 401 and the data path switch 402 of FIGS. 4 to 6 are operated by the method shown in FIGS. 9 to 18, as shown in FIG. The operation of one embodiment of the connection controller 103 can be understood.

Although the configuration and operation of the fourth lane connection controller 705 and the like shown in FIG. 7 are not described in detail herein, the above-described configuration and operation of the third lane connection controller can be easily understood.

In addition, although the processor bus 111, the memory bus 112, and the system bus 113 are all address / data separated types as described with reference to FIGS. 4 to 19, the present invention differs from address / data. Of course, it can be applied to the medium bus. For example, when the processor bus 111 and the system bus 113 are address / data multiplexed buses, the processor address bus 411 and the processor data bus 413 become one bus in the system of FIG. In addition, the system address bus 417 and the system data bus 419 are combined into one bus. Thus, this bus is connected to both the bus-memory connection controller 401 and the data path switch 402. Moreover, although it demonstrated according to the basic concept of this invention, of course, it can change in various ways within the range which does not deviate from the summary of this invention.

As described above, according to the present invention, in a bus system including at least three buses of at least three types of processor buses, memory buses, and system buses, one of the other buses is used while two buses are interlocked. Since it can operate independently, there is an effect that the use efficiency of each bus is maximized. In particular, when the processor bus is connected to multiple processors or cache memory systems, it is possible to simultaneously perform DMA operations and data transfer between multiple processors or between the processor and the cache memory system, and to access the processor / main memory access and the system bus. This has the effect of simultaneously transferring data between multiple devices connected to the network.

Claims (29)

A bus system for an information processing apparatus, comprising: a processor, a processor bus to which one processor is connected, a main memory, a memory bus to which the main memory is connected, a connection device, a system bus to which the connection device is connected, and the processor bus and a memory Three types of buses such as a bus and a system bus are connected in a third shape, and when the processor bus and the memory bus are connected to each other, the transfer operation between the processor bus and the memory bus and the transfer operation on the system bus can be performed in parallel. When the memory bus and the system bus are connected, the transfer operation between the memory bus and the system bus and the transfer operation on the processor bus can be executed in parallel so that each of the three types of buses is physically independent. A third-party connection controller that performs bus-to-bus connections Bus system for the information processing apparatus is characterized in that. The third path connection controller is connected to a connection control means for outputting a data path control signal when the transfer operation is a transfer operation via a plurality of buses, and each data bus of the three types of buses. And data switch means for instructing bus-to-bus connection of two data buses of the three buses in accordance with the data bus signal inputted from the connection control means. 3. The data switching means according to claim 2, wherein the data switch means generates a selection signal in accordance with latch means for each bus for latching data on respective data buses of the three types of buses, and data bus control signals obtained from the connection controller means. The first generating means generates the output of the two latching means provided for each bus of the first generating means and each of the three types of buses, each of which corresponds to two types of buses other than the buses to which the bus is generated. And a first selection means for selecting in accordance with a selection signal. The processor bus and the system bus according to claim 2, wherein the connection control means determines whether the processor or the connection device performs the data transfer with the main memory when either the processor or the connection device executes data transfer. A second selection means for selecting an address signal on any one of the address buses and transmitting the selected address signal to the address bus of the memory bus; and receiving control signals and address signals of the processor bus and system bus, respectively, and the connection with the processor. Determining which of the devices executes data transfer with the main memory, and according to this determination generates at least the data bus control signal, a selection signal to the second selection means, and a control signal to the memory bus; Tablets comprising a means for generating Bus system for beam processing units. The bus system according to any one of claims 1 to 4, wherein at least one of the processor bus, the memory bus, and the system bus is an address / data multiplex bus. A bus system for an information processing apparatus, comprising: a processor, a processor bus to which one processor is connected, a main memory, a memory bus to which the main memory is connected, a connection device, a system bus to which the connection device is connected, and the processor bus and a memory When the three types of buses, the system bus and the system bus, are connected in a third shape, and the processor bus and the memory bus are connected in accordance with control signals and address signals obtained from the processor bus and the memory bus, respectively. Control the data transfer operation between the bus and the data transfer operation on the system bus in parallel, and control the memory bus and the system bus in accordance with control signals and address signals obtained from the processor bus and the memory bus, respectively. Memory bus and system when connecting A third path connection controller which controls the data transfer operation between the buses and the data transfer operation on the processor bus so as to execute the bus-to-bus connection so that each of the three types of buses can operate independently. Bus system for information processing apparatus, characterized in that. 7. The tertiary connection controller according to claim 6, wherein said tertiary connection controller is connected to connection control means for outputting a data bus control signal when said transfer operation is a transfer operation via several buses, and each data bus of said three types of buses. And data switch means for instructing bus-to-bus connection of two data buses of the three buses in accordance with the data bus signal inputted from the connection control means. 8. The data switching means according to claim 7, wherein said data switch means generates a selection signal in accordance with latch means for each bus for latching data on respective data buses of said three types of buses, and data bus control signals obtained from said connection control means. The first generating means generates the output of the two latching means provided for each bus of the first generating means and each of the three types of buses, each of which corresponds to two types of buses other than the buses to which the bus is generated. And a first selection means for selecting in accordance with a selection signal. 8. The processor bus and system bus according to claim 7, wherein the connection control means determines whether the processor or the connection device executes data transfer with the main memory when either the processor or the connection device executes data transfer. A second selection means for selecting an address signal on any one of the address buses and sending it to the address bus of the memory bus; and receiving control signals and address signals of the processor bus and system bus, respectively, and the connection with the processor. Determining which of the devices executes data transfer with the main memory, and according to this determination generates at least the data bus control signal, a selection signal to the second selection means, and a control signal to the memory bus; Tablets comprising a means for generating Bus system for beam processing units. 10. The bus system according to any one of claims 6 to 9, wherein at least one of the processor bus, the memory bus, and the system bus is an address / data multiplex bus. A bus system for an information processing apparatus, comprising: a processor, a processor bus to which one processor is connected, a main memory, a memory bus to which the main memory is connected, a connection device, a system bus to which the connection device is connected, and the processor bus and a memory Control buses and address buses of three types of buses and system buses. Controls that the processor outputs to the processor bus when each of the processor, main memory, and connected device executes a transfer operation on the bus system. The three types of buses are controlled according to respective logic control in response to a signal and an address signal, a control signal and an address signal outputted from the main memory device to a memory bus, a control signal outputted from the connection device to a system bus, and an address signal. And the transfer operation is via multiple buses. Connection bus means for outputting a data bus control signal during operation and two data buses of the three buses in accordance with data bus control signals connected to respective data buses of the three types of buses and input from the connection control means. A third switch configured to connect the three types of buses in a third shape and to perform the inter-bus connection so that each of the three types of buses can be physically independently operated. A bus system for an information processing apparatus, comprising a connection controller. The data switching means according to claim 11, wherein said data switch means generates a selection signal in accordance with latch means for each bus for latching data on respective data buses of said three types of buses, and a data bus control signal obtained from said connection control means. The first generating means generates the output of the two latching means provided for each bus of the first generating means and each of the three types of buses, each of which corresponds to two types of buses other than the buses to which the bus is generated. And a first selection means for selecting in accordance with a selection signal. 12. The processor bus and system bus according to claim 11, wherein the connection control means determines whether the processor or the connection device performs the data transfer with the main memory when either the processor or the connection device performs data transfer. A second selection means for selecting an address signal on any one of the address buses and transmitting the selected address signal to the address bus of the memory bus; and receiving control signals and address signals of the processor bus and system bus, respectively, and the connection with the processor. It is determined which of the devices executes the main memory and the data transfer, and according to the determination, at least a second to generate the data bus control signal, the selection signal to the second selection means, and the control signal to the memory bus; Information destination comprising a generating means Bus system for refurbishment. The bus system according to any one of claims 11 to 13, wherein at least one of the processor bus, the memory bus, and the system bus is an address / data multiplexed bus. An IC device for an information processing bus system controller, comprising: a connection portion for connecting three types of buses in a third shape, a processor bus to which a processor is connected, a memory bus to which a main memory is connected, and a system bus to which a connection device is connected; When the processor bus and the memory bus are connected via the connection portion, the processor bus and the memory bus are controlled to execute in parallel with the transfer operation between the processor bus and the memory bus, and the connection between the memory bus and the system bus is performed. When connecting via the part, the transfer operation between the memory bus and the system bus and the transfer operation on the processor bus can be executed in parallel, so that each of the three types of buses can operate independently independently through the connection part. To a third-level connection controller that IC device for an information processing system, a bus controller, characterized in that that generated. 16. The control circuit according to claim 15, wherein said tertiary connection controller outputs a data bus control signal when said transfer operation is a transfer operation via several buses and said connection to each data bus of said three types of buses. An information processing bus system controller connected via a portion, said data switching means instructing connection between two buses of said three buses in accordance with a data bus signal inputted from said connection control means; IC device. 17. The data switching means according to claim 16, wherein said data switch means generates a selection signal in accordance with a latch means for each bus for latching data on each data bus of said three types of buses, and a control signal of a data bus obtained from said connection control means. The first generating means is provided for each of the first generating means and each of the three types of buses, and the first generating means generates outputs of the two latching means each corresponding to two types of buses other than the buses to which the first generating means and the buses respectively correspond. An IC device for an information processing bus system controller comprising first selecting means for selecting in accordance with a selection signal. 17. The apparatus according to claim 16, wherein the connection control means determines whether or not the processor or the connection device performs data transfer with the main memory depending on which one obtained from the connection portion performs data transfer with the main memory. Second selection means for selecting an address signal on one of the processor bus and the system bus and sending it to the address bus of the memory bus; and receiving control signals and address signals of the processor bus and the system bus, respectively. It is determined which of the processor and the connected device performs main memory and data transfer, and according to this determination at least a control signal of the data bus, a selection signal to the second selection means, and a control signal to the memory bus. A second generating means for outputting The information processing bus system controller for the IC device, characterized in that. 19. The IC device according to any one of claims 15 to 18, wherein the connection portion is connected to the three types of buses, at least one of which is an address / data multiplex bus. An IC device for an information processing bus system controller, comprising: a connection portion for connecting three types of buses in a third shape, a processor bus to which a processor is connected, a memory bus to which a main memory is connected, and a system bus to which a connection device is connected; The processor bus and the memory bus are connected to the processor bus and the memory bus, and the processor bus and the memory bus are connected to the processor bus and the memory bus in accordance with a control signal and an address signal obtained from the processor bus and the memory bus. When connected via a control, a control signal and an address obtained by controlling the transfer operation between the processor bus and the memory bus and the data transfer operation on the system bus can be executed in parallel, and obtained through the connection portion in each of the processor bus and the memory bus. Memo according to signal When the bus and the system bus are connected via the connection portion, the data transfer operation between the memory bus and the system bus and the data transfer operation on the processor bus can be executed in parallel, so that each of the three types of buses can be used. An IC device for an information processing bus system controller comprising a third connection controller that performs a bus-to-bus connection so as to operate physically independently through a connection portion. 21. The apparatus as claimed in claim 20, wherein the third path connection controller is connected to each data bus of the three types of buses and to connection control means for outputting a data bus control signal when the transfer operation is a transfer operation via multiple buses. An information processing bus system controller connected via a portion, said data switching means instructing connection between two buses of said three buses in accordance with a data bus signal inputted from said connection control means; IC device. 22. The data switching means according to claim 21, wherein said data switch means generates a selection signal in accordance with a latch means for each bus for latching data on each data bus of said three types of buses, and a control signal of a data bus obtained from said connection control means. The first generating means is provided for each of the first generating means and each of the three types of buses, and the first generating means generates outputs of the two latching means each corresponding to two types of buses other than the buses to which the first generating means and the buses respectively correspond. An IC device for an information processing bus system controller comprising first selecting means for selecting in accordance with a selection signal. 22. The apparatus according to claim 21, wherein the connection control means determines whether the processor or the connection device executes data transfer with the main memory when any one of the processor and the connection device executes data transfer with the main memory. Second selection means for selecting an address signal on one of the processor bus and the system bus and sending it to the address bus of the memory bus; and receiving control signals and address signals of the processor bus and the system bus, respectively. It is determined which of the processor and the connected device executes data transfer with the main memory, and according to this determination at least the data bus control signal, a selection signal to the second selection means and a control signal to the memory bus And a second generating means for outputting An IC device for an information processing bus system controller, comprising: 24. The IC device according to any one of claims 20 to 23, wherein the connection portion is connected to the three types of buses, at least one of which is an address / data multiplex bus. In an IC device for an information processing bus system controller, a connection connected to each control bus and address bus of three types of buses: a processor bus connected with a processor, a memory bus connected with a main memory, and a system bus connected with a connected device. Having a portion, wherein each of the processor bus, main memory, and connected device performs a transfer operation on a bus system, a control signal and an address signal output from the processor to the processor bus, and a control output from the main memory to the memory bus. In response to a signal and an address signal, a control signal output from the connection device to the system bus, and an address signal through the connection portion to control the processor bus, the memory bus, and the system bus according to respective logic protocols, and the transfer operation. Through this connection, several buses The three types of connection control means for outputting a data bus control signal and a data bus signal connected to each data bus of the three types of buses through the connection portion and inputted from the connection control means in a transmission operation via A data switch means for instructing bus-to-bus connection of two types of data buses of the buses, wherein the three types of buses are connected in a tertiary shape at the connection portion so that each of the three types of buses is physically independent. An IC device for an information processing bus system controller comprising a third connection controller that performs bus-to-bus connection for operation. 26. The connection controller according to claim 25, wherein the third lane connection controller outputs a data bus control signal when the transfer operation is a transfer operation via multiple buses and the connection to each data bus of the three types of buses. An information processing bus system controller connected via a portion, said data switching means instructing connection between two buses of said three buses in accordance with a data bus signal inputted from said connection control means; IC device. The data switching means according to claim 26, wherein the data switch means generates a selection signal in accordance with latch means for each bus for latching data on respective data buses of the three types of buses, and data bus control signals obtained from the connection control means. The first generating means selects the output of the two latch means provided in each of the generating means of 1 and each of the three types of buses, and corresponding to two kinds of buses, each of which is different from the bus to which the bus is generated. An IC device for an information processing bus system controller comprising first selecting means for selecting in accordance with a signal. 27. The apparatus according to claim 26, wherein the connection control means determines whether the processor or the connection device executes data transfer with the main memory when the one of the processor and the connection device performs data transfer with the main memory. Second selection means for selecting an address signal on one of the processor bus and the system bus and sending it to the address bus of the memory bus; and receiving control signals and address signals of the processor bus and the system bus, respectively. It is determined which of the processor and the connected device executes data transfer with the main memory, and according to this determination at least the data bus control signal, a selection signal to the second selection means and a control signal to the memory bus Second generating means for outputting An IC device for an information processing bus system controller comprising: 29. The IC device according to any one of claims 25 to 28, wherein the connection portion is configured to be connected to the three types of buses, at least one of which is an address / data multiplexed bus.