JP4102740B2 - Information processing device - Google Patents

Description

  The present invention relates to a bus system used in an information processing apparatus such as a workstation, a personal computer, or a word processor.

  A bus system in an information processing apparatus is conventionally disclosed in L., Byte, Vol. 14, No. 12 (1989), pages 417-424, (BYTE, Volume 14, Number 12 (1989), pp. 417-424). A configuration in which the memory bus and the system bus are individually connected to the processor bus, or the processor bus and the memory bus are individually connected to the system bus, as in the bus system described in Brett Glass, “INSIDEEISA” It was.

  In the former, since the processor bus cannot operate independently during so-called direct memory access (hereinafter referred to as DMA) in which the system bus and the memory bus operate in conjunction, the use efficiency of the processor bus is deteriorated. On the other hand, the latter has a problem that the use efficiency of the system bus deteriorates because the system bus cannot operate independently during so-called main memory access in which the processor bus and the memory bus operate in an interlocked manner.

  The configuration and problems of these conventional bus systems will be described in detail later with reference to the drawings.

  An object of the present invention is to provide a bus system of an information processing apparatus that maximizes the usage efficiency of each bus.

  Another object of the present invention is to provide a bus system capable of simultaneously performing a linked operation of a processor bus and a memory bus and an independent operation of a system bus.

  It is a further object of the present invention to provide a bus system capable of simultaneously performing a linked operation of a system bus and a memory bus and an independent operation of a processor bus.

  Still another object of the present invention is to provide a bus system for an information processing apparatus that maximizes the use efficiency of each bus when at least three of three types of buses, a system bus, a memory bus, and a processor bus, are interconnected. Is to provide.

  In order to achieve the above object, in the present invention, at least three buses of the first bus, the second bus, and the third bus are connected in a three-way structure, and any two of the three buses are operated in an interlocking manner. During this time, the other buses can be operated independently.

  That is, in the present invention, a processor, a main memory, an input / output device, a first bus connected to the processor, a second bus connected to the main memory, and a third bus connected to the input / output device. In the information processing apparatus, the first bus, the second bus, and the third bus are connected, and data can be transferred between any two of the processor, the main memory, and the input / output device. A first data transfer unit configured to transfer a first data signal between the processor and the main memory using the connected first bus and the second bus. A second data transfer mode for transferring a second data signal between the main memory and the input / output device using the connected second bus and the third bus, and the connected 3rd bus and the above Information processing characterized by enabling independent data transfer modes each comprising a third data transfer mode for transferring a third data signal between the input / output device and the processor using a bus. Device.

  As a result, the usage efficiency of the three types of buses can be maximized.

  In order to achieve the above object, in the present invention, at least three types of buses, that is, a processor bus, a memory bus, and a system bus are connected in a three-way manner, and any two of the three types of buses are operated in an interlocking manner. During this time, another type of bus is configured to be able to operate independently.

  That is, in the present invention, a processor bus to which at least one processor is connected, a memory bus to which main memory is connected, and a system bus to which connection devices such as at least one input / output device (hereinafter referred to as I / O device) are connected. These three types of buses are provided with control means for connecting at least three-way connections, and this control means enables various buses to be interconnected.

  That is, in the present invention, the bus system of the information processing apparatus includes a processor bus to which at least one processor is connected, a memory bus connected to the main memory, a system bus to which at least one connection device is connected, These three types of buses are connected to each other and are configured by connection control means for interconnecting these three types of buses.

  In the present invention, the connection control means includes three data buses connected to each other, a data path switching means for transferring data on these buses to each other, and each of the three kinds of buses, the control bus and the address bus. The bus / memory connection controller is connected to transfer control signals and addresses on the buses to each other and generate data path control signals to the data path switching means.

  Preferably, the data path switching means and the bus memory connection controller are individually or integrally formed on one integrated circuit.

  Furthermore, in the present invention, the three types of buses are not one each, and even when any of the three types of buses is a plurality, the connection control means is similarly configured so that these buses can be interconnected. Can do.

  In the configuration of the present invention described above, the processor bus, the memory bus, and the system bus are connected to each other in at least a three-way configuration, so that, for example, a processor on the processor bus accesses a main memory on the memory bus. In the case of accessing the processor main memory, the data is transferred only through the processor bus and the memory bus and does not go through the system bus, so that the system bus can operate independently. On the other hand, in the case of DMA that accesses the main storage memory on the memory bus from the connected device on the system bus, the data is transferred only through the system bus and the memory bus, and does not go through the processor bus, so the processor bus operates independently It becomes possible to do.

  As a result, the usage efficiency of the three types of buses can be maximized.

  As described above, according to the present invention described in detail, one or more other buses can operate independently while any two of at least three types of buses operate in conjunction with each other. This has the effect of maximizing the use efficiency of the. In particular, when a plurality of processors are connected on the processor bus, or when a cache memory system is connected, data can be transferred simultaneously between the DMA operation and the plurality of processors or between the processor and the cache memory system. Also, there is an effect that the processor main memory access and data transfer between a plurality of system bus connection devices can be performed simultaneously.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS. Of these, FIGS. 2 and 3 show a configuration diagram of a bus system in the prior art, which will be described in detail here for comparison with the present invention.

  In FIG. 1, FIG. 2 and FIG. 3, in common, 101 is an N number (N is an integer), 102 is a cache memory system (cache), 104 is a main memory, 105 is M (M Is an integer) system bus connection device. The system bus connection device 105 is a so-called input / output (I / O) device such as a disk / file controller, a drawing / display controller, a network / communication controller, or the like. 111 is a processor bus, 112 is a memory bus, and 113 is a system bus. In FIG. 1, 103 is a three-way connection controller, 201 and 301 in FIGS. 2 and 3 are bus connection controllers, and 202 and 302 are memory connection controllers.

  In the conventional bus system shown in FIGS. 2 and 3, in FIG. 2, the system bus 113 and the memory bus 112 are independently connected to the processor bus 111 by the bus connection controller 201 and the memory connection controller 202, respectively. Yes. On the other hand, in FIG. 3, the processor bus 111 and the memory bus 112 are configured to be independently connected to the system bus 113 by the bus connection controller 301 and the memory connection controller 302, respectively.

  In the configuration of FIG. 2, the data is transferred between the connection device 105 of the system bus 113 and the main memory on the memory bus 112 via the processor bus 111 in the DMA operation. Therefore, independent operation of the processor bus 111 such as data transfer between the processor 101 and the cache 102 or between the plurality of processors 101 cannot be performed simultaneously with the DMA operation. On the other hand, in the configuration of FIG. 3, since data transfer is performed between the processor 101 and the main memory 104, so-called processor main memory access is performed via the system bus 113. Independent operations of the system bus 113 such as data transfer between the processors 105 cannot be performed simultaneously with the processor main memory access.

  On the other hand, in the bus system of FIG. 1 which is the first embodiment of the present invention, three kinds of buses, that is, the processor bus 111, the memory bus 112, and the system bus 113 are connected in a three-way manner by the three-way connection controller 103. Have a configuration. Accordingly, in the case of the DMA operation, since the processor bus 111 is not passed, the independent operation of the processor bus 111 can be executed simultaneously with the DMA operation. In the case of processor main memory access, since the system bus 113 is not passed, the independent operation of the system bus 113 can be executed simultaneously with the processor main memory access. As a result, even in the case of DMA and processor main memory access, the usage efficiency of the three types of buses can be maximized.

  An example of performance evaluation of the bus system of the first embodiment of the present invention shown in FIG. 1 and the conventional bus system shown in FIGS. 2 and 3 will be described below, and the effects of the first embodiment of the present invention will be described. Explain quantitatively.

  1, 2, and 3, the maximum data throughput of the processor bus 111 is 400 megabytes / second, the maximum data throughput of the memory bus 112 is 400 megabytes / second, and the maximum data throughput of the system bus 113 is 200 megabytes / second. Seconds. The main memory access ratio in the processor bus 111 is 40%, the DMA ratio in the system bus 113 is 70%, and the maximum bus acquisition ratio of the bus connection controllers 201 and 301 is 50%. Under the above conditions, the performance evaluation of each bus system when the processor bus 111 and the system bus 113 try to operate at the maximum data throughput is as follows.

  First, in the conventional bus system of FIG. 2, when the system bus 113 attempts to operate at a maximum throughput of 200 megabytes / second, a DMA request of 140 megabytes / second, which is 70%, is sent to the bus connection controller 201. Since the bus connection controller 201 can acquire the bus up to 200 megabytes / second, which is 50% of 400 megabytes / second, for the processor bus 111, it acquires all 140 megabytes / second DMA requests. As a result, the system bus 113 can operate at 200 megabytes / second, but the processor bus 111 can practically operate only at (400-140) = 260 megabytes / second because of the DMA request. At this time, the processor main memory access is 104 megabytes / second, which is 40% of 260 megabytes / second. Therefore, the request to the memory bus 112 is (140 + 104) = 254 megabytes / second, and the memory bus 112 can respond to this request. In summary, the usage efficiency of the three types of buses in the conventional bus system of FIG. 2 is as follows: the processor bus 111 is 260/400 = 65%, the memory bus 112 is 254/400 = 63.5%, and the system bus 113 is 200/200 = 100%.

  Next, in the conventional bus system of FIG. 3, when the processor bus 111 tries to operate at a maximum throughput of 400 megabytes / second, 40% of the main memory access request of 160 megabytes / second is sent to the bus connection controller 301. . The bus connection controller 301 can acquire the bus for the system bus 113 only up to 100 megabytes / second, which is 50% of 200 megabytes / second. Thus, processor main memory accesses are processed only at 100 megabytes / second, so that the processor bus 111 can only operate at 250 megabytes per second, where 100 megabytes per second is 40%. At this time, the system bus 113 operates substantially at (200-100) = 100 megabytes / second. Thus, the DMA request is 70 megabytes / second, which is 70% of 100 megabytes / second. As a result, the request to the memory bus 112 is (100 + 70) = 170 megabytes / second, and the memory bus 112 can respond to this request. In summary, the usage efficiency of the three types of buses in the conventional bus system of FIG. 3 is as follows: the processor bus 111 is 250/400 = 62.5%, the memory bus 112 is 170/400 = 42.5%, and the system bus 113 is Is 100/200 = 50%.

  On the other hand, in the bus system of FIG. 1 which is the first embodiment of the present invention, when the processor bus 111 tries to operate at 400 megabytes / second, 40% of the main memory access request of 160 megabytes / second is received. , And sent to the three-way connection controller 103. Further, if the system bus 113 attempts to operate at 200 megabytes / second, 70% of the 140 megabyte DMA request is sent to the three-way connection controller 103, respectively. The three-way connection controller 103 combines the processor main memory access request and the DMA request, and sends a request of (160 + 140) = 300 megabytes / second to the memory bus 112, and the memory bus 112 responds to this request. Therefore, the processor bus 111 can operate at 400 megabytes / second and the system bus 113 can operate at 200 megabytes / second. As described above, the usage efficiency of the three types of buses in the bus system of the first embodiment of the present invention shown in FIG. 1 is that the processor bus is 400/400 = 100%, the memory bus 112 is 300/400 = 75%, and the system The bus 113 is 200/200 = 100%.

  The above results are shown in Table 1. As is apparent from Table 1, it can be seen that the bus system of FIG. 1 according to the present invention maximizes the usage efficiency of the three types of buses.

  Prior to an embodiment showing a specific configuration of the present invention, the bus systems according to the second and third embodiments of the present invention will be described with reference to FIGS.

  7 and 8, reference numerals 701 and 703 denote single-configuration processors 1 to N that can connect individual cache memory systems (Cache), and 801 denote N multi-configuration processors that can connect individual cache memory systems. Reference numerals 711 and 712 denote processor buses for connecting the single-configuration processors 701 and 703 and the four-way connection controller 705, and reference numeral 705 denotes a four-way connection controller for connecting the processor buses 711 and 712, the memory bus 112, and the system bus 113. is there. Reference numerals 702, 704, and 802 denote cache memory systems individually connected to the processors 701, 703, and 801, respectively. The system bus connection device 105 is an I / O device similar to the previous embodiment.

  In the second embodiment of the present invention shown in FIG. 7, four types of four buses, that is, two processor buses 711 and 712, a memory bus 112, and a system bus 113 are formed into a four-forked shape by a four-way connecting controller 705. It is connected to the. Processors 701 and 703 are single-configuration processors to which individual cache memory systems 702 and 704 can be connected. Therefore, the processors 701 and 703 can directly access the individual cache memories 702 and 704 without going through the processor bus, but cannot share the processor bus.

  In FIG. 7, a four-way connection controller 705 performs communication between processors 701 and 703 in parallel with DMA by controlling connection of three types of four buses, or main memory access by the processor 701. The system 703 can perform operations such as performing system bus access in parallel.

  As a result, the use efficiency of the three types of four buses can be maximized in the present embodiment as in the previous embodiment.

  8 has a configuration in which three types of buses, that is, a processor bus 111, a memory bus 112, and a system bus 113, are connected on a three-way road by a three-way connection controller 103, similarly to the first embodiment shown in FIG. The processor 801 is a multi-configuration processor capable of connecting individual cache memory systems (cache). Therefore, each of the processors 801 can access the individual cache memory 802 without going through the processor bus, and can share the processor bus 111. Further, in the bus system according to the third embodiment of the present invention shown in FIG. 8, as in FIG. 1, independent operation of the DMA and the processor bus 111 is performed in parallel, or main memory access from the processor bus 111 and the system bus are performed. It is possible to perform operations such as performing the operations of 113 in parallel, so that the use efficiency of the three types of buses can be maximized as in the first embodiment.

  Next, specific examples of the main part of the above-described embodiment of the present invention will be described in detail with reference to FIGS. In particular, the detailed configuration of the three-way connection controller 103 of the first and third embodiments shown in FIGS. 1 and 7 will be described, but the four-way connection controller 705 shown in FIG. 7 can be similarly configured.

  4 shows a configuration diagram of the three-way connection controller 103 by two integrated circuits. In FIG. 4, a processor bus 111, a memory bus 112, and a system bus 113 are connected to the three-way connection controller 103. Each of these buses is constituted by an address bus 411, 414, 417, a control bus 412, 415, 418, and a data bus 413, 416, 419. In the present embodiment, the three-way connection controller 103 includes two integrated circuits, that is, a bus / memory connection controller 401 and a data path switch 402. However, the three-way connection controller 103 can be configured by one or three or more integrated circuits.

  The data path switch 402 connects three data buses, a processor data bus 413, a memory data bus 416, and a system data bus 419, in a three-way configuration. Then, in accordance with the data path control signal 420 output from the bus / memory connection controller 401, connection and disconnection of the three types of data buses 413, 416, and 419 and control of the data input / output direction are performed. On the other hand, the bus / memory connection controller 401 is connected to a processor address bus 411, a processor control bus 412, a system address bus 417, and a system control bus 418. Then, the states of the processor bus 111 and the system bus 113 are monitored. The memory address bus 414, the memory control bus 415, and the data path control signal 412 are output to control the main memory 104 and the data path switch 402. The data path control signal 412 will be described in detail later.

  When a processor main memory access is requested from the processor bus 111, the bus / memory connection controller 401 operates the processor bus 111 and the memory bus 112 in an interlocked manner and operates the system bus 113 independently. Further, when DMA is requested from the system bus 113, the system bus 113 and the memory bus 112 are operated in an interlocked manner, and the processor bus 111 is operated independently. When there is an access request from the processor bus 111 to the system bus 113 or an access request from the system bus 113 to the processor bus 111, the processor bus 111 and the system bus 113 are operated in an interlocking manner. Further, when a request from the processor bus 111 and a request from the system bus 113 conflict, for example, when there is a memory access request from both simultaneously, a wait operation is performed on one of the buses. It has a function to perform arbitration control.

  FIG. 5 is a diagram showing an internal configuration of an embodiment of the data path switch 402 in FIG. In FIG. 5, 507, 508, and 509 are data input / output drivers connected to the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively, 501, 502, and 503 are data latch circuits (Latch), 504, 505, Reference numeral 506 denotes a data selector. The decoder circuit 510 decodes the data path control signal 420 output from the bus / memory connection controller 401, outputs enable signals (Enable) 511, 512, and 513 of the input / output buffers 507, 508, and 509, a data selector 504, Select signals (Select) 514, 515, and 516 of 505 and 506 are generated.

  Data latches 501, 502, and 503 latch input data from the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively. The selectors 504, 505, and 506 respectively select output data to the processor data bus 413, the memory data bus 416, and the system data bus 419 from input data from the other two types of data buses. As a result, control is performed such that input data from any one of the three types of data buses is output to both of the other two types of data buses, or data is output to only one and not to the other. It can be carried out. Therefore, the data path control signal 420 can perform all the three types of data bus linked operations, or any two types of linked operations among the three types, and another type of independent operation.

  FIG. 6 is a diagram showing an embodiment of the internal configuration of the bus / memory connection controller 401 in FIG. In FIG. 6, reference numerals 601, 602, 603, and 604 denote input / output drivers, and reference numerals 605, 606, 607, and 608 denote latch circuits (Latch). Reference numerals 609 and 610 denote decoder circuits, 611 and 612 denote encoder circuits, 613 denotes a sequencer which is a logical operation unit, and 614 denotes a decoder circuit. Reference numeral 615 denotes a selector, 616 denotes a memory control signal generator, and 617 denotes a data path control signal generator.

  Input signals from the processor address bus 411, the processor control bus 412, the system address bus 417, and the system control bus 418 are input to the latch circuits 605, 607, 606, and 608 via the input / output drivers 601, 602, 603, and 604, respectively. Latched. Addresses input from the two types of address buses and latched in the latch circuits 605 and 606 are decoded by the decoder circuits 609 and 610, respectively. The decoding results are combined with the data of the latch circuits 607 and 608 which are signal inputs from the two types of control buses 412 and 418, and are converted into signals indicating the states of the processor bus 111 and the system bus 113 by the encoder circuits 611 and 612, respectively. Encoded. As a result, the bus / memory connection controller 401 can monitor the states of the processor bus 111 and the system bus 113.

  The status signals of the processor bus 111 and the system bus 113 encoded by the encoder circuits 611 and 612 are input to a sequencer 613 that is a logical operation unit. The sequencer 613 calculates the correspondence to each bus and the operation of the memory bus 112 from the status signals of the two types of buses 111 and 113, and outputs it as code information. The sequencer 613 includes a general-purpose microprocessor or a dedicated hardware configuration.

  Code information output from the sequencer 613 is decoded by the decoder circuit 614, and output enable signals 618, 619, 620, 621 of the input / output drivers 601, 602, 603, 604, a select signal 622 of the selector circuit 615, and memory control signal generation 616, a memory control code 623 to the data path control signal generation unit 617, a data path control code 624, and a control output signal 625 to the processor control bus 412 and the system control bus 418 via the input / output drivers 602 and 604, respectively. , 626.

  The input / output driver 601 outputs the input / output address from the system address bus 417 to the processor address bus 411 when the system bus 113 accesses the processor bus 111. Further, the input / output driver 602 outputs a control output signal 625 defined by the specifications of the processor bus 111 to the processor control bus 412. On the other hand, the input / output driver 603 outputs the input / output address from the processor address bus 411 to the system address bus 417 when the processor bus 111 accesses the system bus 113. The input / output driver 604 outputs a control output signal 626 defined by the specification of the system bus 113 to the system control bus 418.

  The selector circuit 615 selects one of the addresses from the processor address bus 411 and the system address bus 417 and outputs it to the memory address bus 414 when the memory bus 112 is accessed. The memory control signal generation unit 616 functions as a code conversion circuit, converts the memory control code 623 output from the decoder circuit 614 into a memory control signal defined by the specifications of the memory bus 112, and outputs the memory control signal to the memory control bus 415. The data path control signal generation unit 617 also functions as a code conversion circuit. The data path control code 624 output from the decoder circuit 614 is converted into a data path control signal 420 for the data path switch 402 and output.

  The bus / memory connection controller 401 in the three-way connection controller 103 described in detail above can control the connection, disconnection, weight, and the like of the three types of buses.

  Next, an example of various data and signals in the above-mentioned three-way connection controller 103 will be described in detail with reference to FIGS.

  FIG. 9 shows a data path control signal 420 output from the bus / memory connection controller 401 to the data path switch 402, and corresponding enable signals 511 of the input / output drivers 507, 508, and 509 decoded by the decoder 510, 512 shows an example of a relationship with select signals 514, 515, 516 of 512, 513 and data selectors 504, 505, 506. In the figure, each column of the master (master), slave (Slave), and read / write (Lead / Wrete) in the top row shows the data transfer master / slave, and whether the data transfer is a read transfer from the master to the slave. It means transfer. In the remaining part of the uppermost stage, signal names corresponding to the above-described signals 511 to 516 in FIG. 5 are described. DT-CNT in the rightmost column at the top is the data path control signal 420. The data path control signal (DT-CNT) 420 is represented by 3 bits in this embodiment. In an idle state (Idel) in which no transfer is performed, DT-CNT 420 is 0 (“000”).

  The enable signals (DIR-P, DIR-M, DIR-S) 511, 512, and 513 are “0” when the input / output drivers 507, 508, and 509 are input, and “1” when they are output. . The select signal (SEL-P) 514 is “0” when the selector 504 selects the memory bus 112 side and is “1” when the system bus 113 side is selected. The select signal (SEL-M) 515 is “0” when the selector 505 selects the processor bus 111 side, and is “1” when the selector 505 selects the system bus 113 side. Further, the select signal (SEL-S) 516 is “0” when the selector 506 selects the processor bus 111 side, and “1” when the selector 506 selects the memory bus 112 side. According to this figure, the selectors 504 to 506 and the input / output drivers 507 to 509 in the data path switch 402 can be controlled by the DT-CNT 420 input to the decoder 510 of the data path switch 402, and the connection directions of the three types of buses. Control becomes possible.

  Next, the operation of the three-way connection controller 103 according to the present invention will be described with reference to the configuration diagram of FIG. 19 in which the bus connected to the three-way connection controller 103 of FIG. 4 is detailed and the timing charts of FIGS.

  In these drawings, the same reference numerals as those in FIGS. 1 and 4 denote the same components. Reference numerals 1910 and 1911 denote DMA master I / O devices and slave I / O devices corresponding to the system bus connection device 105, respectively. In FIG. 19, an acknowledge signal (ACK) 1902 is a response signal to the processor 101, and indicates data confirmation at the time of reading and data acquisition at the time of writing.

  A row address strobe signal (RAS) 1903, a column address strobe signal (CAS) 1904, and a write enable signal (WE) 1905 are each part of a memory control signal sent to the memory control bus 415 of the main memory 104. The address selection signal (AD-MPX) is an internal signal of the bus memory connection controller 401, and outputs a row address when this signal is high and a column address when it is low. A system bus ground signal (S-GNT) 1906 is the system bus connection device 105, which grants permission to use the system bus 113 to the I / O device 1910 that can be a DMA master and enables it to become a DMA master. It is. The address / data strobe signal (S-STB) 1907 is output by the system bus master, and is output by the DMA master I / O device 1910 during DMA access, and the bus / memory connection controller during processor I / O access. 401 is output, and the address is output at the time of reading, and both the address and data are output at the time of writing. A system bus slave response signal (S-ACK) 1908 is a response signal of the system bus slave, and is output by the bus / memory connection controller 401 at the time of DMA access, and slave I at the time of processor system bus I / O access. / O device 1911 outputs. Data is confirmed at the time of reading and data fetching at the time of writing. The S-GNT 1906, the S-STB 1907, the S-ACK 1908, and the signal indicating the read / write (S-READ) 1909 belong to the control output signal 626 sent to the system control bus 418. The system bus address (S-ADD) is sent to the system address bus 417. The system bus read / write signal (S-READ) indicates a read when it is high (H).

  FIG. 16 is a diagram showing an example of state transition of the sequencer 613 of the bus memory connection controller 401. 10 to 15 are diagrams showing signals output at a plurality of steps of the respective state transitions of the respective transfer types shown in FIG. 16, and are respectively a processor main memory read, a processor main memory write, and a processor system bus device. It corresponds to read, processor system bus device write, DMA read, and DMA write. “O” marks indicate signal assertion, and “H” and “L” in S-READ 1909 mean that signal values are high and low, respectively. Moreover, the bar described above the signal name means that the signal is negative logic.

  In FIG. 16, in step S2 of the processor system bus device read corresponding to FIG. 12, the system bus slave waits for data confirmation. In step S3 of the processor system bus device write corresponding to FIG. 13, a write response is waited. In step S1 of DMA read corresponding to FIG. 14, S-STB reception wait is performed, and the transition destination to the next step S2 is determined according to the read / write determination when receiving the S-STB. In step S8 of DMA read and S5 of DMA write, the S-STB negation wait of the DMA master is performed.

  In the time charts of FIGS. 17 and 18 which are transfer time charts defined by FIGS. 9 to 16, those indicated by () are output sources of the respective signals.

  That is, (BMCC) indicates that the bus memory connection controller 401 outputs, and (I / O) indicates the DMA master I / O device 1910 or the slave I / O device that is the slave of the processor system bus I / O access. 1911 respectively.

  Now, the latch circuits 501, 502, and 503 of the data path switch 402 shown in FIG. 5 are configured by edge trigger flip-flops, and are latched at the rising edge of the clock (CLK) shown in FIGS. A start signal (START) 1901 is a transfer start signal output from the processor 1, and an address is latched and used at the rising edge of the output clock (CLK). Otherwise, M-ADD indicates the memory address sent to the memory address bus 414. P-Data, M-data, and S-data indicate data sent to the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively. Further, P-Latch, M-Latch, and S-Latch indicate data latched in the latches 501, 502, and 503, respectively.

  In step S3 of the processor system bus device write shown in FIG. 13, there is one cycle of wait for S-ACK assertion waiting. Also, in step S2 of the processor system bus device read shown in FIG. It is clear from FIG. 16 that the wait due to S-STB assertion waits in step S1 of DMA read shown in FIG. 14 and that the wait due to S-STB negation waits in step S3.

  In FIG. 18, in step S1 of the DMA write, the wait due to the S-STB assertion waits for one cycle, but the negate wait in step S5 is executed with no wait.

  By operating the bus memory connection controller 401 and the data path switch 402 of FIGS. 4, 5, and 6 by the method shown in FIGS. 9 to 18 described in detail above, the three-way connection controller shown in FIG. The operation of one embodiment of 103 was understood.

  The configuration and operation of the four-way connection controller 705 and the like shown in FIG. 7 are not described in detail here, but can be easily understood from the configuration and operation of the above-described three-way connection controller.

  In the description of FIG. 4 and subsequent figures, the processor bus 111, the memory bus 112, and the system bus 113 are all address / data separated buses, but the present invention is also applicable to an address / data multiplexed bus. Needless to say, you can. For example, when the processor bus 111 and the system bus 113 are address / data multiplexed buses, one processor address bus 411 and one processor data bus 413, and one system address bus 417 and one system data bus 419 in FIG. And is connected to both the bus / memory connection controller 401 and the data path switch 402. In addition, it goes without saying that various modifications can be made under the basic concept of the present invention regardless of the above-described embodiments.

1 is a schematic configuration diagram showing a first embodiment of a bus system of the present invention. The schematic block diagram of the bus system of a prior art. The other schematic block diagram of the bus system of a prior art. The schematic block diagram which shows one Example of the three-way connection controller 103 in 1st Example of this invention. The block diagram which shows one Example of the data path switch 402 in one Example of the three-way connection controller 103 in 1st Example of this invention. The block diagram which shows one Example of the bus memory connection controller 401 in one Example of the three-way connection controller 103 in 1st Example of this invention. The schematic block diagram which shows the 2nd Example of the bus system of this invention. The schematic block diagram which shows the 3rd Example of the bus system of this invention. FIG. 6 is a diagram showing a correspondence between a data path control signal 420 decoded by a decoder 510 in the data path switch 402 of the present invention shown in FIG. 5 and a decoding result thereof. The figure which shows the relationship between the data path control signal 420 in each step of the state transition in the case of the processor main memory read in the Example of this invention, and various signals. The figure which shows the relationship between the data path control signal 420 in each step of the state transition in the case of the processor main memory write in the Example of this invention, and various signals. The figure which shows the relationship between the data path control signal 420 in each step of the state transition in the case of processor system bus device read in the Example of this invention, and various signals. The figure which shows the relationship between the data path control signal 420 in each step of the state transition in the case of the processor system bus device write in the Example of this invention, and various signals. The figure which shows the relationship between the data path control signal 420 in each step of the state transition in the case of the DMA read in the Example of this invention, and various signals. The figure which shows the relationship between the data path control signal 420 in each step of the state transition in the case of the DMA write in the Example of this invention, and various signals. FIG. 7 is a transition diagram showing an example of state transition of the sequencer 601 in the bus / memory connection controller 401 shown in FIG. 6. The time chart figure which shows an example of the data transfer prescribed | regulated by FIGS. 9-16. FIG. 17 is another time chart showing an example of data transfer defined by FIGS. 9 to 16. The block diagram which showed concretely the connection of the three-way connection controller 103 in FIG. 4 which showed the signal which appears in FIG. 17, FIG. 18, and each bus | bath 111,112,113.

Explanation of symbols

101 ... N processors,
102: Cache memory system,
103 ... three-way connection controller,
104 ... main memory,
105 ... M system bus connection devices,
111 ... Processor bus,
112 ... Memory bus,
113: System bus.

Claims (5)

A processor bus;
A processor connected to the processor bus;
A memory bus,
A memory unit connected to the memory bus;
The system bus,
A device connected to the system bus;
A data transfer method in an information processing system having a data transfer unit having at least one circuit connected to the processor bus, the memory bus, and the system bus,
The data transfer unit operates the processor bus and the memory bus among the processor bus, the memory bus, and the system bus in an interlocking manner, and bidirectionally transmits the first data between the processor and the memory. A first data transfer mode to transfer to
The data transfer unit operates the memory bus and the system bus in an interlocking manner among the processor bus, the memory bus, and the system bus, and transmits both second data between the main memory and the device. A second data transfer mode ,
The data transfer unit operates the system bus and the processor bus among the processor bus, the memory bus, and the system bus in an interlocking manner to bidirectionally transfer third data between the device and the processor. And a third data transfer mode for transferring to the data transfer method.   The data transfer method according to claim 1, wherein any one or more of the processor bus, the memory bus, and the system bus is a multiplex bus.   The data transfer method according to claim 1, wherein the device is a file controller.   The data transfer method according to claim 1, wherein the device is a display controller.   The data transfer method according to claim 1, wherein the device is a network controller.

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