JP2003248653A - Device access circuit and device access method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device access circuit and a device access method that can improve data transfer efficiency in a total system. <P>SOLUTION: For read access, after a master device confirms that a slave device is in an accessible state, the device access circuit holds access information issued by the master device, reads data from the slave device according to the access information, and after the data reading, transfers the read data to the master device. For write access, after a master device confirms that a slave device is in an accessible state, the device access circuit holds access information issued by the master device and writes data into the slave device according to the access information. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device access circuit and a device access method for improving the data transfer efficiency of a system.

[0002]

2. Description of the Related Art In recent years, in order to make a system high-speed and low-priced in accordance with improvement of CPU performance and access speed of memory, one memory bus is provided with CPU and DMA.
There is a tendency for multiple bus masters to be installed.

FIG. 7 is a block diagram of a memory bus in the prior art. A CPU 10, a DMA 12, and a DMA 13 that are bus masters and a memory 11 that is a bus slave are connected to the memory bus 100. The bus arbiter 200 arbitrates the memory bus 100, the device 16 is under the control of the DMA 12, and the device 17 is the DMA 13. Device 18 and device 19 operate under the control of the device access circuit 14.

The operation of the conventional memory bus thus configured will be described.

In FIG. 7, a DMA 12 performs a DMA transfer between a device 16 on the local bus 1 and a memory 11, and a DMA 13 a device 1 on the local bus 2.
7 and the memory 11 are DMA-transferred. Also, C
The PU 10 accesses the device 18 on the local bus 3 via the device access circuit 14. At this time, in the memory bus 100, access from each master is executed while the bus arbiter 200 arbitrates the memory bus 100.

FIG. 6 shows a time chart at the time of contention for a memory bus in the prior art. Note that the priority of the memory bus 100 is CPU 10, DMA 12, DMA
The order is 13. When the CPU 10 accesses the device 18, the CPU 10 generates the bus request signal CPU_REQ signal via the device access circuit 14, and at the end of the access, receives the CPU_ACK signal to complete the access cycle. Similarly, DMA1
Data transfer is performed while communicating with the bus request signal DMA_REQ and the acknowledge signal DMA_ACK for No. 2 and the bus request signal DMA_REQ and the acknowledge signal DMA_ACK for the DMA13.

[0007]

However, in the above memory configuration, if the device 18 accessed by the CPU 10 is a slow access device, the CPU
Until the access is completed, the memory bus 100 remains occupied and cannot be used by another master.

The present invention solves the above-mentioned conventional problems. Even when the CPU accesses a slow device, the device access circuit and device access method can improve the data transfer efficiency of the entire system without occupying the memory bus. Is intended to provide.

[0009]

In order to solve the above problems, the present invention provides a method of accessing a slave device via a device access circuit when the master device accesses the slave device. After confirming that access to the device is permitted, the device access circuit holds the access information issued by the master device, performs a data read operation to the slave device based on the access information, and transmits the data to the master device after the data read is completed. Read data transfer is performed, and at the time of write access, after confirming that the master device is in an access permission state to the slave device, the device access circuit holds the access information issued by the master device and the slave based on the access information. The method of performing a data write operation to device and characterized. By taking the above method, C
The memory bus is no longer occupied in the PU access operation, and the opportunity for other masters to use the memory bus increases,
The data transfer efficiency of the entire system can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is configured such that when a master device makes a read access to a slave device, the slave device is accessed via a device access circuit. Access information holding means for holding access information necessary for device read access, access state notifying means for notifying the master device of execution or termination of read access to the slave device, and access held by the access information holding means A data acquisition unit that acquires and holds read data from the slave device based on the information, and a data acquisition unit when the master device detects that the read data acquisition is completed by the access state notification unit and requests read access again. Master retained data The present invention is characterized by having a read data transfer means for transferring data to a device. With this configuration, the memory bus is not occupied in the read access operation of the CPU, and other master devices can increase the chances of using the memory bus. it can.

According to a second aspect of the present invention, when the master device makes a write access to the slave device, the slave device is accessed via the device access circuit, and the device access circuit requires the master device for the write access of the slave device. Access information holding means for holding different access information, an access state notifying means for notifying the master device of execution or termination of write access to the slave device, and a slave device based on the access information held in the access information holding means. The present invention is characterized by having a data write means for writing write data. With this configuration, the memory bus is not occupied in the write access operation of the CPU, and other master devices can increase the chances of using the memory bus. .

The invention according to claim 3 is characterized in that the device access circuit according to claim 1 or 2 is configured so that the master device can directly access the slave device. With this configuration, when a device capable of high-speed access is connected to the local bus, it becomes possible to directly access the device.

According to a fourth aspect of the present invention, when the master device accesses the slave device through the device access circuit, the master device is in the access permission state to the slave device during the read access. After confirming that, the device access circuit holds the access information issued by the master device, performs the data read operation to the slave device based on the access information, and transfers the read data to the master device after the data read is completed. A device characterized in that the device access circuit holds the access information issued by the master device and performs a data write operation to the slave device based on the access information after confirming that access to the slave device is permitted. Which is the access method. By performing the access method using the configuration of the device access circuit according to the first and second aspects, the bus is not occupied at the time of CPU access.

Further, the invention according to claim 5 is characterized by having a device access method and means for switching a mode for directly accessing a device, and a case where a device capable of high-speed access is connected. It enables control switching when a low-speed device is connected.

(Embodiment 1) An embodiment of the present invention will be described below.

FIG. 1 is a memory bus configuration diagram in one embodiment of the present invention, FIG. 2 is a device control circuit configuration diagram in one embodiment of the present invention, and FIG. 3 is a CPU write access in one embodiment of the present invention. 4 is a flowchart of CPU read access according to the embodiment of the present invention, and FIG. 5 is a time chart at the time of contention for the memory bus according to the embodiment of the present invention. The following description will be given with reference to these drawings. Here, the same numbers are attached to the same configurations as those of the related art, and the description is omitted.

In FIG. 1, the device access circuit 14
Reference numeral 15 is a buffer control circuit. When the CPU 10 accesses a device on the local bus 3, the access information is temporarily latched in the buffer control circuit 15 and accessed. As shown in FIG. 2, the device access circuit 14 includes a buffer control circuit 15 and an access control circuit 27, and the inside of the buffer control circuit 15 is a control signal latch circuit 21 for latching a control signal.
It is composed of a write data buffer 22, a latch control circuit 23, a read data buffer 24, a data selector 25, and a mode switching circuit 26.

At reset, the READY flag in the device access circuit 14 is in the ready state "1". When the CPU 10 makes a write access to the device 18, it first confirms that the READY flag is in the ready state "1" and then makes an actual write access.

At the time of write access, the buffer control circuit 15
Inside the CPU, the control signal latch circuit 21
The chip select signal, the address signal, and the read / write signal from 10 are latched, the write data is latched in the write data buffer 22, and the CPU access on the memory bus 100 is completed. At this time, the device access circuit 1
Reference numeral 4 sets the READY flag to a busy state of "0" at the time of latching the control signal so that the next CPU access is not accepted. On the other hand, on the local bus 3, a chip select signal, an address signal, a read / write signal, and write data are output to the device 18 on the local bus 3 to start write access. After the write access is completed, the READY flag is set to the ready state of "1" to notify that the next access is possible and the processing is completed.

FIG. 3 shows a flowchart at the time of software write access. Step 1 and step 2
Then, the READY flag is polled to confirm that the ready state is "1", and the write access of step 3 is performed.

Next, regarding the read access, in the case of the read access, the CPU 10 performs the read access after confirming that the READY flag is in the ready state "1" before performing the read access to the device 18. . At the time of read access, the chip select signal, the address signal, and the read / write signal from the CPU 10 are latched, the READY flag is set to the busy state of “0”, the CPU access on the memory bus 100 is terminated, and the device access circuit 14 makes a local bus. Read access is made to the device 18 on the No. At the end of the read access to the local bus 3, the device access circuit 14 holds the read data in the read data buffer 24, and the READY
The flag is set to the “1” ready state to notify the CPU 10 that the read data exists in the read data buffer 24. When confirming that the read data exists in the read data buffer 24, the CPU 10 makes a read access to the read data buffer 24 and acquires the read data.

FIG. 4 shows a flowchart at the time of software read access. Step 1 and Step 2
Then, if the previous access was a write access, it is confirmed that the READY flag is in a ready state so that the sequence is not broken. In step 3, the interrupt is masked with respect to the CPU interrupt so that an access to another local bus may occur due to the interrupt during the read access so that the access sequence is not broken. In step 4, read access is performed to the device 18 of the local bus 3, and in steps 5 and 6, after confirming that the read access is completed, in step 7, the read data of the read data buffer 24 is read from the read port. If the CPU's mask is released in step 8 and continuous reading is performed in step 9, the process returns to step 3, otherwise the read sequence ends.

The read access is executed as described above.

Referring to FIG. 5, a memory bus 10 using the present invention.
The time chart when the three bus masters of the CPU 10, the DMA 12, and the DMA 13 above 0 compete with each other is shown. Compared with the competition between the conventional techniques of FIG. 5 and FIG. 6, since the access cycle of the CPU 10 is shorter in FIG. 5, the DMA 12 and the DMA 13 can use the memory bus, and the data transfer efficiency is improved as a whole system. There is.

Next, the mode switching circuit 26 existing inside the device access circuit 14 will be described. The mode switching circuit 26 is a switching circuit for switching between a mode for performing a sequence for accessing by looking at the flag as described above and a mode for directly accessing the device. When reset is released, the device is in the mode to directly access the device.
When a device capable of high-speed access is connected to the local bus 3, direct access is performed. When a device having a low access speed is connected, the flag is checked to switch to the mode for access. As described above, it is possible to set the memory bus efficiency to be optimal for both a device that can be accessed at high speed and a device that has a slow access speed.

[0026]

As described above, according to the present invention, the CPU does not occupy the memory bus even when the CPU accesses a slow device in the configuration in which the memory bus has a plurality of bus masters. The master can also use the memory bus, and the data transfer efficiency of the entire system can be improved.

Further, by having a switching function between a mode for direct access and a mode for accessing by looking at a flag, the efficiency of the memory bus is optimal for both a device capable of high speed access and a device having a slow access speed. Can be set to.

[Brief description of drawings]

FIG. 1 is a memory bus configuration diagram according to an embodiment of the present invention.

FIG. 2 is a block diagram of a device control circuit according to an embodiment of the present invention.

FIG. 3 is a flowchart of CPU write access according to the embodiment of the present invention.

FIG. 4 is a flowchart of CPU read access according to the embodiment of the present invention.

FIG. 5 is a time chart at the time of contention for memory buses according to the embodiment of the present invention.

FIG. 6 is a time chart when a memory bus conflicts in the conventional technique.

FIG. 7 is a memory bus configuration diagram in a conventional technique.

[Explanation of symbols] 10 CPU 11 memory 12 DMA 13 DMA 14 Device access circuit 15 Buffer control circuit 16 devices 17 devices 18 devices 19 devices 21 Control signal latch circuit 22 Write data buffer 23 Latch control circuit 24 read data buffer 25 data selector 26 mode switching circuit 27 Access control circuit

Claims (5)

[Claims] 1. When a master device makes a read access to a slave device, the master device is accessed via a device access circuit, and the device access circuit holds access information necessary for the master device to make a read access to the slave device. Access information holding means, an access state notifying means for notifying the master device of execution or termination of read access to the slave device, and reading from the slave device based on the access information held in the access information holding means Data acquiring means for acquiring and retaining data, and data retained by the data acquiring means when the master device detects that the read data acquisition is completed by the access state notifying means and requests read access again. The above Device access circuit, characterized in that it comprises a read data transfer means for transferring the data device. 2. When the master device performs write access to a slave device, the master device is configured to access via a device access circuit, and the device access circuit holds access information necessary for the master device to perform write access to the slave device. Access information holding means, an access state notifying means for notifying the master device of execution or termination of write access to the slave device, and writing to the slave device based on the access information held in the access information holding means A device access circuit comprising: a data writing unit for writing data. 3. The device access circuit according to claim 1 or 2, wherein the master device can directly access the slave device. 4. A method of accessing via a device access circuit when a master device accesses a slave device, wherein the device is checked after confirming that the master device is permitted to access the slave device at the time of read access. The access circuit holds the access information issued by the master device, performs a data read operation to the slave device based on the access information, and performs read data transfer to the master device after the data read is completed. The device access circuit performs holding of the access information issued by the master device and a data write operation to the slave device based on the access information after confirming that the device is in an access permitted state. Device access method. 5. The device access method according to claim 4, wherein the device access method has means for switching a mode for directly accessing the device.