JP3206656B2 - Prefetch device and prefetch method on bus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a prefetch protocol in which in a bus arbitration in a computer system, a prefetch request is preferentially arbitrated by a bus use request for a read cycle and a write cycle.

[0002]

2. Description of the Related Art A bus protocol to which the present invention relates is used for improving the bus use efficiency particularly in a computer system in a system bus configuration in which a bus arbiter intensively performs bus use arbitration work.

Generally, in such a bus protocol, a write cycle and a read cycle (the two cycles are collectively referred to as a normal cycle hereinafter).
The bus arbitration work is handled without distinction, and when a read cycle occurs, if the access speed of the memory device at the storage destination of the read data is slow and the preparation of the read data is delayed, the read cycle Latency from start to read data acquisition (Latenc
(y: delay time) was delayed by that much, and the bus use efficiency was also reduced. However, with the recent increase in the speed of the system bus in a computer device, there has been a demand for a reduction in latency until read data acquisition and an improvement in bus use efficiency. It had been.

FIG. 14 is a timing chart showing the operation of a conventional request retry cycle.

In order to respond to the above request, in the timing chart shown in FIG. 14, a target device (not shown) that has received a read command issues a retry request to a master device (not shown) that has issued the read command. Conventionally, a technique has been taken in which the master device ends the cycle to prevent useless occupation of the bus.

In FIG. 14, a master device outputs an address to be read and a read command to an address / data line 101 and a command line 102, respectively, and simultaneously outputs a High level to a bus occupation signal 104 to use the bus. Is notified to other devices. The target device is the address of the address / data line 101 and the command line 1
Decode the 02 read command, recognize that it is a read for its own internal address, and start fetching data from the memory. The High level is output to the retry request signal line 103 on the bus, and a cycle end and a retry request are made to the master device. The master detects that the retry request signal line is at the high level, returns the bus occupation signal line 104 to the low level, and occupies the cycle. As a result, the bus occupation period is two clocks.

[0007]

When the conventional method using a retry request as described above is used, the master device does not know the time required for the fetch of the device from which data is to be read. However, there is a problem that a read cycle occurs due to the retry, and the bus is wasted.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the related art, and has a prefetch request cycle provided in a read cycle protocol.
Accordingly, in the bus use right acquisition arbitration, the above bus use request signal for the prefetch request cycle is prioritized over the bus use request signal for the normal cycle,
It is still another object of the present invention to provide a prefetch protocol that does not accept a bus use request of a master device that has issued a prefetch request during a fetch period of a target device, and a bus arbitration method thereof.

[0009]

According to the present invention, there is provided a prefetch having a bus arbiter for arbitrating a bus use request input from a plurality of devices connected via a system bus. A bus arbiter that receives a bus use request from a plurality of devices assigned priority and a prefetch request for reading data from a plurality of devices in advance, and receives a bus use request and a priority assigned to the prefetch request. It is characterized in that it recognizes in advance the order and the time required for fetching a plurality of devices, preferentially permits a prefetch request based on the time required for the fetch, and does not accept a bus use request from the device that issued the prefetch request. And

The bus arbiter includes a prefetch request cycle arbiter for arbitrating prefetch requests from a plurality of devices connected to the system bus, and a prefetch request cycle arbiter for arbitrating prefetch requests from devices that have issued the prefetch request. A request mask unit that masks a bus use request, a normal cycle arbiter that arbitrates the bus use request output from the request mask unit, a multiplexer that multiplexes the outputs of the prefetch request cycle arbiter and the normal cycle arbiter, and a multiplexer output. A bus use permission signal output unit that generates a signal for giving a bus use permission to the device that has issued the bus use request.

The multiplexer multiplexes the prefetch request output from the prefetch request cycle arbiter preferentially over the bus use request output from the normal cycle arbiter, and outputs a bus use permission signal to the device that has output the prefetch request. It is characterized by doing.

The request mask unit includes: a plurality of mask fetch period registers storing the number of clocks required for fetching a plurality of devices; a clock stored in one of the plurality of mask fetch period registers; A compare timer that compares one of the signals and outputs a signal when they match, and starts counting, a signal obtained by performing a logical sum of fetch start signals from a plurality of devices, and a signal output from a bus use permission signal output unit An AND gate circuit that takes the logical product of the bus use permission signals
Set when the signal from the AND gate circuit is input,
A flip-flop that is reset when a signal from the compare timer is input.

The flop is set when a signal is input from a compare timer, and is reset when a prefetch request and a bus use request are simultaneously output.

Further, a decoder for decoding a signal from the two devices is provided between the prefetch request cycle arbiter and the request mask unit.

The decoder receives prefetch request signals and bus use request signals from a plurality of devices and generates a bus use permission request signal, a fetch start signal, and a bus use request signal from these signals. It is characterized by outputting.

Further, a prefetch request for reading data from a memory in advance is provided in a protocol of a read cycle connected to the system bus, and the prefetch request is processed with priority over a bus use request.

In the present invention configured as described above, the prefetch request cycle to be performed prior to the read cycle is defined in advance, and the prefetch request processing is performed based on the prefetch request cycle. The bus occupation period can be shortened compared with the means for improving the bus efficiency such as the retry which has been used for the device which requires the above.

Further, the prefetch request cycle is
Defined in the protocol and giving the bus use priority over the normal cycle, it is possible to reduce the latency until receiving the read data in the read cycle, and to execute the prefetch request cycle to make the bus available. Since the occupation time is shorter than the time for occupying the bus by the conventional retry cycle, the overall bus use efficiency can be improved.

Further, since the bus use permission request signal for the prefetch request cycle and the bus use permission request signal for the normal cycle are separated, different priorities can be set for each, and the fetch time is long. Regarding the device, the priority of the bus use permission request signal allocation in the prefetch request cycle can be set higher, regardless of the priority of the bus use permission signal allocation for the normal cycle. As a result, arbitration can be performed efficiently even when the bus use permission in the prefetch request cycle is activated simultaneously from a plurality of devices.

Further, in order to prevent a device that is prefetching in response to the prefetch request from performing a read cycle from a device that has requested prefetching before data is not ready, a request mask unit is provided in the bus arbiter. Is provided to temporarily remove the traffic from the arbitration target, so that unnecessary traffic increase can be prevented and the bus use efficiency can be improved.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration example of the first embodiment of the present invention.

As shown in FIG. 1, a computer device 1 of this embodiment has a host bridge 3, a memory controller 5, a USB (Universal Serial
Bus) interface 6, graphic controller 7, SCSI (Small Computer System Interface) interface 8, CPU 9 is connected to host bridge 3, and memory 10 is connected to memory controller 5. , 7, and 8, the arbitration work of the bus use requests output from one bus arbiter 4 is performed.

The bus arbiter 4 is a device that performs bus arbitration for arbitrating bus use requests from the devices 3, 5, 6, 7, and 8 constituting the computer device 1.
If this bus arbitration is not performed, when each device issues a bus use request simultaneously or almost at the same time, it becomes impossible to know which device should preferentially process the bus use request.

Therefore, considering the case where a bus use request is issued from a plurality of devices at the same time, each device 3, 5, 6, 7, 8
Are assigned priorities for receiving bus use requests. By doing so, if bus use requests are issued at the same time, processing is performed in order from the device with the highest priority, so that confusion does not occur.

In the above description, USB is an interface standard for connecting a personal computer and peripheral devices,
SI is an interface standard for connecting a personal computer or the like to a peripheral device such as a hard disk or a laser printer.

FIG. 2 is a block diagram showing a signal flow of the request / fetch signal 20 and the bus use permission signal 21 via the system bus 2 according to the first embodiment of the present invention.

Referring to FIG. 2, the host bridge 3, memory controller 5, graphic controller 7, and U
A request / fetch signal 20 is output from the SB interface 6 and the SCSI interface 8 and input to the bus arbiter 4. The bus arbiter 4 receives these request / fetch signals 20 and outputs a bus use permission signal 21 to each device that has output the request / fetch signal 20.

FIG. 3 is a table showing the signals input to and output from each device and the priorities.

Here, the request / fetch signal 20 is not a single signal, but as shown in FIG.
A bus request signal REQA-REQE for normal cycle requesting a normal cycle from 6, 7, 8 and a bus request signal FETCHR for prefetch request cycle requesting prefetch.
EQA to FETCHREQE and fetch start signals FETCHA to FETCHE
And consists of

However, the bus arbiter 4 outputs all the devices 3, 5, 6, 7, 8 that have output the request / fetch signal 20.
, The bus use permission is given according to the priority given in advance.
FIG. 3 shows the priority of each device. As shown in FIG. 3, the priority order is the host bridge 3, the memory controller 5,
The graphic controller 7, the USB interface 6, and the SCSI interface 8 are set in this order.
When each of these devices 3, 5, 6, 7, and 8 simultaneously outputs the request / fetch signal 20 to the bus arbiter 4, a bus use permission is given in accordance with the priority described above.

The same applies to the case where the request / fetch signal 20 is output from the host bridge 3, the graphic controller 7, the SCSI interface 8 and the like at the same time, but not simultaneously, in duplicate within the time determined by the machine cycle. The bus use permission is given according to the priority given.

More specifically, what if the request / fetch signal 20 is output not at the same time but at a time lag, in such a case, the devices 3, 5, 6, 7, 8
Depends on how much the output of the request / fetch signal 20 is shifted in time. If the bus use time between the devices does not overlap at all and is output in a different machine cycle, the request / fetch signal 20 is output regardless of the priority.
Are received in the order in which are output. In the case where they are somewhat overlapped in time and are output within the same machine cycle, the processing of the request that arrives next is executed after the execution of the processing that has arrived earlier ends in principle.

As described above, the bus arbiter 4 receives the bus use request or the prefetch request from each of the devices 3, 5, 6, 7, and 8, and assigns the priority assigned to each of the devices 3, 5, 6, 7, and 8. In order. When the bus use request and the prefetch request are issued at the same time, the prefetch request is arbitrated preferentially, and the bus use request processing is performed after the prefetch request processing is completed.

Before describing the operation of the present embodiment, the input / output device of each signal shown in FIG. 3 and its input / output timing will be briefly described here.

REQA to REQE are normal cycle bus use request signals input to the bus arbiter 4 from the devices 3, 5, 6, 7, and 8 during a normal cycle. FETCHREQA ~ FE
TCHEREQE is a bus use request signal for a prefetch request cycle input to the bus arbiter 4 at the time of a prefetch request. FETCHA to FETCHE are fetch start signals input to the bus arbiter 4 at the start of fetch. GNTA
.About.GNTE is a bus use permission signal output from the bus arbiter 4 to a device permitted to use the bus.

The output order of the signals 13 to 16 is as follows. First, a normal cycle bus use request signal REQA to REQE is output when a normal cycle occurs, and a prefetch request cycle signal is output when a prefetch request cycle occurs. The bus use request signals FETCHREQA to FETCHEREQE are output, followed by the fetch start signals FETCHA to FETCHE, and finally, the bus use permission signals GNTA to GNTE.

FIGS. 4A to 4C show, as an example, the host bridge 3 when the host bridge 3 shown in FIG.
The operation contents of the memory controller 5 and the bus arbiter 4 are shown on a time axis. When reading data, see FIG.
FIG. 4 shows the prefetch request cycle shown in FIG.
During the prefetch execution shown in (b), it consists of three phases of the read cycle shown in FIG. 4 (c).

Now, the operation will be described according to the passage of time.

In the prefetch request cycle, the host bridge 3 sends the bus arbiter 4 a bus use request signal FETCHREQA for the prefetch request cycle, for example.
14 is output. This signal is preferentially arbitrated, generating a prefetch request cycle, and the bus arbiter 4 masks the bus use request from the host bridge 3 while the memory controller 5 executes the fetch of data from the memory 10 accordingly, Not accepted.

During the prefetch, the memory controller 5 operates the memory 1 by the fetch start signal FETCHA15.
Prefetch data from 0.

In the read cycle, after completion of the prefetch, the bus use request is unmasked, a bus use request from the host bridge 3 is added, arbitration is performed, and a bus use permission signal GNTA 16 is output to the host bridge 3. As a result, the host bridge 3 reads data from the memory controller 5 and obtains read data.

As described above, the bus arbiter 4 preferentially permits execution of the prefetch request cycle prior to the read cycle. As described above, the latency until the device that has caused the read cycle acquires the read data is reduced, and the use efficiency of the entire bus is improved.

FIG. 5 is a diagram showing the internal configuration of the bus arbiter 4 shown in FIG. As shown in FIG. 5, the bus arbiter 4 includes devices 3, 5, connected to the system bus 2.
A prefetch request cycle arbiter for arbitrating the prefetch requests from 6, 7, 8 and a bus use request for a normal cycle from the device that issued the prefetch request during execution of the prefetch of the device that issued the prefetch. The request mask unit 30, a normal cycle arbiter 31 for arbitrating the normal cycle output from the request mask unit 30, a prefetch request cycle arbiter 28 and a normal cycle arbiter 31
And a bus use permission signal GNTA to GNTE2 for giving a bus use permission to a device which has issued a bus use request from the output of the multiplexer 33.
And a bus use permission signal output unit 32 for generating and outputting 9.

The request mask unit 30 includes a bus use request signal FETCHREQA-FET for a prefetch request cycle.
While the device that has output the CHREQE 26 generates a prefetch request cycle and executes fetching, the bus use request from the device that has output the prefetch request cycle bus use request signals FETCHREQA to FETCHREQE 26 is masked and is not accepted. This is to process the prefetch request preferentially and to prevent the system bus 2 from being confused due to the mixture of the prefetch request and the normal bus use request.

Normal cycle bus use request signals REQA-RE
The QE 27 and the bus use request signals FETCHREQA to FETCHEREQE 26 for the prefetch request cycle are input to the request mask unit 30 and the prefetch request cycle arbiter 28 in the bus arbiter 4, respectively. The request mask unit 30 uses the corresponding prefetch request cycle use request signals FETCHREQA to FETCHF during the fetch period.
The normal cycle bus use request signals REQA to REQE27 from the device that issued the ETCHREQE 26 are masked and do not participate in arbitration.

Normal cycle bus use request signals BUSREQA to BUSREQE2 output from request mask unit 30
4 and prefetch request cycle bus use request signals FETCHREQA to FETCHREQE2 from the respective devices 3, 5, 6, 7, and 8.
6 are prefetch request cycle arbiters 2
8 and the normal cycle arbiter 31, the output destination of the bus use permission signal is determined by each arbitration protocol, and the bus use permission signal output destination codes 22 and 2
3 is input to the multiplexer 33. The multiplexer 33 multiplexes the bus use permission signal output destination code 23 from the prefetch request cycle arbiter 28 preferentially, and outputs the bus use permission signal output destination code 29 to the bus use permission signal output unit 32. The bus use permission signal output unit 32 decodes the
The bus use permission signals GNTA to GNTE 21 are fed back to the request mask unit 30 and output to the devices 3, 5, 6, 7, and 8 connected to the system bus 2, and one of the bus use permission signals GNTA to GNTE 21 is output. Activating one allows the device to which it connects to use the bus.

Each of the above-mentioned signals is sent to the FETCHREQA to FETCHREQE6, FETCHA to FETCHE2
5, REQA to REQE27, GNTA to GNTE21, or the reverse.

FIG. 6 is a diagram showing the internal configuration of the request mask unit 30 in the bus arbiter 3.

The part which realizes the function of the bus arbiter 4 is the request mask unit 30.

As shown in FIG. 6, the request mask unit 30 is provided with each device 3, 5, 6, on the system bus 2.
A plurality of REQA-REQE mask fetch period registers 41 storing the number of clocks required for the fetches 7 and 8, the number of clocks stored in one of the plurality of REQA-REQE mask fetch registers 41, One of the fetch start signal signals FETCHA to FETCHE25 input from 5, 6, 7, and 8
Compare timer 4 that outputs match signal 46 and starts countdown when matched.
5 and a signal obtained by ANDing the fetch start signals FETCHA to FETCHE25 with the bus use permission signals GNTA to GNTE21 fed back from the bus use permission output unit 32, And a normal cycle bus use request signal REQA to REQE2 input from the RS flip-flop 34 and the devices 3, 5, 6, 7, and 8 which are reset by the signal input from the compare timer 45.
7 and an AND gate circuit 36 for generating bus use permission signals BUSREQA to BUSREQE 24.

In the request mask unit 30,
The start timing of the prefetch request and the execution period of the prefetch are determined in advance, and these are set by the values of the REQA-REQE mask fetish period register 41 incorporated in the request mask unit 30.
For example, the host bridge 3 operates the graphic controller 7 by using the REQA mask fetch period register 41.
Is set by the fetch period register 41 for the RECC mask.

However, the execution period of the prefetch is determined by the position and performance of the device on the system bus 2, and it is not always necessary to give a higher priority to the device having the longer prefetch period. Higher priority may be given from shorter ones.

Each device 3, 5, 6, on the system bus 2
The number of clocks required for the fetch of 7, 8 is
6, 7, and 8 are written in the fetch period registers 41 for the REQA-REQE masks. One of the values written in the REQA-REQE fetch period register 41 is the compare value of the compare timer 45. RS latch 34
Is a configuration in which five RS latches are arranged in parallel. A match signal 45 of the compare timer 44 is input to each set terminal (S), and each reset terminal (R)
Is a fetch start signal from each device 3,5,6,7,8
After ORing the FETCHA to FETCHE25 with the OR gate circuit 42, the AND gate circuit 38 uses the bus use permission signal GNTA
To GNTE 21 are input. This R
The output 35 of the S-latch 34 masks the normal cycle bus use request signals REQA to REQE17 from the devices 3, 5, 6, 7, and 8 by the AND gate 36, and outputs the normal cycle bus use request signals BUSREQA to BUSREQE 34 as the normal cycle. Output to the arbiter 31.

On the other hand, the normal cycle bus use request signals REQA-REQE17 and the request mask signal REQMASKA
When both signals .about.REQMASKE 35 are input, the output of the AND gate 36 becomes 1 (High level) for the first time.
This is an unmasked state.

The system configuration blocks 3, 5, 6, 7, 8, 9, and 10 other than the bus arbiter 4 in FIG. 1 are well known to those skilled in the art and are not directly related to the present invention. Detailed configuration is omitted.

FIG. 7 is a timing chart at the time of arbitration of a bus use request according to the first embodiment of the present invention.
FIG. 8B is a timing chart showing a prefetch request cycle, and FIG. 8B is a timing chart showing reading after the end of prefetch.

Hereinafter, the operation of this embodiment will be described with reference to FIGS.

As can be seen from FIG. 7, each of the devices 3, 5, 6, 7, and 8 connected to the system bus 2 generates a normal cycle bus use request signal REQA when generating a normal cycle.
~ REQE27 and a bus use request signal for a prefetch request cycle when a prefetch request cycle is to be generated.
Activate FETCHREQA to FETCHREQE26. On the other hand, the bus arbiter 4 activates the bus use permission signals GNTA to GNTE 21 for only one device.

In this embodiment, the bus use request signals FETCHREQA to FETCHREQE 28 for the prefetch request cycle have higher priority than the bus use request signals REQA to REQE 27 for the normal cycle. Now, as shown in FIG. 7, the host bridge 3 issues a bus use request signal FETCHREQA 28 for a prefetch request cycle.
Is activated (High level), and the memory controller 5 sends a bus use request signal for a prefetch request cycle.
The FETCHREQB 28 is activated, and the graphic controller 7, the USB interface 6, and the SCSI interface 8 transmit the normal cycle use bus request signals RECC, REQ, respectively.
When the D, REQE 27 is activated, the prefetch request cycle arbiter 28 outputs the device code of the host bridge 3 having the higher priority among the bus use request signals FETCHREQA and FETCHREQB 28 for the prefetch request cycle to the bus use permission signal output destination code 23. Multiplexer 33
Output to

On the other hand, the normal cycle arbiter 31 outputs a device code having a higher priority order among the normal cycle bus use request signals REQC, REQD, and REQE 27 which is not masked by the request mask unit 30 to a bus use permission signal output destination. The code 22 is output to the multiplexer 33. The multiplexer 33 preferentially outputs the bus use permission output signal 23 from the prefetch request cycle arbiter 28 to the bus use permission signal output unit 32. The bus use permission signal output unit 32 decodes this,
Bus use permission signal GNTA to each device 3, 5, 6, 7, 8
Bus use permission signal to host bridge 3 in GNTE 21
The GNTA 21 is activated (high level) as shown in FIG.

After receiving the bus use permission signal GNTA 21 in this way, the device which generates the prefetch request cycle outputs an address to be read and a command indicating the prefetch request to the system bus 2 and thereafter renews the same. A read cycle is generated using the address. Until the device to be read ends the prefetch, the read cycle by the master device may insignificantly increase the traffic, so that a bus use permission request from the master device is not accepted.

As shown in the timing chart of FIG. 8A, upon detecting that the bus use request permission signal GNTA 21 has become active, the host bridge 3 sends an address to be read out to the address / data line 88 to the command line 89. Output fetch command.

Each device 3, 6, 7, 8 on the system bus 2
Always monitors the output of these addresses and commands, and if this address falls within its own address range, reads out the data immediately from the above address in accordance with the prefetch request command on the command line 89, and Data is fetched in a register (not shown).

Now, the memory controller 5 decodes the above-described fetch command and address, activates the fetch start signal FETCHB90 at the next clock, and starts fetching. In the request mask unit 30 in the bus arbiter 4, the fetch start signal FETCHB90 becomes active,
The value of the REQA-REQE fetch period register 41 is selected as the compare value of the compare timer 45, and the compare timer 45 starts counting down at the same time. Since the fetish start signal FETCHB93 has become active, the signal 4 obtained by ORing the fetch start signals FETCHA to FETCHE25
4 becomes active (High level), and at this time, the bus use permission signal GNTA 89 also becomes active (High level), so that the request mask signals REQMASKA to REQM
Of the ASKE 35, only the request mask signal REQMASKA 35 of the host bridge 3 becomes active (Low level), and masks the normal cycle bus use request signal REQA 27. At this time, the bus use permission request signals BUSREQA to BUS
Of the REQE 24, the bus use permission request signal BUSREQA 39 for the host bridge 3 goes low.

Thereafter, the match signal 4 of the compare timer 45 is output.
When 6 becomes active (High level), the RS latches 34 are all set, and the mask is released when the request mask signal BUSREQA 37 of the host bridge 3 becomes High level.

On the other hand, the master device which has generated the above-described prefetch request cycle causes a read cycle again as shown in FIG. 8B, and stores the above-mentioned address on the address / data line 88 and the command line 89 on the command line. Output a read command to Upon confirming that this address matches the address in the above-described prefetch request cycle, the device that has received the prefetch request command outputs the read data fetched on the register to the address / data line 88.

As described above, according to the present embodiment, the number of clocks required for fetching the devices 3, 4, 5, 6, 7, and 8 connected to the system bus 2 is determined by the REQA in the bus arbiter 4.
The master device that has issued the prefetch request is excluded from the arbitration processing during the fetch period by the bus arbiter 4 notifying the bus arbiter 4 that the device that has performed the prefetch is stored in the fetch period register 41 for REQE mask. By doing so, it is possible to prevent a decrease in bus efficiency due to useless read cycles.

FIG. 9 is a block diagram showing the overall configuration of the second embodiment of the present invention.

As shown in FIG. 9, in the present embodiment, a decoder 70 is provided between the prefetch request cycle arbiter 28 in the bus arbiter 4 'and the request mask unit 71, and the fetch start signals FETCHA to FETCHE25 in FIG.
This is an example in which the input of is omitted. As the second embodiment of the present invention, the basic configuration is as described above, but the number of signal lines required on the system bus 2 is further reduced.

Since the other structure is the same as that of the first embodiment shown in FIG. 5, it is denoted by the same reference numerals as in FIG.

Prefetch request bus use request signals FETCHREQA to FETCHREQE 26 from the devices 3, 5, 6, 7, and 8
And the normal cycle bus use request signals FETCHA to FETCHE27 from the devices 3, 5, 6, 7, and 8 are all input to the decoder 70. The decoder 70 sends the bus use permission request signals FETCHREQA to FETCHREQE 72 to the prefetch request cycle arbiter 28 based on the combination of these two signals.
Fetch start signals FETCHA to FETCHE73 and a bus use request signal to the request mask unit 71.
BUSREQA to BUSREQE 74 are generated and output.

Each device 3, 5, 6, on the system bus 2
When the prefetch is started in response to the prefetch request cycle, the prefetch request bus use request signals FETCHREQA to FETCHREQE 26 and the normal cycle bus request are used instead of the fetch start signal 25 of the first embodiment. The signals FETCHA to FETCHE27 all become High level. The decoder 70 decodes this and sets the corresponding portion of the fetch start signal 73 to High level, thereby notifying the request mask unit 30 of the timing of the start of prefetch.

FIG. 10 is a diagram showing the internal configuration of the decoder 70. As shown in FIG. 10, the decoder includes fifteen AND gate circuits 71, five of which invert and input the normal cycle bus use request signals REQA to REQE27, and the other five. The bus use request signals FETCHREQA to FETCHREE 26 for the prefetch request cycle are inverted and input.

As described above, according to the present embodiment, the input of the fetch start signals FETCHA to FETCHE25 is reduced, and the fetch start signals are generated inside the bus arbiter 4 '.
It is possible to reduce the congestion of wiring on the motherboard using this system bus 2 and to reduce power consumption.

FIG. 11 is a block diagram showing the configuration of the third embodiment of the present embodiment. FIG. 12 is a block diagram showing the bus arbiter 4 '.
FIG. 3 is a diagram showing an internal configuration of the device. This embodiment is basically similar to FIG.
However, the priority change signal PCHANGE 35 for changing the priority of each of the devices 3, 5, 6, 7, and 8 is input to the request mask unit 30.

As shown in FIG. 11, in the present embodiment, the transaction amount (load situation) of each device 3, 5, 6, 7, 8
In this example, a transaction monitor signal TMONITOR 23 is input from each of the devices 3, 5, 6, 7, and 8. In the first embodiment,
Although the priority is given according to the length of the period required for the fetch of each of the devices 3, 5, 6, 7, and 8, the present embodiment does not limit the current transaction of the device regardless of the length of the fetch period. The priority is determined according to the quantity. Specifically, for example, when the processing amount of the image data increases, the highest priority is given to the graphic controller 7.

As described above, according to the present embodiment, the priority order can be dynamically changed according to the transaction amount of each of the devices 3, 5, 6, 7, and 8, and the use of the bus is permitted according to the load state of each part of the system. Since acquisition and sequential processing can be performed, not only efficiency of the bus but also efficiency of the entire system can be improved. In addition, a priority may be given according to the urgency or importance of the process, regardless of the amount of the transaction.

FIG. 13 is a timing chart of the prefetch request cycle of the first to third embodiments.

In FIG. 13, the master device sends an address to be read and a fetch command to an address / address, respectively.
Output to the data line 106 and the command line 107,
A high level is output to the bus occupancy signal 108 to notify other devices that the bus is being used, and the bus occupancy signal is returned to the low level at the next clock, and the cycle is completed. As described above, since the bus is occupied without waiting for a response from the target device, the bus occupation period becomes one clock (half of the conventional example) and the conventional retry cycle as compared with the conventional example shown in FIG. The bus occupation period is shorter than that of the prefetch execution.

It should be noted that the present invention is not limited to the combinations of the circuits and signals of the above-described embodiments, but may be combined in any manner as long as equivalent functions can be realized. A circuit configuration may be used.

[0082]

As described above, according to the present invention,
The following remarkable effects are obtained.

(1) By defining a prefetch request cycle to be performed prior to a read cycle, the bus occupation period is shorter than the means for improving the bus efficiency such as retry which has conventionally been used for a device requiring a long time for fetch. Can be shortened.

(2) The prefetch request cycle is
By defining in the protocol and giving the bus use permission with priority over the normal cycle, it is possible to reduce the latency until receiving the read data in the read cycle. Further, the time for occupying the bus by executing the prefetch request cycle is shorter than the time for occupying the bus by the conventional retry cycle, which leads to an improvement in the overall bus use efficiency.

(3) Since the bus use permission request signal for the prefetch request cycle and the bus use permission request signal for the normal cycle are separated, different priorities can be set for each, and the fetch time can be reduced. For a long device, the priority of allocating the bus use permission request signal in the prefetch request cycle can be set high irrespective of the priority of allocating the bus use permission signal for the normal cycle. As a result, arbitration can be performed efficiently even when the bus use permission in the prefetch request cycle is activated simultaneously by a plurality of devices.

(4) In order to prevent a device that is prefetching in response to a prefetch request from causing a read cycle from a device that has requested prefetching before data is not ready, a request mask unit is provided in the bus arbiter. Since it is provided and temporarily removed from the arbitration target, unnecessary traffic increase can be prevented, and the bus can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a signal flow of a request / fetch signal 20 and a bus use permission signal 21 via the system bus 2 according to the first embodiment of the present invention.

FIG. 3 is a table summarizing signals input to and output from each device and their priorities;

FIG. 4 is a diagram showing, on a time axis, the operation contents of the host bridge 3, the memory controller 5, and the bus arbiter 4 when the host bridge 3 shown in FIG. 3 reads data from the memory controller 5.

FIG. 5 is a diagram showing an internal configuration of a bus arbiter 3 shown in FIG.

FIG. 6 is a diagram showing an internal configuration of a request mask unit 30.

FIG. 7 is a timing chart at the time of arbitration of a bus use request according to the first embodiment of this invention.

FIG. 8 is a timing chart showing reading using a prefetch request cycle.

FIG. 9 is a block diagram showing an overall configuration of a second embodiment of the present invention.

FIG. 10 is a diagram showing an internal configuration of a decoder 70.

FIG. 11 is a block diagram showing a configuration of a third example of the present example.

FIG. 12 is a diagram showing an internal configuration of a bus arbiter 4 ″.

FIG. 13 is a timing chart of a request retry cycle according to a conventional example.

FIG. 14 is a timing chart showing a conventional request retry cycle operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Computer apparatus 2 System bus 3 Host bridge 4, 4 'bus arbiter 5 Memory controller 6 USB (Universal System Interface) interface 7 Graphic controller 8 SCSI (Small Computer System Interface)
Interface 9 CPU 10 Memory 28 Prefetch request cycle arbiter 30 Request mask unit 31 Normal cycle arbiter 32 Bus use permission signal output unit 33 Multiplexer 34 RS flip-flop 36, 38 AND gate circuit 41 REQA to REQE mask fetch period register 42 OR Gate circuit 45 Compare timer 70 Decoder

Claims (8)

(57) [Claims] 1. A system bus, a plurality of devices connected to the system bus, the system bus arbitration use between the respective devices performed
And the system is connected to any one of the devices.
In the prefetch unit and a bus arbiter to allow the use of Temubasu, each device, the data to other devices of the respective devices
Use of the system bus is required for prefetching.
Request and the prefetch request
In order to read the data with a low priority request
A bus use request for requesting use of the system bus;
Pre-notifying that the prefetch of the data has started
A fetch start notification can be sent to the bus arbiter
, And the said bus arbiter, of the data in the respective devices
The time required for prefetching is stored for each device.
Of the devices that have transmitted the prefetch request,
Permitted one of the devices to use the system bus
Then, the prefetch start notification is received from the other device.
From the time of transmission to the time required for prefetching of the other device
By the time the system bus has been granted
If the bus use request is received from the device that
A prefetch device that does not accept a bus use request . 2. The prefetch device according to claim 1, wherein the bus arbiter is a prefetch request cycle arbiter that arbitrates prefetch requests from the plurality of devices connected to the system bus, and a bus arbiter that outputs a prefetch request. A request mask unit that masks a bus use request from the device that issued the prefetch request during execution of the prefetch request; a normal cycle arbiter that arbitrates the bus use request output from the request mask unit; and the prefetch request cycle arbiter. A multiplexer for multiplexing the output of the normal cycle arbiter; and a bus use permission signal output unit for generating a signal for giving a bus use permission to a device which has issued a bus use request from the output of the multiplexer. Prefetch Location. 3. The prefetch device according to claim 2, wherein the multiplexer preferentially multiplexes a prefetch request output from the prefetch request cycle arbiter over a bus use request output from the normal cycle arbiter. A prefetch device that outputs a bus use permission signal to a device that has output a prefetch request. 4. The prefetch device according to claim 2, wherein the request mask unit includes a plurality of mask fetch period registers storing the number of clocks required for fetching the plurality of devices, and the plurality of mask fetches. Comparing the clock stored in one of the period registers with one of the fetch start signals,
A compare timer that outputs a signal when they match and starts counting, a signal obtained by performing a logical sum of fetch start signals from the plurality of devices, and a bus use permission signal output from the bus use permission signal output unit. A prefetch device, comprising: an AND gate circuit that takes a logical product; and a flip-flop that is set when a signal from the AND gate circuit is input and reset when a signal from the compare timer is input. 5. The prefetch device according to claim 4, wherein the flop flop is set when a signal is input from the compare timer and reset when a prefetch request and a bus use request are output simultaneously. A prefetch device characterized by the above-mentioned. 6. The prefetch device according to claim 2, wherein a decoder for decoding a signal from the two devices is provided between the prefetch request cycle arbiter and the request mask unit. 7. A pre-fetch apparatus according to claim 6, wherein the decoder inputs a prefetch request signal and the bus use request signals from the plurality of devices, the bus use permission request signal from these signals And a fetch start signal and a bus use request signal. 8. A method for prefetching data to a system bus, a plurality of devices connected to the system bus , and another of the devices.
Request to use the system bus to
Fetch request and priority lower than the prefetch request
Request to use the bus to read the data.
Request and the start of prefetching of the data.
And the start notification of the prefetch shown
Arbitrates use of the system bus between the devices
And the system is connected to any one of the devices.
A bus arbiter permitting use of the system bus, wherein the bus arbiter is configured to store the data in each of the devices.
Prefetch time is stored in advance for each device.
In addition, the bus arbiter has transmitted the prefetch request.
One of the devices is connected to the system bus.
After allowing use, the prefetch from the other device
From the other device's pre-
By the time the time required to switch
Received the bus use request from a device permitted to use
In such a case, a prefetch device that does not accept the bus use request .