JP7468112B2 - INTERFACE CIRCUIT AND METHOD FOR CONTROLLING INTERFACE CIRCUIT - Patent application - Google Patents

Description

The present invention relates to an interface circuit and a method for controlling an interface circuit.

A memory system has been disclosed in which multiple sets of interface circuits and memory chips are mounted in the same package, and the memory chips can be accessed by each interface circuit in response to multiple chip select signals from the outside (see, for example, Patent Document 1). In this type of memory system, the use of a serial interface memory chip prevents the increase in the area of the mounting board on which the memory chips and interface circuits are mounted.

Recently, serial interfaces such as SPI (Serial Peripheral Interface: registered trademark) have a serial mode in which data is transferred using one signal line, and a parallel mode in which data is transferred using multiple signal lines. A processor such as a CPU (Central Processing Unit) is connected to the serial memory via an interface circuit to enable access to serial memories of various interfaces. The interface circuit can control access to serial memories of various specifications by changing the setting value of a setting register.

Processors such as CPUs (Central Processing Units) that use this type of serial interface to read programs from serial memory usually start fetching programs in serial mode when powered on. For this reason, in order to increase the data transfer rate and improve the access efficiency of the serial memory, it is necessary to switch the operating mode of the serial memory from serial mode to parallel mode.

However, changing the operating mode while the CPU is fetching a program from the serial memory may result in malfunction. In order to prevent malfunction, for example, the program stored in the serial memory is transferred to another memory such as a RAM, and the operating mode of the serial memory is switched while the program in the other memory is being fetched. In this case, since the program is not fetched from the serial memory while it is being transferred to the RAM, etc., fetch efficiency decreases.

The present invention was made in consideration of the above problems, and aims to switch the operating mode of a serial memory while continuing to access the serial memory.

In order to solve the above technical problem, an interface circuit according to one aspect of the present invention is an interface circuit for controlling access to a serial memory that is switchable between a serial mode in which data is transferred using one signal line and a parallel mode in which data is transferred using a plurality of signal lines, the interface circuit including a first instruction holding unit that holds an instruction for accessing the serial memory output from a processor that executes a program held in the serial memory, a first interface unit for indirect access that outputs the instruction held in the first instruction holding unit, and a third interface unit for memory mapped access that converts a memory access request from the processor into an instruction acceptable to the serial memory and outputs the converted instruction. the serial memory, and an arbitration unit which outputs an instruction output by the first interface unit or the second interface unit to the serial memory and prohibits the output of the instruction received from the second interface unit when there is a conflict between receiving an instruction from the first interface unit and receiving an instruction from the second interface unit, the second interface unit having a second instruction holding unit which holds the converted instruction and a third instruction holding unit to which the converted instruction is transferred from the second instruction holding unit, and the first interface unit has a shift flag which is set when transferring the converted instruction from the second instruction holding unit to the third instruction holding unit in response to output of the instruction held in the first instruction holding unit.

It is possible to switch the operating mode of the serial memory while continuing to access the serial memory.

1 is a block diagram showing an example of a system in which an SPI controller according to a first embodiment of the present invention is installed. 2 is a timing diagram showing an example of a read operation in a single mode of the serial ROM of FIG. 1; 2 is a timing diagram showing an example of a read operation in QPI mode of the serial ROM of FIG. 1; 2 is a timing diagram showing an example of a read operation of the serial ROM of FIG. 1 in a XIP mode. FIG. 2 is a block diagram illustrating an example of the SPI controller of FIG. 1. 6 is an explanatory diagram showing an example of the setting contents of a register provided in the sequencer of FIG. 5 . 6 is an explanatory diagram showing an example of signals exchanged between the sequencer and the request arbitration circuit in FIG. 5; 6 is an explanatory diagram showing an example of signals exchanged between the request arbitration circuit and the protocol generation circuit of FIG. 5; 6 is a timing diagram showing an example of the operation of the protocol generating circuit of FIG. 5. 10 is an explanatory diagram showing an example of values set in each register in the timing diagram of FIG. 9 . 6 is a timing diagram illustrating an example of the operation of the request arbitration circuit of FIG. 5. 10 is a flow chart showing an example of an operation of the SPI controller of FIG. 1 switching the serial ROM from a single mode to a XIP mode. FIG. 13 is an explanatory diagram showing an example of setting a current control register for memory mapping when the flow of FIG. 12 is executed; 13 is an explanatory diagram showing an example of setting a memory-mapped next control register when the flow of FIG. 12 is executed; FIG. 13 is an explanatory diagram showing an example of setting a current control register for indirect when the flow of FIG. 12 is executed; FIG. 13 is an explanatory diagram showing an example of setting a next control register for indirect when the flow of FIG. 12 is executed. 6 is a timing diagram illustrating an example of the operation of the SPI controller of FIG. 5 for transitioning the serial ROM from single mode to XIP mode. FIG. 18 is a timing diagram showing a continuation of FIG. 17. FIG. 19 is a timing diagram showing a continuation of FIG. 18. FIG. 20 is a timing diagram showing a continuation of FIG. 19 . FIG. 11 is a block diagram showing an example of an SPI controller according to a second embodiment of the present invention. 22 is an explanatory diagram showing an example of the setting contents of a register provided in the sequencer of FIG. 21; FIG. 22 is a timing diagram showing an example of the operation of the SPI controller of FIG. 21 for transitioning the serial ROM from a single mode to an instruction omission mode. FIG. 24 is a timing diagram showing a continuation of FIG. 23. FIG. 25 is a timing diagram showing a continuation of FIG. 24.

The following describes the embodiments with reference to the drawings. Note that in each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted. Also, reference numerals indicating signals are used as reference numerals indicating terminals or signal lines.

First Embodiment
Fig. 1 is a block diagram showing an example of a system in which an SPI controller according to a first embodiment of the present invention is installed. Although not particularly limited, the system SYS shown in Fig. 1 is included in an image forming apparatus such as an MFP (Multifunction Printer) having a copy function, a facsimile function, a print function, a scanner function, etc.

The system SYS has a SoC (System on a Chip) 100 and a serial ROM 200 such as a serial flash memory. The SoC 100 has a CPU 300, a decoder 400, an SPI controller 500, a RAM (Random Access Memory) 600, an input/output interface unit 700, and a network interface unit 800. The serial ROM 200 is an example of a serial memory, the SPI controller 500 is an example of an interface circuit that controls access to the serial ROM 200, and the CPU 300 is an example of a processor.

The CPU 300 operates by fetching programs stored in the serial ROM 200, and controls operations within the SoC 100 and communication with external devices connected to the SoC 100. The CPU 300 outputs a clock signal CLK and a chip select signal /CS to the serial ROM 200, and inputs and outputs a 4-bit data signal IO (IO0-IO3) to the serial ROM 200. The data signal IO output from the CPU 300 to the serial ROM 200 may not only be a data signal, but may also be a command signal (instruction) or an address signal. How many bits of the 4-bit data signal IO are used depends on the operating mode.

The CPU 300 directly executes the program (instruction code and operands) read from the serial ROM 200 without loading the program stored in the serial ROM 200 into the RAM 600. To improve the efficiency of program fetching, for example, the CPU 300 may have a cache memory (not shown) that stores programs once fetched in reverse chronological order.

The decoder 400 identifies the device to be accessed by decoding the address included in the access request output from the CPU 300, and outputs a select signal to access the identified device. The device to be accessed is the serial ROM 200, the RAM 600, an input/output device connected to the input/output interface unit 700, or various devices connected to a network connected to the network interface unit 800.

The SPI controller 500 controls access to the serial ROM 200 based on an access request to the serial ROM 200 output from the CPU 300, and for example reads a program or data from the serial ROM 200. The SPI controller 500 can execute accesses called memory mapped accesses and indirect accesses.

In memory-mapped access, a read access request (read command) issued by the CPU 300 is automatically converted into the command system of the serial ROM 200 by the SPI controller 500. Then, data read from the serial ROM 200 is output directly to the CPU 300 from the SPI controller 500 without the CPU 300 executing the read command. Therefore, the CPU 300 can access the serial ROM 200 as a memory assigned on the memory map without being aware of the interface specifications of the serial ROM 200. For example, memory-mapped access is applied only to read access.

In indirect access, the SPI controller 500 performs write access or read access to the serial ROM 200 based on information written by the CPU 300 to a register in the SPI controller 500. For example, write access by indirect access is used to switch the operation mode of the serial ROM 200. An example of the internal configuration of the SPI controller 500 is described in FIG. 5.

RAM 600 is a so-called working RAM, and has the minimum storage capacity required for the operation of SoC 100. The input/output interface unit 700 inputs and outputs information between an input/output device (not shown) connected to the system SYS. An input device or an output device may be connected to the input/output interface unit 700. An input/output interface unit 700 may be provided for each device to be connected. The network interface unit 800 communicates with other devices via a network (not shown) connected to the system SYS.

The serial ROM 200 supports, for example, single mode, dual mode, quad mode, quad parallel instruction mode, and instruction omission mode as operation modes. In single mode, instructions and addresses are input to the data terminal IO0 (DI), and read data is output serially from the data terminal IO1 (DO). Single mode is an example of a serial mode in which data is transferred using one signal line (IO0 or IO1).

In dual mode, commands are input to data terminal IO0, addresses are input to data terminals IO0 and IO1, and read data is output in parallel from data terminals IO0 and IO1. In quad mode, commands are input to data terminal IO0, addresses are input to data terminals IO0 to IO3, and read data is output in parallel from data terminals IO0 to IO3.

In the quad parallel instruction mode, instructions and addresses are input to data terminals IO0 to IO3, and read data is output in parallel from data terminals IO0 to IO3. The instruction omission mode is an operating mode in which the input of instructions is omitted, and instructions input before entering the instruction omission mode are carried over. For example, in the instruction omission mode, addresses are input to data terminals IO0 to IO3, and read data is output in parallel from data terminals IO0 to IO3. The dual mode, quad mode, and instruction omission mode are examples of parallel modes that transfer data using multiple signal lines.

Switching from another operating mode to the quad-parallel instruction mode or the instruction omission mode is performed by inputting a switching command. In this case, the number of bits of the data terminal IO used to input the switching command depends on the current operating mode. In the following, the quad-parallel instruction mode is referred to as the QPI mode, and the instruction omission mode is referred to as the XIP mode.

Figure 2 is a timing diagram showing an example of a read operation in single mode of the serial ROM 200 of Figure 1. In Figure 2 and the following timing diagrams, shading indicates Don't Care. In single mode, while the chip select signal /CS is at a low level, the command INS and address AD are input to the serial ROM 200 in synchronization with the clock signal CLK, and read data RDT is output from the serial ROM 200. The command INS and address AD are input to the data terminal IO0, and the read data RDT is output from the data terminal IO1.

In FIG. 2, the command INS is 03h, but the command code is not limited to 03h. The "h" at the end of the command code indicates that the number preceding it is a hexadecimal number. The number of bits of the command INS, address AD, and read data RDT (8 bits, 24 bits, and 32 bits (4 bytes), respectively) may also be other than those shown in the figure. The same applies to the number of bits (bytes) shown in the subsequent timing diagrams. The upper limit of the frequency of the clock signal CLK in single mode is about 50 MHz. Since the frequency of the clock signal CLK is lower than in QPI mode and XIP mode, in single mode, it is not necessary to insert a dummy cycle DMY (FIG. 3) between the address AD and the read data RDT.

Figure 3 is a timing diagram showing an example of a read operation in QPI mode of the serial ROM 200 of Figure 1. The input of the chip select signal /CS and the clock signal CLK is the same as in Figure 2. In QPI mode, 4-bit data terminals IO0 to IO3 are used. An 8-bit command INS is input to the serial ROM 200 in two clock cycles, and a 24-bit address AD is input to the serial ROM 200 in six clock cycles.

After the address AD is input, an 8-bit mode MD is input to the serial ROM 200 in two clock cycles, a dummy cycle DMY is inserted for four clock cycles, and then four bytes of read data RDT are output in eight clock cycles.

Note that unlike the single mode, the QPI mode uses 4-bit data terminals IO0 to IO3 to supply commands to the serial ROM 200. For this reason, in order to use the QPI mode, the serial ROM 200 must be entered into the QPI mode beforehand. Entering the QPI mode is executed by setting the command code (EBh) of the Fast Read Quad I/O (Enter XIP mode) shown in FIG. 19 (described later) to 38h.

In FIG. 3, the command INS EBh indicates the entry of XIP mode, and depending on the input value of mode MD, it is determined whether or not the input of command INS is omitted in the next assertion cycle of the chip select signal /CS. By inserting a dummy cycle DMY, the read operation inside the serial ROM 200 can be hidden by the dummy cycle DMY. As a result, the upper limit of the frequency of the clock signal CLK in QPI mode is about 133 MHz, which is higher than in single mode.

Figure 4 is a timing diagram showing an example of a read operation in XIP mode of the serial ROM 200 of Figure 1. For example, the read operation in XIP mode shown in Figure 4 is executed when the mode MD indicates the omission of the command INS in the read operation in QPI mode of Figure 3.

A read operation in XIP mode is similar to QPI mode, except that the INS command is omitted from a read operation in QPI mode. For example, in XIP mode, if mode MD indicates the omission of the INS command input, a XIP mode read operation is also executed at the next assert cycle of the chip select signal /CS. On the other hand, in XIP mode, if mode MD indicates the input of the INS command, a QPI mode read operation including the input of the INS command is executed at the next assert cycle of the chip select signal /CS.

Figure 5 is a block diagram showing an example of the SPI controller 500 of Figure 1. The SPI controller 500 has a CPU interface circuit 510, a sequencer 520, a request arbitration circuit 530, and a protocol generation circuit 540. The CPU interface circuit 510 is connected to the CPU 300 of Figure 1 via a CPU bus.

The CPU interface circuit 510 outputs the reset signal reset_n received from the CPU 300 via the CPU bus to the sequencer 520. The sequencer 520 is reset during the low level period of the reset signal reset_n, and is released from the reset state when the reset signal reset_n changes to high level, and starts operating.

The sequencer 520 has a control register group 522 for memory-mapped access, a control register group 525 for indirect access, and a common control register 528 that is common to memory-mapped access and indirect access. The control register group 522 has a control register 523 used in Phase 0 to Phase 5, which will be described later, and a data buffer 524. The control register group 525 has a control register 526 used in Phase 0 to Phase 5, which will be described later, and a data buffer 527.

The control register 523 has a current register that holds an instruction to be output to the request arbitration circuit 530, and a next register that holds an instruction to be transferred to the current register. The control register 526 has a current register that holds an instruction to be output to the request arbitration circuit 530, and a next register that holds an instruction to be transferred to the current register. In the control register 523, the current register is an example of a third instruction holding section, and the next register is an example of a second instruction holding section. In the control register 526, the current register is an example of a first instruction holding section. The specifications of the control register groups 522, 525 and the common control register 528 are shown in FIG. 6.

Of the sequencer 520, the control register group 525 and an element that uses the control register group 525 to control access to the serial ROM 200 are an example of a first interface unit. Of the sequencer 520, the control register group 522 and an element that uses the control register group 522 to control access to the serial ROM 200 are an example of a second interface unit.

The sequencer 520 outputs commands INS, etc. to the serial ROM 200 based on an access request for the serial ROM 200 received from the CPU 300 via the CPU interface circuit 510, and receives read data RDT, etc. from the serial ROM 200.

The request arbitration circuit 530 arbitrates between the memory-mapped access request and the indirect access request output from the sequencer 520, and outputs the request selected by arbitration to the protocol generation circuit 540. When the request arbitration circuit 530 receives an indirect access request, it masks the acceptance of the memory-mapped access request and outputs the indirect access request to the protocol generation circuit 540. In other words, the request arbitration circuit 530 selects the indirect access request in priority over the memory-mapped access request. The request arbitration circuit 530 is an example of an arbitration unit.

The protocol generation circuit 540 is connected to the serial ROM 200 in FIG. 1. The protocol generation circuit 540 generates a signal according to the interface specifications of the serial ROM 200 based on the memory mapped access request or indirect access request received from the request arbitration circuit 530, and outputs the generated signal to the serial ROM 200. Then, based on the access request issued by the CPU 300, the serial ROM 200 is accessed under the control of the sequencer 520.

Figure 6 is an explanatory diagram showing an example of the settings of registers provided in sequencer 520 of Figure 5. A request issuing register is provided in each of control register group 522 for memory mapped access and control register group 525 for indirect access. When the request issuing register is set to "1", sequencer 520 issues an access request to request arbitration circuit 530 according to the settings of control register 523 (or 526). After issuing the access request to request arbitration circuit 530, sequencer 520 returns the request issuing register to "0".

In addition, in memory-mapped access, the sequencer 520 sets information for accessing the serial ROM 200 in the control register 523 according to the information included in the access request from the CPU 300, and then sets the request issuing register of the control register group 522 to "1". In indirect access, the request issuing register of the control register group 525 is set to "1" by the program executed by the CPU 300. The request issuing register is an example of a request issuing flag.

The shift enable register (memory mapped) included in the control register group 522 is set by the CPU 300. When the shift enable register (memory mapped) is "1", the sequencer 520 copies the contents of the next register of the memory mapped control register 523 to the current register in response to the execution of an indirect access. The shift enable register (memory mapped) is an example of a shift flag that is set when an instruction is transferred from the next register of the control register 523 to the current register in response to the output of an instruction from the current register of the control register 526.

The shift enable register (indirect) included in the control register group 525 is set by the CPU 300. When the shift enable register (indirect) is "1", the sequencer 520 copies the contents of the next register of the indirect control register 526 to the current register in response to the execution of an indirect access.

The data buffer 524 included in the group of control registers 522 for memory-mapped access is used to temporarily store read data read from the serial ROM 200. The sequencer 520 outputs the read data stored in the data buffer 524 to the CPU 300 in accordance with the data bus width of the CPU 300 without receiving a read request from the CPU 300.

The data buffer 527 included in the group of control registers 525 for indirect access is used to store read data read from the serial ROM 200. The sequencer 520 retrieves the read data stored in the data buffer 527 in response to a read request (load command) from the CPU 300, and outputs the retrieved read data to the CPU 300. In other words, the read data held in the group of control registers 525 for indirect access needs to be explicitly read by the CPU 300.

The CLKL width register is set to, for example, how many clocks of the system clock used by SoC100 the low level period of the clock signal CLK supplied to serial ROM200 should be. The CLKH width register is set to, for example, how many clocks of the system clock the high level period of the clock signal CLK should be.

The configurations of the control registers 523, 526 for each PhaseN (N=0 to 4) of the control register groups 522, 525 are the same. In addition, the configurations of the current and next registers of each control register 523, 526 are the same.

When the Phase validity register is "1", it indicates that the corresponding Phase is valid, and when it is "0", it indicates that the corresponding Phase is invalid. When the IO direction register is "1", it indicates that the data signal IO is output to the serial ROM 200, and when it is "0", it indicates that the data signal IO is input from the serial ROM 200. Note that in the phase of the dummy cycle DMY shown in Figures 3 and 4, the Phase validity register is set to "2", which is neither input nor output.

The IO number register is set to a number "1" less than the number of valid data terminal IOs. When the IO number register is "0", 1 bit is valid, when it is "1", 2 bits are valid, and when it is "3", 4 bits are valid.

The CLK number register is set to a number that is "1" less than the number of clock cycles of the clock signal CLK used in that phase. For example, a phase with a CLK number register of "7" indicates that 8 clock cycles are used, and a phase with a CLK number register of "23" indicates that 24 clock cycles are used.

When the output data selection register is "0", it indicates that the data held in the data register is to be output to the data terminal IO, and when it is "1", it indicates that the data included in the access request from the CPU 300 is to be output to the data terminal IO. When the output data selection register is "0", the data register is enabled and the data held in the data register is output.

Figure 7 is an explanatory diagram showing an example of a signal exchanged between the sequencer 520 and the request arbitration circuit 530 in Figure 5. Figure 8 is an explanatory diagram showing an example of a signal exchanged between the request arbitration circuit 530 and the protocol generation circuit 540 in Figure 5.

Figure 9 is a timing diagram showing an example of the operation of the protocol generation circuit 540 in Figure 5. After the signal names in Figure 9, (I) indicates an input signal, (O) indicates an output signal, and (I/O) indicates an input/output signal. Figure 10 is an explanatory diagram showing an example of values set in each register in the timing diagram of Figure 9. As shown in Figure 10, the protocol generation circuit 540 receives five sets of control parameter values for Phase 0 to Phase 4, and operates as a sequencer according to the control parameters.

In FIG. 9 (1), an access request is issued when the request issuance signal ACC_REQ becomes logical 1. At this time, the parameter signal ACC_PARAM is set to the setting value of the parameter of the access request.

At (2), the protocol generation circuit 540 detects a logical value of 1 for the request issuance signal ACC_REQ. At this time, the busy signal ACC_BUSY has a logical value of 0, and access to the serial ROM 200 is possible. Therefore, the protocol generation circuit 540 asserts a request acknowledge signal ACC_ACK to a logical value of 1 and asserts a chip select signal /CS to a logical value of 0, and starts accessing the serial ROM 200.

The protocol generation circuit 540 first starts accessing the serial ROM 200 using parameters for Phase 0. The CLKL width and CLKH width are set to values that indicate one system clock (1 SYSCLK). Therefore, the SPI controller 500 generates a clock signal CLK that is the system clock SYSCLK divided by two.

In Phase 0, one data terminal IO is used to output EBh set in the data register in eight clock cycles. Therefore, the protocol generation circuit 540 outputs 03h, which indicates a Fast Read Quad I/O command, to the serial ROM 200 in series until the period (11).

(11) to (17) are Phase 1, and the address is output in the Fast Read Quad I/O command according to the setting value of Phase 1. Note that in the case of memory-mapped access, the address included in the access request from the CPU 300 is used, so the output data selection register is set to a logical value of 1. In the case of indirect access, the value set in the data register is used as the address, so the output data selection register is set to a logical value of 0.

(17) to (19) are Phase 2, in which the logical value of the mode in the Fast Read Quad I/O command is output to the serial ROM 200. (19) to (23) are Phase 3, which corresponds to the dummy cycle DMY in the Fast Read Quad I/O command. The number of clock cycles in the dummy cycle DMY is set according to the interface specifications of the serial ROM 200. The dummy cycle DMY ensures a waiting time from when the command (address) is output to the serial ROM 200 until the read data is output.

(23) to (31) are Phase 4, during which data is output from the serial ROM 200 in the Fast Read Quad I/O command. The protocol generation circuit 540 outputs the data received from the serial ROM 200 as a read data signal ACC_RD to the sequencer 520 via the request arbitration circuit 530 during the period from (25) to (33). The protocol generation circuit 540 also asserts the read data valid signal ACC_RDRDY to a logical value of 1 during the data output period by the read data signal ACC_RD. The data read from the serial ROM 200 is then stored in one of the data buffers 524, 527 of the sequencer 520 via the request arbitration circuit 530.

After the access to the serial ROM 200 by Phase 1 to Phase 4 shown in FIG. 9 is completed, the chip select signal /CS is negated to a high level. For example, the chip select signal /CS is negated one clock cycle (1 CLKL width + 1 CLKH width) of the clock signal CLK after the end of the final Phase 4.

Figure 11 is a timing diagram showing an example of the operation of the request arbitration circuit 530 of Figure 5. As in Figure 9, (I) after the signal name indicates an input signal, and (O) after the signal name indicates an output signal. In addition, a signal with the same name as a register name is set to the same logical value as the setting value of the register.

First, in (1), the request arbitration circuit 530 receives a request issuance signal MMA_REQ asserted to a logical value of 1 from the sequencer 520 and detects the occurrence of a memory mapped access request. The request arbitration circuit 530 also receives a request issuance signal IDA_REQ asserted to a logical value of 1 from the sequencer 520 and detects the occurrence of an indirect access request. In other words, the request arbitration circuit 530 detects that a memory mapped access request and an indirect access request have occurred simultaneously.

In (2), the request arbitration circuit 530 arbitrates indirect access requests with priority over memory-mapped access requests. As a result, while the serial ROM 200 is being accessed by an indirect access request, access to the serial ROM 200 by a memory-mapped access request is prohibited.

The request arbitration circuit 530, which has determined that access is to be made by an indirect access request, outputs a request acknowledge signal IDA_ACK asserted to a logical value of 1 to the sequencer 520. The request arbitration circuit 530 also outputs the contents (IDP_P0) of the parameter signal IDA_PARAM received from the sequencer 520 to the protocol generation circuit 540 as a parameter signal ACC_PARAM. At the same time, the request arbitration circuit 530 outputs a request issue signal ACC_REQ asserted to a logical value of 1 to the protocol generation circuit 540.

In (2), the request arbitration circuit 530 outputs a shift request signal IDA_NEXT asserted to a logical value of 1 to the sequencer 520, requesting that the next parameter be shifted to current in response to the indirect access request. This is because the shift enable signal IDA_SHIFT received from the sequencer 520 is asserted to a logical value of 1, and the indirect access request is permitted. The shift enable signal IDA_SHIFT of logical value 1 indicates a request to copy the contents of the indirect control register 526 for next to those for current, based on the execution of an access to the serial ROM 200 due to the indirect access request.

In (3), the request arbitration circuit 530 receives the request acknowledge signal ACC_ACK, which is asserted to a logical value of 1, and the busy signal ACC_BUSY from the protocol generation circuit. The request arbitration circuit 530 also receives the contents of the parameter signal IDA_PARAM (IDP_P1) from the sequencer 520.

During periods (6) to (8), the request arbitration circuit 530 receives read data (RD_IO0, RD_IO1) from the serial ROM 200 as a read data signal ACC_RD via the protocol generation circuit 540. The request arbitration circuit 530 detects that the read data signal ACC_RD is valid data by the read data valid signal ACC_RDRDY asserted to a logical value of 1.

The request arbitration circuit 530 outputs the received read data (RD_IO0, RD_IO1) to the sequencer 520 as a read data signal IDA_RD during the period (7) to (9). The request arbitration circuit 530 asserts the read data valid signal IDA_RDRDY to a logical value of 1 while it is outputting a valid read data signal IDA_RD. The read data (RD_IO0, RD_IO1) is stored in the indirect data buffer 527 of the sequencer 520.

At (9), the request arbitration circuit 530 detects the negation (logical value 0) of the busy signal ACC_BUSY from the protocol generation circuit 540. The request arbitration circuit 530 also detects that the request issuance signal MMA_REQ and the request issuance signal IDA_REQ are both asserted at this timing. To give priority to arbitrating the indirect access request, the request arbitration circuit 530 asserts the request acknowledge signal IDA_ACK at (9).

The request arbitration circuit 530 also outputs the contents (IDP_P1) of the parameter signal IDA_PARAM received in (3) to the protocol generation circuit 540 as the parameter signal ACC_PARAM, and at the same time asserts the request issue signal ACC_REQ. In response to this, in (10), the request arbitration circuit 530 receives the request acknowledge signal ACC_ACK and busy signal ACC_BUSY asserted from the protocol generation circuit 540.

In addition, in (10), the request arbitration circuit 530 outputs a shift request signal MMA_NEXT asserted to a logical value of 1 to the sequencer 520, requesting that the next parameters of the control register 523 for memory mapped access be shifted to the current parameters. This is because the shift enable signal MMA_SHIFT received from the sequencer 520 is asserted to a logical value of 1, and the indirect access request is permitted. The shift enable signal MMA_SHIFT of logical value 1 indicates a request to copy the next contents of the control register 523 for memory mapped access to the current parameters based on the access execution of the serial ROM 200 due to the indirect access request.

Next, in (13), the request arbitration circuit 530 detects the negation of the busy signal ACC_BUSY from the protocol generation circuit 540. The request arbitration circuit 530 also detects the assertion of only the request issue signal MMA_REQ from the sequencer 520. As a result, the request arbitration circuit 530 outputs the request acknowledge signal MMA_ACK, asserted to a logical value of 1, to the protocol generation circuit 540.

The request arbitration circuit 530 also outputs the contents (MMA_P1) of the parameter signal IDA_PARAM to the protocol generation circuit 540 as the parameter signal ACC_PARAM, and at the same time asserts the request issue signal ACC_REQ. In response to this, at (15), the request arbitration circuit 530 receives the request acknowledge signal ACC_ACK and busy signal ACC_BUSY asserted from the protocol generation circuit 540. Then, at (16) to (18), the request arbitration circuit 530 receives the read data DR_M10 and RD_M11 from the serial ROM 200 via the protocol generation circuit 540.

Figure 12 is a flow diagram showing an example of the operation of the SPI controller 500 in Figure 1 to switch the serial ROM 200 from single mode to XIP mode. Figure 12 shows an example of a control method of the SPI controller 500. The switch to the XIP mode is executed by the sequencer 520 based on the writing of parameters by the CPU 300 to the control registers 522 and 525 in the sequencer 520.

First, in step S10, based on a write command from the CPU 300, parameters for reading data from the serial ROM 200 in XIP mode are set for the next parameter of the control register 523 for memory-mapped access (Fast Read Quad I/O (XIP)). The parameters set for the next parameter of the control register 523 for memory-mapped access are used in the first command executed after entering the XIP mode.

Next, in step S12, based on a write command from CPU 300, a parameter for entering XIP mode is set for the current indirect access control register 526 (Fast Read Quad I/O (XIP transition)). For example, entry into XIP mode is performed together with an access to read read data from serial ROM 200 in quad mode.

Next, in step S14, a "1" is set in the shift enable register (memory mapped) based on a write command from CPU 300. Next, in step S16, a "1" is set in the request issuing register for indirect access based on a write command from CPU 300.

Next, in step S18, the sequencer 520 issues a read access request to the serial ROM 200 to switch to the XIP mode based on step S16. Then, based on the read access request to switch to the XIP mode, the sequencer 520 stores the read data output from the serial ROM 200 in the data register and resets the request issuing register for indirect access to "0". This completes the operation to switch to the XIP mode. After the operation shown in FIG. 12 is completed, the read operation in the XIP mode shown in FIG. 4 is repeatedly executed, thereby improving the efficiency of reading the program from the serial ROM 200.

Figure 13 is an explanatory diagram showing an example of the settings of the memory-mapped current control register when executing the flow of Figure 12. The memory-mapped current control register shown in Figure 13 is set as a default value. Figure 13 shows an example of parameters set in the memory-mapped current control register to execute a read operation (normal read) in single mode in parallel with the setting of parameters in various registers according to the flow of Figure 12. The state of the register shown in Figure 13 is set by the sequencer 520 in response to a read access request from the CPU 300 when the serial ROM 200 is set to single mode.

In a read operation performed on the serial ROM 200 in the state shown in FIG. 13, the sequencer 520 outputs a command and address to the serial ROM 200 and receives read data from the serial ROM 200 according to the information set in the registers of Phases 0 to 2. Then, the read operation shown in FIG. 2 is executed. In a memory-mapped access, the sequencer 520 outputs the data received from the serial ROM 200 and stored in the data buffer 524 to the CPU 300 in response to the read access request.

Figure 14 is an explanatory diagram showing an example of the setting of the memory-mapped next control register when executing the flow of Figure 12. Figure 14 shows the next state of the memory-mapped access control register 523 after execution of step S10 of Figure 12. An example of a read operation executed on the serial ROM 200 in the state shown in Figure 14 is shown in Figure 4.

Figure 15 is an explanatory diagram showing an example of the setting of the current control register for indirect access when executing the flow of Figure 12. Figure 15 shows the current state of the control register 526 for indirect access after execution of step S12 of Figure 12, which is set when the serial ROM 200 transitions from single mode to XIP mode.

Figure 16 is an explanatory diagram showing an example of the settings of the indirect next control register when executing the flow of Figure 12. For example, the next control register 526 for indirect access is not used when switching from single mode to XIP mode. In this case, the sequencer 520 maintains or sets the parameters of each register to "0" (invalid) or "Don't Care".

Figure 17 is a timing diagram showing an example of the operation of the SPI controller 500 in Figure 5 that transitions the serial ROM 200 from single mode to XIP mode. Detailed description of operations similar to those in Figure 2 will be omitted. The operations shown in Figures 17 to 20 show an example of a control method of the SPI controller 500.

The operation shown in FIG. 17 is executed under the control of the sequencer 520 based on the parameter settings shown in FIG. 13. First, at (1), the reset signal reset_n is released to a logical value of 1, and the SPI controller 500 starts operation. Thereafter, the reset signal reset_n is maintained at a high level "H". As shown in CPU access, the CPU 300 issues a memory-mapped access request (read request) to fetch instructions for its own operation. Note that immediately after the release of the reset signal reset_n, the serial ROM 200 is set to single mode.

Next, in (2), the status of the request arbitration circuit 530 is low level "L". Therefore, in response to a memory-mapped access request from the CPU 300, the SPI controller 500 executes a read operation in single mode using the setting value of the memory-mapped control register 523. Here, the low level "L" of the request arbitration circuit status indicating the status of the request arbitration circuit 530 indicates a state in which no indirect access request has been generated and memory-mapped access requests are not prohibited.

The read operation of the serial ROM 200 in single mode in response to a memory-mapped access request is executed as follows: (2) to (3), and the read data RDT read from the serial ROM 200 is returned to the CPU 300, completing the read operation.

The CPU 300 issues a memory-mapped access request (read) in (4) to fetch the next instruction. The SPI controller 500 permits this memory-mapped access request in (5), and in (5) to (6), a read operation is performed in single mode, similar to (2) to (3).

Next, in FIG. 18, the CPU 300 issues an access request for setting the next parameter of the memory-mapped control register 523. The various parameters for memory-mapped access read from the serial ROM 200 based on the access request are set for the next parameter of the control register 523 in (7). The memory-mapped next parameter is a memory access request in XIP mode (read; Fast Read Quad I/O (XIP)) that is executed immediately after switching to the XIP mode.

In this embodiment, the current register of the memory-mapped control register 523 can be used to access the serial ROM 200 in single mode (fetching a program) while pre-storing an instruction in the XIP mode for the next register. In addition, when the shift enable register (memory-mapped) is set, the transfer of an instruction from the next register to the current register is performed based on the output of an instruction from the current register of the indirect control register 526. As a result, as shown in Figures 18 and 19, after switching the serial ROM 200 to the XIP mode using the current register of the indirect access control register 526, an instruction in the XIP mode can be executed quickly.

At (7), the CPU 300 issues an access request for setting the current indirect control register 526. At (8), various parameters for indirect access read from the serial ROM 200 based on the access request are set as the current indirect control register 526. The current indirect parameters are a memory access request (read; Fast Read Quad I/O (Enter XIP mode)) for entering XIP mode.

In this embodiment, the control register 523 for memory-mapped access and the control register 526 for indirect access are provided independently of each other. This allows the control register 526 to store an instruction for the XIP mode in advance before using the control register 526 to switch to the XIP mode. In other words, the instruction for switching the serial ROM 200 to the XIP mode and the XIP mode instruction to be executed after switching can be held simultaneously.

Then, the CPU 300 issues a memory-mapped access request (read) to fetch the next instruction. The SPI controller 500 permits this memory-mapped access request in (9), and in (9) to (10), a read operation is performed in single mode, as in FIG. 17. In (10), the CPU 300 issues a request to set the shift enable register (memory mapped) to "1", and the shift enable register (memory mapped) is set to "1".

In (11) of FIG. 19, the CPU 300 issues an access request that sets the request issuing register for indirect to "1". The request issuing register for indirect is set to "1" in (12). In response to the "1" in the request issuing register for indirect, the sequencer 520 outputs parameters including the instruction held for current use in the control register 526 to the request arbitration circuit 530. The request issuing registers are provided corresponding to both indirect access and memory-mapped access. This allows the access requests held for each of the control registers 526 and 523 to be issued to the serial ROM 200 via the request arbitration circuit 530 at any position in the program executed by the CPU 300.

The request arbitration circuit 530 prohibits the selection of a memory-mapped access command based on the reception of an indirect access command, and sets the request arbitration circuit status to high level "H". In other words, when there is a conflict between the reception of an indirect access command and the reception of a memory-mapped access command, the request arbitration circuit 530 prohibits the output of the memory-mapped access command to the serial ROM 200.

Here, a high level "H" request arbitration circuit status indicates that an indirect access request has occurred and memory-mapped access requests are prohibited. The request arbitration circuit status is internal information of the request arbitration circuit 530, but may be output to the outside of the request arbitration circuit 530 as an inhibition signal indicating inhibition of the selection of an instruction for memory-mapped access.

The arbitration control of the request arbitration circuit 530 can, for example, prevent the XIP mode command held in the control register 523 from being executed before the command to switch to XIP mode held in the control register 526. Therefore, when switching the operation mode of the serial ROM 200, it is possible to prevent the operation mode of the serial ROM 200 from becoming inconsistent with the operation mode of the command supplied to the serial ROM 200, and it is possible to prevent malfunction of the serial ROM 200. As a result, it is possible to prevent malfunction of the system SYS.

The request arbitration circuit 530 outputs the indirect access request (a command to enter XIP mode) selected by arbitration to the serial ROM 200 and notifies the sequencer 520 of the issuance of the indirect access request. The shift enable register (memory mapped) is set to "1" in (10) of FIG. 18. Therefore, based on the notification of the issuance of the indirect access request, the sequencer 520 copies the contents of the memory mapped control register (for next) to the memory mapped control register (for current) in (13).

By providing a shift enable register (memory mapped), in response to the issuance of an indirect access request, the memory mapped access request issued thereafter can be set as the current one in the control register 523 for memory mapped access. Therefore, for example, after switching to XIP mode in an indirect access request, it is possible to execute a XIP mode instruction in a memory mapped access request.

On the other hand, if it is not clear where in a sequence of multiple consecutive memory-mapped access requests the XIP mode switch command for an indirect access request will be inserted due to the arbitration order by the request arbitration circuit 530, the following problems will occur. For example, if a XIP mode switch command is inserted between consecutive memory-mapped access requests in single mode, the access request in single mode after switching to XIP mode will not be executed normally. Also, if a XIP mode switch command is inserted between consecutive memory-mapped access requests in XIP mode, the access request in XIP mode before switching to XIP mode will not be executed normally.

In (14) to (15), a Fast Read Quad I/O (Enter XIP mode) access is executed to enter the serial ROM 200 into the XIP mode, and the operation mode of the serial ROM 200 is switched from the single mode to the XIP mode. When the access to the serial ROM 200 by the indirect access request is completed (16), the request arbitration circuit 530 returns the request arbitration circuit status to the low level "L". This releases the prohibition of output of the memory-mapped access request to the serial ROM 200. By prohibiting the selection of the memory-mapped access request until the access to the serial ROM 200 by the indirect access request that triggered the prohibition of the output of the memory-mapped access request is completed, it is possible to prevent malfunction of the SPI controller 500. In addition, it is possible to minimize the waiting time until the serial ROM 200 is accessed by the memory-mapped access request after switching to the XIP mode.

In FIG. 20, the CPU 300 issues a memory-mapped access request (read) in (17) to fetch the next instruction. The SPI controller 500 permits this memory-mapped access request in (18). At this point, parameters for Fast Read Quad I/O (XIP mode) are set in the memory-mapped control register (for current). Therefore, the SPI controller 500 executes the read operation of the serial ROM 200 in XIP mode without issuing an instruction code in (18) to (19). Then, the read data RDT read from the serial ROM 200 is returned to the CPU 300, and the read operation in XIP mode is completed.

Note that, before the reset signal reset_n in FIG. 17 is released, an instruction for switching to the XIP mode may be stored in advance in the control register 526 for indirect access, and an instruction for the XIP mode may be stored in advance in the control register 523 for memory-mapped access. Then, before the reset signal reset_n in FIG. 17 is released, the request issuing register for indirect may be set to "1" in advance. In this case, the CPU 300 issues a request to set the shift enable register (memory-mapped) to "1" at the beginning after the reset signal reset_n is released, so that switching to the XIP mode can be executed at the beginning of the program. As a result, the efficiency of instruction execution can be improved compared to the case where multiple single mode instructions are executed after the reset signal reset_n is released, and the performance of the system SYS can be improved.

As described above, in this embodiment, when an instruction held in the control register 526 for indirect access is output to the serial ROM 200, the instruction held in the control register 523 for memory mapped access is prohibited from being output to the serial ROM 200. As a result, for example, when an instruction for switching the operation mode of the serial ROM 200 is output from the control register 526, it is possible to prevent an instruction for the post-switching operation mode from being output to the serial ROM 200 before the switching of the operation mode.

In addition, it is possible to prevent a command for an operation mode different from the operation mode to be switched from being output to the serial ROM 200 after the operation mode is switched. As a result, it is possible to prevent malfunction of the serial ROM 200 and to prevent malfunction of the system SYS. In other words, it is possible to switch the operation mode of the serial ROM 200 while continuing access to the serial ROM 200.

Since the control register 523 for memory-mapped access and the control register 526 for indirect access are provided independently of each other, it is possible to store an instruction for the XIP mode in the control register 526 before switching to the XIP mode. In other words, it is possible to simultaneously hold an instruction to switch the serial ROM 200 to the XIP mode and an instruction for the XIP mode to be executed after switching.

The request issuing registers are provided for indirect access and memory mapped access, respectively. This allows the access requests held in the control registers 526 and 523 to be issued to the serial ROM 200 via the request arbitration circuit 530 at any position in the program executed by the CPU 300. It is also possible to flexibly accommodate new devices.

By prohibiting the selection of a memory-mapped access request until the access to the serial ROM 200 by the indirect access request that triggered the prohibition of the output of the memory-mapped access request is completed, it is possible to prevent malfunction of the SPI controller 500. In addition, it is possible to minimize the waiting time until the serial ROM 200 is accessed by a memory-mapped access request after switching to the XIP mode.

The sequencer 520 has, in its memory-mapped control register 523, a current register that holds the instruction issued by the serial ROM 200, and a next register that holds the instruction to be issued after the current register. This makes it possible to use the current register to access the serial ROM 200 in single mode (fetch a program), while pre-storing an instruction for XIP mode for the next register.

In addition, when the shift enable register (memory mapped) is set, the transfer of an instruction from the next register to the current register is performed based on the output of an instruction from the current register of the indirect control register 526. As a result, after the serial ROM 200 is switched to the XIP mode using the current register of the indirect access control register 526, the XIP mode instruction can be executed quickly.

Second Embodiment
Fig. 21 is a block diagram showing an example of an SPI controller according to a second embodiment of the present invention. The same elements as those in Fig. 5 are given the same reference numerals, and detailed description thereof will be omitted. The SPI controller 500A shown in Fig. 21 has a sequencer 520A instead of the sequencer 520 of the SPI controller 500 in Fig. 5.

The sequencer 520A has a common control register 528A instead of the common control register 528 of the sequencer 520 in FIG. 5. The common control register 528A has a parameter read control register 529A added to the common control register 528. The parameter read control register 529A is an example of a parameter read request flag. The parameter read control register 529A has a flag that triggers the operation of reading parameters from the serial ROM 200 and setting them in a register in the SPI controller 500A, and a buffer. The data read from the serial ROM 200 is temporarily stored in the buffer when the flag is set.

The rest of the configuration of the SPI controller 500A is the same as the configuration of the SPI controller 500 in FIG. 5. In addition, the configuration of the system SYS including the SPI controller 500A is the same as that in FIG. 1.

Figure 22 is an explanatory diagram showing an example of the setting contents of the registers provided in the sequencer 520A of Figure 21. In Figure 22, the setting contents of the parameter read control register 529A of Figure 21 are added to the setting contents of Figure 6. When the parameter read control register 529A is "1", the SPI controller 500A stores the parameters read from the serial ROM 200 in the control register group 522 for memory mapped access and the control register group 525 for indirect access. For example, the parameter read control register 529A is set to "1" when the reset signal reset_n is released (when the logical value changes from 0 to 1). After storing the various parameters read from the serial ROM 200 in the registers, the SPI controller 500 resets the parameter read control register 529A to "0".

Figure 23 is a timing diagram showing an example of the operation of the SPI controller 500A in Figure 21 that transitions the serial ROM 200 from the single mode to the command omission mode. Detailed explanations of operations similar to those in Figures 17 to 20 will be omitted. The operations shown in Figures 23 to 25 show an example of a control method of the SPI controller 500A.

In this embodiment, before the operation of FIG. 23, a logical value of 1 is set to the flag of the parameter read control register 529A. Also, parameters for reading 128 bytes of data in single mode from the last address of the serial ROM 200 (e.g., FFFF80h) are stored for the current of the control register 526 for indirect access. In FIG. 23 to FIG. 25, the setting value of the parameter read control register 529A is shown as the logical value of the parameter read request signal PReadreq (high level "H" in FIG. 23).

In FIG. 23 (1), the reset signal reset_n is cleared to logical 1, and the SPI controller 500 starts operating. When the flag of the parameter read control register 529A is set to logical 1, the CPU 300 issues a memory-mapped access request (read request) to fetch instructions for its own operation (memory-mapped read), as shown in CPU access. However, because the request arbitration circuit status is set to the high level "H", access requests from the memory-mapped side (i.e., the CPU 300) are prohibited by the request arbitration circuit 530.

In (2), the SPI controller 500A executes a read operation to read 128 bytes of data from the last address of the serial ROM 200 in accordance with the parameter read command held for current use in the indirect access control register 526. The read operation is executed in single mode. For example, the address where the data to be read is stored and the number of bytes of the data to be read are stored in the operand of the command executed by the CPU 300. The SPI controller 500A sequentially accumulates the data read from the serial ROM 200 in the buffer of the parameter read control register 529A.

When the read operation is completed (3), the SPI controller 500A transfers the data stored in the buffer to the next register of the control register 523 for memory mapped access and the current register of the control register 526 for indirect access. The SPI controller 500A also sets the request issuing register of the control register group 525 for indirect access to "1".

As shown in FIG. 23, in this embodiment, when the SPI controller 500A is started, data stored in the serial ROM 200 can be read as an instruction for a memory-mapped access request and an instruction for an indirect access request. Then, parameters for Fast Read Quad I/O (XIP) are set for the next of the control register 523 for memory-mapped access. Parameters for Fast Read Quad I/O (Enter XIP mode) are set for the current of the control register 526 for indirect access.

Therefore, parameters can be stored in the control registers 523 and 526 without the CPU 300 executing commands to store the parameters in the control registers 523 and 526. As a result, for example, switching from single mode to XIP mode can be efficiently executed. Since data stored in the serial ROM 200 can be set as parameters in the control registers 523 and 526, it is possible to flexibly respond to new devices.

Note that FIG. 23 shows the operation when the read request signal PReadreq is set to a logical value of 1 when the reset signal reset_n is released, but the read request signal PReadreq may also be set to a logical value of 1 by a write access by the CPU 300. In this case, while the read request signal PReadreq is a logical value of 0, the memory access by the CPU 300 is executed using the current register of the control register 523 for memory-mapped access. Then, based on the change of the read request signal PReadreq to a logical value of 1, the operation from (2) in FIG. 23 is started.

In FIG. 24 (4), when the request issuing register of the indirect access control register group 525 is set to "1", the request arbitration circuit status is maintained at high level "H". Therefore, the SPI controller 500A starts a Fast Read Quad I/O (Enter XIP mode) access according to the current parameters of the indirect access control register 526. Execution of the Fast Read Quad I/O (Enter XIP mode) access causes the serial ROM 200 to transition from single mode to XIP mode.

When the access of Fast Read Quad I/O (Enter XIP mode) is completed in (5), the SPI controller 500A changes the request arbitration circuit status to low level "L" to allow access from the memory-mapped side. The SPI controller 500A also changes the parameter read request signal PReadreq to low level "L". At this point, Fast Read Quad I/O (for XIP) is transferred from the next to the current of the control register 523 for memory-mapped access.

In FIG. 25 (6), a Fast Read Quad I/O (for XIP) access is started according to the current parameters of the memory-mapped access control register 523. When the Fast Read Quad I/O (for XIP) access is executed, read data is output from the serial ROM 200, and the XIP mode read operation is completed in (7).

As described above, this embodiment can also achieve the same effects as the above-mentioned embodiment. Furthermore, in this embodiment, parameters can be stored in the control registers 523 and 526 without the CPU 300 executing commands to store parameters in the control registers 523 and 526. As a result, for example, switching from single mode to XIP mode can be efficiently executed. Data stored in the serial ROM 200 can be set in the control registers 523 and 526 as parameters, so that new devices can be flexibly supported.

The present invention has been described above based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form.

100 SoC
200 Serial ROM
300 CPU
400 Decoder 500, 500A SPI controller 510 CPU interface circuit 520, 520A Sequencer 522 Control register group 523 Control register 524 Data buffer 525 Control register group 526 Control register 527 Data buffer 528, 528A Common control register 530 Request arbitration circuit 540 Protocol generation circuit 600 RAM
700 Input/Output Interface Unit 800 Network Interface Unit AD Address CLK Clock Signal DMY Dummy Cycle INS Command IO (IO0-IO3) Data Terminal MD Mode RDT Read Data reset_n Reset Signal SYS System

JP 2017-045311 A

Claims (7)

An interface circuit for controlling access to a serial memory that can switch between a serial mode in which data is transferred using one signal line and a parallel mode in which data is transferred using a plurality of signal lines, comprising:
a first interface unit for indirect access including a first instruction storage unit that stores an instruction for accessing the serial memory output from a processor that executes a program stored in the serial memory, the first interface unit outputting the instruction stored in the first instruction storage unit;
a second interface unit for memory mapped access that converts a memory access request from the processor into an instruction that can be accepted by the serial memory and outputs the converted instruction;
an arbitration unit that outputs a command output from the first interface unit or the second interface unit to the serial memory, and when reception of a command from the first interface unit and reception of a command from the second interface unit conflict with each other, prohibits output of the command received from the second interface unit;
having
The second interface unit is
a second instruction storage unit for storing the converted instruction;
a third instruction holding unit to which the converted instruction is transferred from the second instruction holding unit,
the first interface unit has a shift flag which is set when the converted instruction is transferred from the second instruction holding unit to the third instruction holding unit in response to an output of the instruction held in the first instruction holding unit;
An interface circuit comprising: 2. The interface circuit according to claim 1, wherein the instruction held in the first instruction holding unit is an instruction for switching the serial memory from the serial mode to the parallel mode. The first interface unit is
a request issue flag set by the processor;
3. The interface circuit according to claim 1, further comprising: a first instruction holding unit that outputs an instruction held in said first instruction holding unit in response to said request issue flag being set. The first interface unit is
a request issuing flag that is set when the interface circuit is started;
3. The interface circuit according to claim 1, wherein when the request issue flag is set, the interface circuit outputs a command previously held in the first command holding unit. 5. The interface circuit according to claim 3, wherein the arbitration unit that has prohibited output of the command received from the second interface unit prohibits output of the command received from the second interface unit until operation of the serial memory based on the command from the first interface unit that was output to the serial memory is completed. A parameter read request flag is provided.
6. The interface circuit according to claim 1, wherein when the parameter read request flag is set when the interface circuit is started, the first interface unit stores data read from the serial memory in accordance with execution of an instruction stored in the first instruction holding unit in the first instruction holding unit as an instruction for accessing the serial memory. A control method for an interface circuit including a first interface unit for indirect access, a second interface unit for memory mapped access, and an arbitration unit , for controlling access to a serial memory switchable between a serial mode in which data is transferred using one signal line and a parallel mode in which data is transferred using a plurality of signal lines, the control method comprising:
the first interface unit including a first instruction holding unit and a shift flag, the first instruction holding unit holding an instruction for accessing the serial memory output from a processor that executes a program held in the serial memory, outputs the instruction held in the first instruction holding unit ;
the second interface unit including a second instruction holding unit and a third instruction holding unit converts a memory access request from the processor into an instruction that can be accepted by the serial memory, holds the converted instruction in the second instruction holding unit, and transfers the converted instruction from the second instruction holding unit to the third instruction holding unit for output;
the arbitration unit outputs a command output by the first interface unit or the second interface unit to the serial memory, and when there is a conflict between reception of a command from the first interface unit and reception of a command from the second interface unit, prohibits output of the command received from the second interface unit ;
the shift flag is set when the converted instruction is transferred from the second instruction holding unit to the third instruction holding unit in response to an output of the instruction held in the first instruction holding unit .

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