JP2021174051A - Interface circuit and control method of interface circuit - Google Patents

Abstract

To switch an operation mode of a serial memory while continuing an access to the serial memory.SOLUTION: An interface circuit of controlling an access to a serial memory capable of switching between a serial mode and a parallel mode includes a first instruction holding unit that holds an instruction for access of the serial memory output from a processor executing a program held in the serial memory, and includes: a first interface unit that outputs the instruction held in the first instruction holding unit; a second interface unit that converts a memory access request from the processor into an instruction capable of being received by the serial memory, and outputs the converted instruction; and an arbitration unit that outputs the instruction output by the first or second interface unit to the serial memory, and when conflict occurs between reception of the instruction from the first interface unit and reception of the instruction from the second interface unit, prohibits outputting of the instruction from the second interface unit.SELECTED DRAWING: Figure 5

Description

The present invention relates to an interface circuit and a method for controlling the interface circuit.

A memory system in which a plurality of sets of interface circuits and a memory chip are mounted in the same package and the memory chips can be accessed by each interface circuit according to each of a plurality of chip select signals from the outside is disclosed ( For example, see Patent Document 1). In this type of memory system, the use of a memory chip with a serial interface suppresses an increase in the area of the mounting board on which the memory chip and the interface circuit are mounted.

Recently, serial interfaces such as SPI (Serial Peripheral Interface: registered trademark) have a serial mode in which data is transferred using one signal line and a parallel mode in which data is transferred using multiple signal lines. Has. Further, a processor such as a CPU (Central Processing Unit) is connected to the serial memory via an interface circuit in order to make the serial memory of various interfaces accessible. The interface circuit can control access to serial memories having various specifications by changing the set value of the setting register.

A processor such as a CPU (Central Processing Unit) that reads a program or the like from a serial memory using this type of serial interface usually starts fetching a program in a serial mode at power-on. Therefore, in order to increase the data transfer rate and improve the access efficiency of the serial memory, it is necessary to switch the operation mode of the serial memory from the serial mode to the parallel mode.

However, if the operation mode is changed while the CPU is fetching the program from the serial memory, there is a risk of malfunction. In order to suppress malfunction, for example, the operation mode of the serial memory is switched while the program stored in the serial memory is transferred to another memory such as RAM and the program on the other memory is fetched. Be done. In this case, the fetch efficiency is lowered because the fetch of the program to the serial memory is not executed during the transfer of the program to the RAM or the like.

The present invention has been made in view of the above problems, and an object of the present invention is to switch the operation mode of the serial memory while continuing to access the serial memory.

In order to solve the above technical problems, the interface circuit of one embodiment of the present invention includes a serial mode in which data is transferred using one signal line and a parallel mode in which data is transferred using a plurality of signal lines. An interface circuit that controls access to the serial memory that can be switched, and is a first instruction holding unit that holds an instruction for accessing the serial memory output from a processor that executes a program held in the serial memory. A first interface unit that includes and outputs an instruction held in the first instruction holding unit, and a second interface that converts a memory access request from the processor into an instruction that can be accepted by the serial memory and outputs the converted instruction. The unit and the instruction output by the first interface unit or the second interface unit are output to the serial memory, and the reception of the instruction from the first interface unit and the reception of the instruction from the second interface unit conflict with each other. In this case, it has an arbitration unit that prohibits the output of instructions received from the second interface unit.

It is possible to switch the operation mode of the serial memory while continuing to access the serial memory.

It is a block diagram which shows an example of the system which mounts the SPI controller which concerns on 1st Embodiment of this invention. It is a timing diagram which shows an example of the read operation in the single mode of the serial ROM of FIG. It is a timing diagram which shows an example of the read operation in the QPI mode of the serial ROM of FIG. It is a timing diagram which shows an example of the read operation in the XIP mode of the serial ROM of FIG. It is a block diagram which shows an example of the SPI controller of FIG. It is explanatory drawing which shows an example of the setting contents of the register provided in the sequencer of FIG. It is explanatory drawing which shows an example of the signal sent and received between the sequencer of FIG. 5 and the demand arbiter circuit. It is explanatory drawing which shows an example of the signal sent and received between the request arbitration circuit and the protocol generation circuit of FIG. It is a timing diagram which shows an example of the operation of the protocol generation circuit of FIG. It is explanatory drawing which shows an example of the value set in each register in the timing diagram of FIG. It is a timing diagram which shows an example of the operation of the demand arbiter circuit of FIG. FIG. 5 is a flow chart showing an example of an operation in which the SPI controller of FIG. 1 switches the serial ROM from the single mode to the XIP mode. It is explanatory drawing which shows the setting example of the current control register for memory-mapped when the flow of FIG. 12 is executed. It is explanatory drawing which shows the setting example of the next control register for memory-mapped when the flow of FIG. 12 is executed. It is explanatory drawing which shows the setting example of the current control register for indirect when the flow of FIG. 12 is executed. It is explanatory drawing which shows the setting example of the next control register for indirect when the flow of FIG. 12 is executed. FIG. 5 is a timing diagram showing an example of the operation of the SPI controller of FIG. 5 for transitioning the serial ROM from the single mode to the XIP mode. It is a timing diagram which shows the continuation of FIG. It is a timing diagram which shows the continuation of FIG. It is a timing diagram which shows the continuation of FIG. It is a block diagram which shows an example of the SPI controller which concerns on 2nd Embodiment of this invention. It is explanatory drawing which shows an example of the setting contents of the register provided in the sequencer of FIG. FIG. 5 is a timing diagram showing an example of the operation of the SPI controller of FIG. 21 for transitioning the serial ROM from the single mode to the instruction omission mode. It is a timing diagram which shows the continuation of FIG. It is a timing diagram which shows the continuation of FIG.

Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals, and duplicate description may be omitted. In addition, a code indicating a signal is also used as a code indicating a terminal or a signal line.

(First Embodiment)
FIG. 1 is a block diagram showing an example of a system in which the SPI controller according to the first embodiment of the present invention is mounted. Although not particularly limited, the system SYS shown in FIG. 1 is included in, for example, an image forming apparatus such as an MFP (MultiFunction Printer) having a copy function, a facsimile function, a print function, a scanner function, and the like.

The system SYS has a SoC (System on a Chip) 100 and a serial ROM 200 such as a serial flash memory. The SoC 100 includes a CPU 300, a decoder 400, an SPI controller 500, a RAM (Random Access Memory) 600, an input / output interface unit 700, and a network interface unit 800. The serial ROM 200 is an example of a serial memory, the SPI controller 500 is an example of an interface circuit that controls access to the serial ROM 200, and the CPU 300 is an example of a processor.

The CPU 300 operates by fetching the program stored in the serial ROM 200, and controls the operation in the SoC 100 and the communication with the external device connected to the SoC 100. The CPU 300 outputs the clock signal CLK and the chip select signal / CS to the serial ROM 200, and inputs / outputs the 4-bit data signal IO (IO0-IO3) to the serial ROM 200. The data signal IO output from the CPU 300 to the serial ROM 200 may be not only a data signal but also a command signal (instruction) or an address signal. How many bits of the 4-bit data signal IO are used depends on the operation mode.

The CPU 300 directly executes the program (instruction code and operand) read from the serial ROM 200 without expanding the program held by the serial ROM 200 to the RAM 600. In order to improve the fetch efficiency of the program, for example, the CPU 300 may have a cache memory (not shown) that holds the programs fetched once in the new order.

The decoder 400 identifies the device to be accessed by decoding the address included in the access request output from the CPU 300, and outputs a select signal for accessing the specified device. The device to be accessed is an input / output device connected to the serial ROM 200, the RAM 600, the input / output interface unit 700, or various devices connected to the network connected to the network interface unit 800.

The SPI controller 500 controls access to the serial ROM 200 based on an access request to the serial ROM 200 output from the CPU 300, and reads, for example, a program or data from the serial ROM 200. The SPI controller 500 can perform access called memory-mapped access and indirect access.

In the memory-mapped access, the read access request (read command) issued by the CPU 300 is automatically converted into the command system of the serial ROM 200 by the SPI controller 500. Then, the data read from the serial ROM 200 is directly output from the SPI controller 500 to the CPU 300 without the CPU 300 executing the read command. Therefore, the CPU 300 can access the serial ROM 200 as the memory allocated on the memory map without being aware of the interface specifications of the serial ROM 200. For example, memory-mapped access applies only to read access.

In indirect access, the SPI controller 500 makes write access or read access to the serial ROM 200 based on the information written in the register in the SPI controller 500 by the CPU 300. For example, write access by indirect access is used to switch the operating mode of the serial ROM 200. An example of the internal configuration of the SPI controller 500 will be described with reference to FIG.

The RAM 600 is a so-called working RAM, and has a minimum storage capacity required for the operation of the SoC 100. The input / output interface unit 700 inputs / outputs information to / from an input / output device (not shown) connected to the system SYS. An input device or an output device may be connected to the input / output interface unit 700. The input / output interface unit 700 may be provided for each device to be connected. The network interface unit 800 communicates with other devices via a network (not shown) connected to the system SYS.

The serial ROM 200 supports, for example, a single mode, a dual mode, a quad mode, a quad parallel instruction mode, and an instruction omission mode as operation modes. In single mode, instructions and addresses are input to data terminal IO0 (DI) and read data is output in series from data terminal IO1 (DO). The single mode is an example of a serial mode in which data is transferred using one signal line (IO0 or IO1).

In the dual mode, the instruction is input to the data terminals IO0, the address is input to the data terminals IO0 and IO1, and the read data is output in parallel from the data terminals IO0 and IO1. In the quad mode, an instruction is input to the data terminals IO0, an address is input to the data terminals IO0 to IO3, and read data is output in parallel from the data terminals IO0 to IO3.

In the quad parallel instruction mode, instructions and addresses are input to data terminals IO0 to IO3, and read data is output in parallel from data terminals IO0 to IO3. The instruction omission mode is an operation mode in which the input of the instruction is omitted, and the instruction input before entering the instruction omission mode is inherited. For example, in the instruction omission mode, the address is input to the data terminals IO0 to IO3, and the read data is output in parallel from the data terminals IO0 to IO3. Dual mode, quad mode, and instruction omission mode are examples of parallel modes in which data is transferred using a plurality of signal lines.

Switching from another operation mode to the quad parallel instruction mode or the instruction omission mode is performed by inputting a switching instruction. In this case, the number of bits of the data terminal IO used for inputting the switching instruction depends on the current operation mode. Hereinafter, the quad parallel instruction mode is referred to as a QPI mode, and the instruction omission mode is referred to as an XIP mode.

FIG. 2 is a timing diagram showing an example of the read operation of the serial ROM 200 of FIG. 1 in the single mode. In FIG. 2 and subsequent timing diagrams, shading indicates Don't Care. In the single mode, the instruction INS and the address AD are input to the serial ROM 200 in synchronization with the clock signal CLK while the chip select signal / CS is at the low level, and the read data RDT is output from the serial ROM 200. The instruction INS and the address AD are input to the data terminal IO0, and the read data RDT is output from the data terminal IO1.

In FIG. 2, the instruction INS is set to 03h, but the instruction code is not limited to 03h. The "h" at the end of the instruction code indicates that the number before it is a hexadecimal number. Further, the number of bits of the instruction INS, the address AD, and the read data RDT (8 bits, 24 bits, and 32 bits (4 bytes), respectively) may not be shown. The same applies to the number of bits (number of bytes) shown in the subsequent timing diagrams. The upper limit of the frequency of the clock signal CLK in the single mode is about 50 MHz. Since the frequency of the clock signal CLK is lower than that of the QPI mode and the XIP mode, it is not necessary to insert the dummy cycle DMY (FIG. 3) between the address AD and the read data RDT in the single mode.

FIG. 3 is a timing diagram showing an example of the read operation of the serial ROM 200 of FIG. 1 in the QPI mode. The input of the chip select signal / CS and the clock signal CLK is the same as in FIG. In the QPI mode, 4-bit data terminals IO0 to IO3 are used. Then, the 8-bit instruction INS is input to the serial ROM 200 in 2 clock cycles, and the 24-bit address AD is input to the serial ROM 200 in 6 clock cycles.

After the address AD is input, the 8-bit mode MD is input to the serial ROM 200 in 2 clock cycles, the dummy cycle DMY is inserted in 4 clock cycles, and then the 4-byte read data RDT is output in 8 clock cycles.

In the QPI mode, unlike the single mode, instructions are supplied to the serial ROM 200 using the 4-bit data terminals IO0 to IO3. Therefore, in order to use the QPI mode, it is necessary to enter the serial ROM 200 in the QPI mode in advance. Entering the QPI mode is executed by setting the instruction code (EBh) of the Fast Read Quad I / O (Enter XIP mode) shown in FIG. 19 to be described later to 38h.

In FIG. 3, the EBh of the instruction INS indicates the enter of the XIP mode, and whether or not the input of the instruction INS is omitted in the next chip select signal / CS assert cycle according to the input value of the mode MD. It is determined. By inserting the dummy cycle DMY, the read operation inside the serial ROM 200 can be hidden by the dummy cycle DMY. As a result, the upper limit of the frequency of the clock signal CLK in the QPI mode is about 133 MHz, which is higher than that in the single mode.

FIG. 4 is a timing diagram showing an example of the read operation of the serial ROM 200 of FIG. 1 in the XIP mode. For example, the read operation in the XIP mode shown in FIG. 4 is executed when the mode MD indicates omission of the instruction INS in the read operation in the QPI mode shown in FIG.

The read operation in the XIP mode is the same as the read operation in the QPI mode except that the instruction INS is omitted from the read operation in the QPI mode. For example, in the XIP mode, when the mode MD indicates that the input of the instruction INS is omitted, the read operation of the XIP mode is also executed in the assert cycle of the next chip select signal / CS. On the other hand, in the XIP mode, when the mode MD indicates an instruction INS input, the QPI mode read operation including the instruction INS input is executed in the next chip select signal / CS assert cycle.

FIG. 5 is a block diagram showing an example of the SPI controller 500 of FIG. The SPI controller 500 includes a CPU interface circuit 510, a sequencer 520, a request arbiter circuit 530, and a protocol generation circuit 540. The CPU interface circuit 510 is connected to the CPU 300 of FIG. 1 via the CPU bus.

The CPU interface circuit 510 outputs, for example, a reset signal reset_n received from the CPU 300 via the CPU bus to the sequencer 520. The sequencer 520 is reset during the low level period of the reset signal reset_n, and the reset is released by the change of the reset signal reset_n to the high level, and the operation is started.

The sequencer 520 has a control register group 522 for memory-mapped access, a control register group 525 for indirect access, and a common control register 528 common to memory-mapped access and indirect access. The control register group 522 has a control register 523 used in Phase 0 to Phase 5 described later, and a data buffer 524. The control register group 525 has a control register 526 used in Phase 0 to Phase 5 described later, and a data buffer 527.

The control register 523 has a current register that holds an instruction to be output to the request arbiter circuit 530 and a next register that holds an instruction to be transferred to the current register. The control register 526 has a current register that holds an instruction to be output to the request arbiter circuit 530 and a next register that holds an instruction to be transferred to the current register. In the control register 523, the current register is an example of the third instruction holding unit, and the next register is an example of the second instruction holding unit. In the control register 526, the current register is an example of the first instruction holding unit. The specifications of the control register group 522, 525 and the common control register 528 are shown in FIG.

In the sequencer 520, the control register group 525 and the element that controls the access of the serial ROM 200 by using the control register group 525 are an example of the first interface unit. The element of the sequencer 520 that controls access to the serial ROM 200 by using the control register group 522 and the control register group 522 is an example of the second interface unit.

The sequencer 520 outputs an instruction INS or the like to the serial ROM 200 based on an access request of the serial ROM 200 received from the CPU 300 via the CPU interface circuit 510, and receives read data RDT or the like from the serial ROM 200.

The request arbitration circuit 530 arbitrates the memory-mapped access request output from the sequencer 520 and the indirect access request, and outputs the request selected by arbitration to the protocol generation circuit 540. When the request arbitration circuit 530 receives the indirect access request, the request arbitration circuit 530 masks the reception of the memory-mapped access request and outputs the indirect access request to the protocol generation circuit 540. That is, the request arbitration circuit 530 selects the indirect access request in preference to the memory-mapped access request. The required arbiter circuit 530 is an example of the arbitration unit.

The protocol generation circuit 540 is connected to the serial ROM 200 of FIG. The protocol generation circuit 540 generates a signal according to the interface specifications of the serial ROM 200 based on the memory-mapped access request or the indirect access request received from the request arbitration circuit 530, and outputs the generated signal to the serial ROM 200. Then, the serial ROM 200 is accessed under the control of the sequencer 520 based on the access request issued by the CPU 300.

FIG. 6 is an explanatory diagram showing an example of the setting contents of the register provided in the sequencer 520 of FIG. Request issuance registers are provided in the memory-mapped access control register group 522 and the indirect access control register group 525, respectively. When the request issuance register is set to "1", the sequencer 520 issues an access request according to the setting contents of the control register 523 (or 526) to the request arbiter circuit 530. After issuing the access request to the request arbiter circuit 530, the sequencer 520 returns the request issuance register to "0".

In the memory-mapped access, the sequencer 520 sets the information for accessing the serial ROM 200 in the control register 523 according to the information included in the access request from the CPU 300, and then sets the request issuance register in the control register group 522. Set "1". In indirect access, the request issuance register of the control register group 525 is set to "1" by the program executed by the CPU 300. The request issuance register is an example of a request issuance flag.

The shift enable register (memory-mapped) included in the control register group 522 is set by the CPU 300. When the shift enable register (memory-mapped) is "1", the sequencer 520 sets the contents of the next register of the memory-mapped control register 523 to the current register in response to the execution of indirect access. Copy to. The shift enable register (memory-mapped) is an example of a shift flag set when an instruction is transferred from the next to the current of the control register 523 in response to the output of the instruction from the current of the control register 526. be.

The shift enable register (indirect) included in the control register group 525 is set by the CPU 300. When the shift enable register (indirect) is "1", the sequencer 520 copies the contents of the next register of the indirect control register 526 to the current register in response to the execution of the indirect access. do.

The data buffer 524 included in the control register group 522 for memory-mapped access is used to temporarily store the read data read from the serial ROM 200. The sequencer 520 outputs the read data stored in the data buffer 524 to the CPU 300 according to the data bus width of the CPU 300 without receiving a read request from the CPU 300.

The data buffer 527 included in the control register group 525 for indirect access is used to store the read data read from the serial ROM 200. The sequencer 520 takes out the read data accumulated in the data buffer 527 in response to a read request (load instruction) from the CPU 300, and outputs the read data taken out to the CPU 300. That is, the read data held in the control register group 525 for indirect access needs to be explicitly read by the CPU 300.

In the CLKL width register, for example, the number of clocks of the system clock used in the SoC100 is set for the low level period of the clock signal CLK supplied to the serial ROM 200. The CLKH width register sets how many clocks of the system clock the high level period of the clock signal CLK is set.

The configurations of the control registers 523 and 526 of each Phase N (N = 0 to 4) of the control register groups 522 and 525 are the same as each other. Further, the current and next register configurations of the control registers 523 and 526 are the same as each other.

When the Phase valid register is "1", it indicates that the Phase is valid, and when it is "0", it indicates that the Phase is invalid. When the IO direction register is "1", it indicates the output of the data signal IO to the serial ROM 200, and when it is "0", it indicates the input of the data signal IO from the serial ROM 200. In the case of the dummy cycle DMY shown in FIGS. 3 and 4, the Phase valid register is set to "2", which is neither an input nor an output.

The number of IOs is set to "1" less than the number of valid data terminal IOs. When the IO number register is "0", 1 bit is valid, when it is "1", 2 bits are valid, and when it is "3", 4 bits are valid.

A number "1" less than the number of clock cycles of the clock signal CLK used in the Phase is set in the CLK number register. For example, a Phase with a CLK number register of "7" indicates that it uses 8 clock cycles, and a Phase with a CLK number register of "23" indicates that it uses 24 clock cycles.

When the output data selection register is "0", it indicates that the data held in the data register is output to the data terminal IO, and when it is "1", the data included in the access request from the CPU 300 is sent to the data terminal IO. Indicates to output. The data register is enabled when the output data selection register is "0", and the data held in the data register is output.

FIG. 7 is an explanatory diagram showing an example of a signal transmitted / received between the sequencer 520 of FIG. 5 and the request arbiter circuit 530. FIG. 8 is an explanatory diagram showing an example of a signal transmitted / received between the request arbitration circuit 530 and the protocol generation circuit 540 of FIG.

FIG. 9 is a timing diagram showing an example of the operation of the protocol generation circuit 540 of FIG. (I) shown after the signal name in FIG. 9 indicates an input signal, (O) indicates an output signal, and (I / O) indicates an input / output signal. FIG. 10 is an explanatory diagram showing an example of values set in each register in the timing diagram of FIG. As shown in FIG. 10, the protocol generation circuit 540 receives control parameter values for five sets of Phase 0 to Phase 4, and operates as a sequencer according to the control parameters.

In (1) of FIG. 9, an access request is issued when the request issuance signal ACC_REF becomes a logical value 1. At this time, the parameter signal ACC_PARAM is fixed to the set value of the parameter of the access request.

In (2), the protocol generation circuit 540 detects the logical value 1 of the request issuance signal ACC_CHECK. At this time, the busy signal ACC_BUSY has a logical value of 0 and is in a state where the serial ROM 200 can be accessed. Therefore, the protocol generation circuit 540 asserts the request permission signal ACC_ACK to the logical value 1 and the chip select signal / CS to the logical value 0 to start access to the serial ROM 200.

The protocol generation circuit 540 first initiates access to the serial ROM 200 using the parameters for Phase 0. The CLKL width and the CLKH width are set to values indicating one system clock (1SYSCLK). Therefore, the SPI controller 500 generates a clock signal CLK obtained by dividing the system clock SYSCLK by two.

In Phase 0, one data terminal IO is used to output the EBh set in the data register in 8 clock cycles. Therefore, the protocol generation circuit 540 outputs 03h indicating the Fast Read Quad I / O instruction in series to the serial ROM 200 until the period (11).

(11) to (17) are Phase 1, and the address is output by the Fast Read Quad I / O instruction according to the set value of Phase 1. In the case of memory-mapped access, since the address included in the access request from the CPU 300 is used, the output data selection register is set to the logical value 1. In the case of indirect access, the value of the data register setting is used as the address, so the output data selection register is set to the logical value 0.

(17) to (19) are Phase 2, and the logical value of the mode in the Fast Read Quad I / O instruction is output to the serial ROM 200. (19) to (23) are Phase 3, which corresponds to the dummy cycle DMY in the Fast Read Quad I / O instruction. The number of clock cycles of the dummy cycle DMY is set according to the interface specifications of the serial ROM 200. The dummy cycle DMY secures a waiting time from when the instruction (address) is output to the serial ROM 200 until the read data is output.

(23) to (31) are Phase 4, which is a period during which data is output from the serial ROM 200 in the Fast Read Quad I / O instruction. The protocol generation circuit 540 outputs the data received from the serial ROM 200 to the sequencer 520 via the request arbiter circuit 530 as a read data signal ACC_RD during the period (25) to (33). Further, the protocol generation circuit 540 asserts the read data valid signal ACC_RDRDY to the logical value 1 during the data output period by the read data signal ACC_RD. Then, the data read from the serial ROM 200 is stored in any of the data buffers 524 and 527 of the sequencer 520 via the request arbiter circuit 530.

After the access to the serial ROM 200 by Phases 1 to 4 shown in FIG. 9 is completed, the chip select signal / CS is negated to a high level. For example, the chip select signal / CS is negated after one clock cycle (1CLKL width + 1CLKH width) of the clock signal CLK after the end of the final Phase 4.

FIG. 11 is a timing diagram showing an example of the operation of the request arbiter circuit 530 of FIG. Similar to FIG. 9, (I) shown after the signal name indicates an input signal, and (O) shown after the signal name indicates an output signal. Further, the signal having the same name as the register name is set to the same logical value as the set value of the register.

First, in (1), the request arbiter circuit 530 receives the request issuance signal MMA_RQ asserted to the logical value 1 from the sequencer 520, and detects the occurrence of the memory-mapped access request. Further, the request arbiter circuit 530 receives the request issuance signal IDA_RQ asserted to the logical value 1 from the sequencer 520, and detects the occurrence of an indirect access request. That is, the request arbiter circuit 530 detects that the memopped access request and the indirect access request occur at the same time.

In (2), the request arbitration circuit 530 arbitrates the indirect access request in preference to the memory-mapped access request. As a result, while the serial ROM 200 is being accessed by the indirect access request, the access of the serial ROM 200 by the memory-mapped access request is prohibited.

The request arbiter circuit 530, which determines the access by the indirect access request, outputs the request permission signal IDA_ACK asserted to the logical value 1 to the sequencer 520. Further, the request arbiter circuit 530 outputs the content (IDP_P0) of the parameter signal IDA_PARAM received from the sequencer 520 to the protocol generation circuit 540 as the parameter signal ACC_PARAM. At the same time, the request arbiter circuit 530 outputs the request issuance signal ACC_CHECK asserted to the logical value 1 to the protocol generation circuit 540.

In (2), the request arbiter circuit 530 outputs the shift request signal IDA_NEXT asserted to the logical value 1 to the sequencer 520, and requests the indirect access request to shift the next parameter to the current. This is because the shift enable signal IDA_SHIFT received from the sequencer 520 is asserted to the logical value 1 and the indirect access request is permitted. The shift enable signal IDA_SHIFT of the logical value 1 indicates a request to copy the contents for the next of the control register 526 for indirect for the current based on the access execution of the serial ROM 200 by the indirect access request.

In (3), the request arbiter circuit 530 receives the request permission signal ACC_ACK and the busy signal ACC_BUSY asserted to the logical value 1 from the protocol generation circuit. Further, the request arbiter circuit 530 receives the contents (IDP_P1) of the parameter signal IDA_PARAM from the sequencer 520.

In the period (6) to (8), the request arbiter circuit 530 receives the read data (RD_IO0, RD_IO1) from the serial ROM 200 as the read data signal ACC_RD via the protocol generation circuit 540. The request arbiter circuit 530 detects that the read data signal ACC_RD is valid data by the read data valid signal ACC_RDRY asserted to the logical value 1.

The request arbiter circuit 530 outputs the received read data (RD_IO0, RD_IO1) to the sequencer 520 as a read data signal IDA_RD during the period (7) to (9). The request arbiter circuit 530 asserts the read data valid signal IDA_RDRDY to the logical value 1 while the valid read data signal IDA_RD is being output. The read data (RD_IO0, RD_IO1) is stored in the indirect data buffer 527 of the sequencer 520.

In (9), the request arbiter circuit 530 detects the negate (logical value 0) of the busy signal ACC_BUSY from the protocol generation circuit 540. Further, the request arbiter circuit 530 detects that both the request issue signal MMA_RQ and the request issue signal IDA_RQ are asserted at this timing. Since the request arbitration circuit 530 preferentially arbitrates the indirect access request, the request permission signal IDA_ACK is asserted in (9).

Further, the request arbiter circuit 530 outputs the content (IDP_P1) of the parameter signal IDA_PARAM received in (3) to the protocol generation circuit 540 as the parameter signal ACC_PARAM, and at the same time asserts the request issuance signal ACC_CHECK. In response to this, in (10), the request arbiter circuit 530 receives the request permission signal ACC_ACK and the busy signal ACC_BUSY asserted from the protocol generation circuit 540.

Further, in (10), the request arbiter circuit 530 outputs the shift request signal MMA_NEXT asserted to the logical value 1 to the sequencer 520, and shifts the next parameter of the memory-mapped access control register 523 to the current value. Demand that. This is because the shift enable signal MMA_SHIFT received from the sequencer 520 is asserted to the logical value 1 and the indirect access request is permitted. The shift enable signal MMA_SHIFT of the logical value 1 indicates a request to copy the contents for the next of the memory-mapped control register 523 for the current based on the access execution of the serial ROM 200 by the indirect access request.

Next, in (13), the request arbiter circuit 530 detects the negate of the busy signal ACC_BUSY from the protocol generation circuit 540. Further, the request arbiter circuit 530 detects the assertion of only the request issuance signal MMA_RQ from the sequencer 520. As a result, the request arbiter circuit 530 outputs the request permission signal MMA_ACK asserted to the logical value 1 to the protocol generation circuit 540.

Further, the request arbiter circuit 530 outputs the content (MMA_P1) of the parameter signal IDA_PARAM to the protocol generation circuit 540 as the parameter signal ACC_PARAM, and at the same time asserts the request issuance signal ACC_CHECK. In response to this, in (15), the request arbiter circuit 530 receives the request permission signal ACC_ACK and the busy signal ACC_BUSY asserted from the protocol generation circuit 540. Then, the request arbiter circuit 530 receives the read data DR_M10 and RD_M11 from the serial ROM 200 via the protocol generation circuit 540 in (16) to (18).

FIG. 12 is a flow chart showing an example of an operation in which the SPI controller 500 of FIG. 1 switches the serial ROM 200 from the single mode to the XIP mode. FIG. 12 shows an example of a control method of the SPI controller 500. The switching to the XIP mode is executed by the sequencer 520 based on the parameter writing to the control registers 522 and 525 in the sequencer 520 by the CPU 300.

First, in step S10, a parameter for reading data from the serial ROM 200 in the XIP mode is set for the next of the control register 523 for memory-mapped access based on the write instruction from the CPU 300 (Fast Read Quad). I / O (XIP)). The parameters set for the next of control register 523 for memory-mapped access are used in the first instruction executed after enter into XIP mode.

Next, in step S12, a parameter for entering the XIP mode is set for the current of the control register 526 for indirect access based on the write instruction from the CPU 300 (Fast Read Quad I / O (XIP). transition)). For example, the enter to the XIP mode is performed together with the access to read the read data from the serial ROM 200 in the quad mode.

Next, in step S14, "1" is set in the shift enable register (memory-mapped) based on the write instruction from the CPU 300. Next, in step S16, "1" is set in the request issuance register for indirect access based on the write instruction from the CPU 300.

Next, in step S18, the sequencer 520 issues a read access request for switching to the XIP mode to the serial ROM 200 based on step S16. Then, the sequencer 520 stores the read data output from the serial ROM 200 in the data register based on the read access request for switching to the XIP mode, and resets the request issuing register for indirect access to "0". This completes the operation of switching to the XIP mode. After the operation shown in FIG. 12 is completed, the read operation in the XIP mode shown in FIG. 4 is repeatedly executed, so that the read efficiency of the program from the serial ROM 200 is improved.

FIG. 13 is an explanatory diagram showing an example of setting a memory-mapped current control register when the flow of FIG. 12 is executed. The memory-mapped current control register shown in FIG. 13 is set as a default value. FIG. 13 shows the parameters set in the memory-mapped current control register in order to execute the read operation (normal read) in the single mode in parallel with the parameter setting in the various registers according to the flow of FIG. An example of is shown. The state of the register shown in FIG. 13 is set by the sequencer 520 in response to a read access request from the CPU 300 when the serial ROM 200 is set to the single mode.

In the read operation executed for the serial ROM 200 in the state shown in FIG. 13, the sequencer 520 outputs an instruction and an address to the serial ROM 200 according to the information set in the registers of Phases 0 to 2, and reads the read data from the serial ROM 200. Receive. Then, the read operation shown in FIG. 2 is executed. In the memory-mapped access, the sequencer 520 outputs the data received from the serial ROM 200 and stored in the data buffer 524 to the CPU 300 as a response to the read access request.

FIG. 14 is an explanatory diagram showing an example of setting a memory-mapped next control register when the flow of FIG. 12 is executed. FIG. 14 shows the next state of the control register 523 for memory-mapped access after executing step S10 of FIG. An example of a read operation performed on the serial ROM 200 in the state shown in FIG. 14 is shown in FIG.

FIG. 15 is an explanatory diagram showing a setting example of a current control register for indirect when the flow of FIG. 12 is executed. FIG. 15 shows the current state of the control register 526 for indirect access after the execution of step S12 in FIG. 12, and is set when the serial ROM 200 transitions from the single mode to the XIP mode.

FIG. 16 is an explanatory diagram showing a setting example of the next control register for indirect when the flow of FIG. 12 is executed. For example, the next control register 526 for indirect access is not used when switching from the single mode to the XIP mode. In this case, the sequencer 520 maintains or sets the parameter of each register to "0" (invalid) or "Don't Care".

FIG. 17 is a timing diagram showing an example of the operation of the SPI controller 500 of FIG. 5 for transitioning the serial ROM 200 from the single mode to the XIP mode. A detailed description of the same operation as in FIG. 2 will be omitted. The operations shown in FIGS. 17 to 20 show an example of a control method of the SPI controller 500.

The operation shown in FIG. 17 is executed under the control of the sequencer 520 based on the parameter settings shown in FIG. First, in (1), the reset signal reset_n is released to the logical value 1, and the SPI controller 500 starts operation. After that, the reset signal reset_n is maintained at the high level "H". The CPU 300 issues a memory-mapped access request (read request) in order to fetch an instruction for its own operation, as shown in CPU access. Immediately after the reset signal reset_n is released, the serial ROM 200 is set to the single mode.

Next, in (2), the status of the request arbiter circuit 530 is low level "L". Therefore, the SPI controller 500 executes the read operation in the single mode by using the set value of the memory-mapped control register 523 in response to the memory-mapped access request from the CPU 300. Here, the low level "L" of the request arbitration circuit status indicating the status of the request arbiter circuit 530 indicates a state in which an indirect access request has not occurred and the memory-mapped access request is not prohibited.

The read operation of the serial ROM 200 in the single mode in response to the memory-mapped access request is executed in (2) to (3), the read data RDT read from the serial ROM 200 is returned to the CPU 300, and the read operation is completed. do.

The CPU 300 issues a memory-mapped access request (read) in (4) for subsequent instruction fetch. The SPI controller 500 permits the memory-mapped access request in (5), and in (5) to (6), the read operation in the single mode is executed in the same manner as in (2) to (3).

Next, in FIG. 18, the CPU 300 issues an access request for setting the next of the memory-mapped control register 523. Various parameters for memory-mapped access read from the serial ROM 200 based on the access request are set in (7) for the next of the control register 523. The parameter for the memory-mapped next is a memory access request (read; Fast Read Quad I / O (XIP)) in the XIP mode that is executed immediately after switching to the XIP mode.

In this embodiment, the current version of the memory-mapped control register 523 is used to store the XIP mode instruction in advance for the next while executing the access (program fetch) of the serial ROM 200 in the single mode. be able to. Further, the transfer of the instruction from the next register to the current register is output from the current instruction of the indirect control register 526 when the shift enable register (memory-mapped) is set. It is executed based on. As a result, as shown in FIGS. 18 and 19, after switching the serial ROM 200 to the XIP mode using the current of the control register 526 for indirect access, the instruction of the XIP mode can be executed quickly.

In (7), the CPU 300 issues an access request for setting the current of the control register 526 for indirect. Various parameters for indirect access read from the serial ROM 200 based on the access request are set for the current of the control register 526 in (8). The indirect current parameter is a memory access request (read; Fast Read Quad I / O (Enter XIP mode)) for entering the XIP mode.

In this embodiment, the control register 523 for memory-mapped access and the control register 526 for indirect access are provided independently of each other. As a result, the instruction for the XIP mode can be stored in the control register 526 in advance before switching to the XIP mode using the control register 526. In other words, the instruction for switching the serial ROM 200 to the XIP mode and the instruction for the XIP mode to be executed after the switching can be held at the same time.

After this, the CPU 300 issues a memory-mapped access request (read) for subsequent instruction fetch. The SPI controller 500 permits the memory-mapped access request in (9), and in (9) to (10), the read operation in the single mode is executed as in FIG. In (10), the CPU 300 issues a request to set the shift enable register (memory-mapped) to "1", and the shift enable register (memory-mapped) is set to "1".

In (11) of FIG. 19, the CPU 300 issues an access request for setting "1" in the request issuance register for indirect. The request issuance register for indirect is set to "1" in (12). In response to "1" of the request issuance register for indirect, the sequencer 520 outputs a parameter including an instruction held for the current of the control register 526 to the request arbiter circuit 530. Request issuance registers are provided for indirect access and memory-mapped access, respectively. As a result, the access request held for each of the control registers 526 and 523 can be issued to the serial ROM 200 via the request arbiter circuit 530 at an arbitrary position of the program executed by the CPU 300.

The request arbiter circuit 530 prohibits the selection of the memory-mapped access instruction based on the reception of the instruction for indirect access, and sets the request arbiter circuit status to the high level "H". In other words, the request arbitration circuit 530 prohibits the output of the memory-mapped access instruction to the serial ROM 200 when the reception of the instruction for indirect access and the reception of the instruction for memory-mapped access conflict with each other. ..

Here, the high level "H" request arbitration circuit status indicates a state in which an indirect access request has occurred and the memory-mapped access request is prohibited. The request arbiter circuit status is internal information of the request arbiter circuit 530, but may be output to the outside of the request arbiter circuit 530 as a suppression signal indicating suppression of selection of a memory-mapped access instruction.

By the arbitration control of the request arbitration circuit 530, for example, it is possible to prevent the XIP mode instruction held in the control register 523 from being executed before the XIP mode switching instruction held in the control register 526. .. Therefore, when switching the operation mode of the serial ROM 200, it is possible to prevent the operation mode of the serial ROM 200 from being inconsistent with the operation mode of the instruction supplied to the serial ROM 200, and it is possible to suppress the malfunction of the serial ROM 200. can. As a result, the malfunction of the system SYS can be suppressed.

The request arbitration circuit 530 outputs an indirect access request (instruction to enter the XIP mode) selected by arbitration to the serial ROM 200, and notifies the sequencer 520 of the issuance of the indirect access request. The shift enable register (memory-mapped) is set to "1" in (10) of FIG. Therefore, the sequencer 520 copies the contents of the memory-mapped control register (for next) to the memory-mapped control register (for current) in (13) based on the notification of the issuance of the indirect access request. do.

By providing a shift enable register (memory-mapped), the memory-mapped access request issued thereafter in response to the issuance of the indirect access request is set for the current of the control register 523 for the memory-mapped access. can do. Therefore, for example, after switching the XIP mode in the indirect access request, the XIP mode instruction in the memory-mapped access request can be executed.

On the other hand, it is not known where the XIP mode switching timing in the indirect access request is inserted between a plurality of consecutive memory-mapped access requests due to the arbitration order by the request arbitration circuit 530, as shown below. Such a problem occurs. For example, if an XIP mode switching instruction is inserted between consecutive memory-mapped access requests in single mode, the single mode access request after switching to XIP mode is not normally executed. Further, when the XIP mode switching instruction is inserted between the continuous memory-mapped access requests in the XIP mode, the access request in the XIP mode before switching to the XIP mode is not normally executed.

In (14) to (15), the Fast Read Quad I / O (Enter XIP mode) access for entering the serial ROM 200 into the XIP mode is executed, and the operation mode of the serial ROM 200 is switched from the single mode to the XIP mode. The request arbiter circuit 530 returns the request arbiter circuit status to the low level "L" when the access to the serial ROM 200 by the indirect access request is completed (16). As a result, the prohibited state of outputting the memory-mapped access request to the serial ROM 200 is released. By prohibiting the selection of the memory-mapped access request until the access to the serial ROM 200 by the indirect access request that triggered the output prohibition of the memory-mapped access request is completed, the malfunction of the SPI controller 500 is suppressed. Can be done. Further, after switching to the XIP mode, the waiting time until the serial ROM 200 is accessed by the memory-mapped access request can be minimized.

In FIG. 20, the CPU 300 issues a memory-mapped access request (read) in (17) for subsequent instruction fetch. The SPI controller 500 permits this memory-mapped access request in (18). At this point, the parameters for Fast Read Quad I / O (XIP mode) are set in the memory-mapped control register (for current). Therefore, in (18) to (19), the SPI controller 500 executes the read operation of the serial ROM 200 in the XIP mode without issuing an instruction code. Then, the read data RDT read from the serial ROM 200 is returned to the CPU 300, and the read operation in the XIP mode is completed.

Before the reset signal reset_n in FIG. 17 is released, the instruction for switching the XIP mode is stored in advance in the control register 526 for indirect access, and the instruction for the XIP mode is stored in the control register 523 for memory-mapped access. It may be stored in advance. Then, "1" may be set in advance in the request issuance register for indirect before the reset signal reset_n in FIG. 17 is released. In this case, the CPU 300 first issues a request to set the shift enable register (memory-mapped) to "1" after the reset signal register_n is released, thereby executing the switch to the XIP mode at the beginning of the program. be able to. As a result, the execution efficiency of the instructions can be improved and the performance of the system SYS can be improved as compared with the case where a plurality of single mode instructions are executed after the reset signal reset_n is released.

As described above, in this embodiment, when the instruction held in the control register 526 for indirect access is output to the serial ROM 200, the output of the instruction held in the control register 523 for memory-mapped access to the serial ROM 200 is prohibited. Thereby, for example, when the instruction for switching the operation mode of the serial ROM 200 is output from the control register 526, it is possible to prevent the instruction of the operation mode after the switching from being output to the serial ROM 200 before the operation mode is switched. can.

Further, it is possible to prevent the instruction of the operation mode different from the operation mode to be switched from being output to the serial ROM 200 after the operation mode is switched. As a result, the malfunction of the serial ROM 200 can be suppressed, and the malfunction of the system SYS can be suppressed. That is, the operation mode of the serial ROM 200 can be switched while continuing the access to the serial ROM 200.

Since the control register 523 for memory-mapped access and the control register 526 for indirect access are provided independently of each other, the instruction for XIP mode is stored in advance in the control register 526 before switching to the XIP mode. Can be kept. In other words, the instruction for switching the serial ROM 200 to the XIP mode and the instruction for the XIP mode to be executed after the switching can be held at the same time.

Request issuance registers are provided for indirect access and memory-mapped access, respectively. As a result, the access request held for each of the control registers 526 and 523 can be issued to the serial ROM 200 via the request arbiter circuit 530 at an arbitrary position of the program executed by the CPU 300. In addition, it is possible to flexibly support new devices.

By prohibiting the selection of the memory-mapped access request until the access to the serial ROM 200 by the indirect access request that triggered the output prohibition of the memory-mapped access request is completed, the malfunction of the SPI controller 500 is suppressed. Can be done. Further, after switching to the XIP mode, the waiting time until the serial ROM 200 is accessed by the memory-mapped access request can be minimized.

The sequencer 520 has, in the memory-mapped control register 523, a current one for holding an instruction issued by the serial ROM 200 and a next one for holding an instruction to be issued next for the current one. As a result, the XIP mode instruction can be stored in advance for the next while executing the access (program fetch) of the serial ROM 200 in the single mode by using the current one.

Further, the transfer of the instruction from the next register to the current register is output from the current instruction of the indirect control register 526 when the shift enable register (memory-mapped) is set. It is executed based on. As a result, after switching the serial ROM 200 to the XIP mode using the current of the control register 526 for indirect access, the instruction of the XIP mode can be executed quickly.

(Second Embodiment)
FIG. 21 is a block diagram showing an example of the SPI controller according to the second embodiment of the present invention. The same elements as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. The SPI controller 500A shown in FIG. 21 has a sequencer 520A instead of the sequencer 520 of the SPI controller 500 of FIG.

The sequencer 520A has a common control register 528A instead of the common control register 528 of the sequencer 520 of FIG. The common control register 528A adds a parameter read control register 529A to the common control register 528. The parameter read control register 529A is an example of the parameter read request flag. The parameter read control register 529A has a flag and a buffer that trigger an operation of reading a parameter from the serial ROM 200 and setting it in a register in the SPI controller 500A. Data read from the serial ROM 200 is temporarily stored in the buffer when the flag is set.

Other configurations of the SPI controller 500A are the same as the configuration of the SPI controller 500 of FIG. The configuration of the system SYS including the SPI controller 500A is the same as that in FIG.

FIG. 22 is an explanatory diagram showing an example of the setting contents of the register provided in the sequencer 520A of FIG. 21. In FIG. 22, the setting contents of the parameter read control register 529A of FIG. 21 are added to the setting contents of FIG. When the parameter read control register 529A is "1", the SPI controller 500A stores the parameters read from the serial ROM 200 in the control register group 522 for memory-mapped access and the control register group 525 for indirect access. For example, the parameter read control register 529A is set to "1" when the reset signal register_n is released (when the logical value changes from 0 to 1). The SPI controller 500 stores the various parameters read from the serial ROM 200 in the register, and then resets the parameter read control register 529A to "0".

FIG. 23 is a timing diagram showing an example of the operation of the SPI controller 500A of FIG. 21 for transitioning the serial ROM 200 from the single mode to the instruction omission mode. Detailed description of the same operation as in FIGS. 17 to 20 will be omitted. The operations shown in FIGS. 23 to 25 show an example of a control method of the SPI controller 500A.

In this embodiment, the logical value 1 is set in the flag of the parameter read control register 529A before the operation of FIG. 23. Further, for the current of the control register 526 for indirect access, a parameter for reading 128 bytes of data from the final address (for example, FFFF80h) of the serial ROM 200 in a single mode is stored. In FIGS. 23 to 25, the set value of the parameter read control register 529A is shown as a logical value of the parameter read request signal PREAdreq (high level “H” in FIG. 23).

In (1) of FIG. 23, the reset signal reset_n is released to the logical value 1, and the SPI controller 500 starts operation. When the flag of the parameter read control register 529A is set to the logical value 1, the CPU 300 fetches an instruction for its own operation (memory-mapped read) as shown in the CPU access, so that the memory-mapped access Issue a request (lead request). However, since the request arbiter circuit status is set to the high level "H", the access request from the memory-mapped side (that is, the CPU 300) is prohibited by the request arbiter circuit 530.

In (2), the SPI controller 500A executes a read operation of reading 128 bytes of data from the final address of the serial ROM 200 in accordance with a parameter read instruction held for the current of the control register 526 for indirect access. .. The read operation is performed in single mode. For example, the address where the read data is stored and the number of bytes of the read data are stored in the operand of the instruction executed by the CPU 300. The SPI controller 500A sequentially stores the data read from the serial ROM 200 in the buffer of the parameter read control register 529A.

When the read operation is completed (3), the SPI controller 500A transfers the data stored in the buffer to the next control register 523 for memory-mapped access and the current control register 526 for indirect access. .. Further, the SPI controller 500A sets the request issuance register of the control register group 525 for indirect access to "1".

As shown in FIG. 23, in this embodiment, the data stored in the serial ROM 200 when the SPI controller 500A is started can be read as an instruction for a memory-mapped access request and an instruction for an indirect access request. .. Then, the parameters for Fast Read Quad I / O (XIP) are set for the next of the control register 523 for memory-mapped access. The parameters for Fast Read Quad I / O (Enter XIP mode) are set for the current of the control register 526 for indirect access.

Therefore, the parameters can be stored in the control registers 523 and 526 without the CPU 300 executing the instructions for storing the parameters in the control registers 523 and 526, respectively. As a result, for example, switching from the single mode to the XIP mode can be efficiently executed. Since the data stored in the serial ROM 200 can be set in the control registers 523 and 526 as parameters, it is possible to flexibly deal with new devices.

Note that FIG. 23 shows the operation when the read request signal PREAdreq is set to the logical value 1 when the reset signal reset_n is released, but the read request signal PREAdreq is set to the logical value 1 by the write access by the CPU 300. You may. In this case, the memory access by the CPU 300 is executed by using the current use of the memory-mapped access control register 523 during the period when the read request signal PREAdreq has a logical value of 0. Then, based on the change of the read request signal PREAdreq to the logical value 1, the operation from (2) of FIG. 23 is started.

In FIG. 24 (4), when the request issuance register of the control register group 525 for indirect access is set to "1", the request arbiter circuit status is maintained at the high level "H". Therefore, the SPI controller 500A starts the Fast Read Quad I / O (Enter XIP mode) access according to the current parameter of the control register 526 for indirect access. By executing the access of Fast Read Quad I / O (Enter XIP mode), the serial ROM 200 transitions from the single mode to the XIP mode.

When the Fast Read Quad I / O (Enter XIP mode) access is completed in (5), the SPI controller 500A changes the request arbiter circuit status to the low level "L" and permits access from the memory-mapped side. .. Further, the SPI controller 500A changes the parameter read request signal PREAdreq to the low level "L". At this point, the Fast Read Quad I / O (for XIP) has been transferred from the next to the current of the control register 523 for the memory-mapped access.

In FIG. 25 (6), the Fast Read Quad I / O (for XIP) access is started according to the current parameter of the memory-mapped access control register 523. By executing the access of Fast Read Quad I / O (for XIP), the read data is output from the serial ROM 200, and the read operation in the XIP mode is completed in (7).

As described above, even in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, the parameters can be stored in the control registers 523 and 526 without the CPU 300 executing the instructions for storing the parameters in the control registers 523 and 526, respectively. As a result, for example, switching from the single mode to the XIP mode can be efficiently executed. Since the data stored in the serial ROM 200 can be set in the control registers 523 and 526 as parameters, it is possible to flexibly deal with new devices.

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. With respect to these points, the gist of the present invention can be changed without impairing the gist of the present invention, and can be appropriately determined according to the application form thereof.

100 SoC
200 serial ROM
300 CPU
400 Decoder 500, 500A SPI controller 510 CPU interface circuit 520, 520A Sequencer 522 Control register group 523 Control register 524 Data buffer 525 Control register group 526 Control register 527 Data buffer 528, 528A Common control register 530 Request arbitration circuit 540 Protocol generation circuit 600 RAM
700 I / O interface unit 800 Network interface unit AD address CLK clock signal DMY dummy cycle INS command IO (IO0-IO3) data terminal MD mode RDT read data reset_n reset signal SYSTEM

JP-A-2017-045311

Claims (8)

An interface circuit that controls access to a serial memory that can switch between a serial mode that transfers data using a single signal line and a parallel mode that transfers data using multiple signal lines.
A first instruction holding unit that holds an instruction for accessing the serial memory output from a processor that executes a program held in the serial memory, and outputs an instruction held in the first instruction holding unit. Interface part and
A second interface unit that converts a memory access request from the processor into an instruction that can be accepted by the serial memory and outputs the converted instruction.
When the instruction output by the first interface unit or the second interface unit is output to the serial memory, and the reception of the instruction from the first interface unit and the reception of the instruction from the second interface unit conflict with each other. An arbitration unit that prohibits the output of instructions received from the second interface unit, and
An interface circuit characterized by having. The interface circuit according to claim 1, wherein the instruction held in the first instruction holding unit is an instruction for switching the serial memory from the serial mode to the parallel mode. The first interface unit is
Has a request issuance flag set by the processor
The interface circuit according to claim 1 or 2, wherein an instruction held in the first instruction holding unit is output in response to the set of the request issuing flags. The first interface unit is
It has a request issuance flag that is set when the interface circuit is started.
The interface circuit according to claim 1 or 2, wherein when the request issuance flag is set, an instruction held in advance is output to the first instruction holding unit. The arbitration unit, which prohibits the output of the instruction received from the second interface unit, is used from the second interface unit until the operation of the serial memory by the instruction from the first interface unit output to the serial memory is completed. The interface circuit according to claim 3 or 4, wherein the output of the received instruction is prohibited. Has a parameter read request flag
When the parameter read request flag is set at the time of starting the interface circuit, the first interface unit receives data read from the serial memory according to the execution of the instruction stored in the first instruction holding unit. The interface circuit according to any one of claims 1 to 5, wherein the command is stored in the first instruction holding unit as an instruction for accessing the serial memory. The second interface unit is
A second instruction holding unit that holds the converted instruction, and
It has a third instruction holding unit to which the converted instruction is transferred from the second instruction holding unit.
The first interface unit is set when the converted instruction is transferred from the second instruction holding unit to the third instruction holding unit in response to the output of the instruction held in the first instruction holding unit. The interface circuit according to any one of claims 1 to 6, wherein the interface circuit has a shift flag. A first interface unit and a second interface unit that control access to a serial memory that can switch between a serial mode in which data is transferred using one signal line and a parallel mode in which data is transferred using multiple signal lines. It is a control method of an interface circuit including an interface unit and an arbitration unit.
The first interface unit outputs the instruction held in the first instruction holding unit that holds the instruction for accessing the serial memory output from the processor that executes the program held in the serial memory.
The second interface unit converts the memory access request from the processor into an instruction that can be accepted by the serial memory, and outputs the converted instruction.
The arbitration unit outputs a command output by the first interface unit or the second interface unit to the serial memory, and receives an instruction from the first interface unit and a command from the second interface unit. A method for controlling an interface circuit, which prohibits the output of an instruction received from the second interface unit when the two interfaces conflict with each other.

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