JP2007108882A - Memory controller, memory-controlling method, and information processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To elimite the need for read-return buffers to be provided in a plurality of slaves when a master simultaneously access the slaves inside a system LSI. <P>SOLUTION: A memory controller receives an access request to a memory from a bus master and accesses a memory. When data read out from the memory are transmitted to the bus master when the read access request to the memory from the bus master is made, a command issuing control part 606' determines, based on command-issue timing information, whether the transmission collides with reading responses to the bus master from other slaves. When determined that the collision occurs, the command issuing control part 606' delays access to the memory. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller that controls access from a bus master to a memory, a memory control method therefor, and an information processing apparatus including the memory controller.

  Due to advances in semiconductor technology and microprocessor technology, the application fields of embedded systems consisting of processors and memories are steadily expanding. For example, embedded systems are used in home appliances, AV equipment, OA equipment, automobiles, and communication equipment. It has been broken. What is characteristic in recent years is that the so-called system LSI, in which the controller function of the embedded device is integrated into one LSI, is becoming common as a result of the increased integration of the LSI. By using such a system LSI, it is possible to realize area saving, cost reduction, low power consumption, and high reliability.

  FIG. 1 is a diagram illustrating an example of a configuration that implements an embedded system of OA equipment using a system LSI disclosed in Patent Document 1. In FIG. In FIG. 1, reference numeral 110 denotes an embedded system board on which a system LSI 100, a memory 101, and various I / O interfaces are mounted. More specifically, the system LSI 100 is a single-chip scanning / printing engine including a processor core, a processor peripheral controller, a memory controller, a scanner controller, a printer controller, a PCI interface, a USB device interface, and the like.

  Examples of the I / O interface provided in the embedded substrate 110 include a scanner I / F 131, a FAX I / F 132, a USB I / F 134, and a printer I / F 133. Each is connected to a scanner 121, FAX 122, PC 124, and printer 123 to constitute the entire system. Further, the system LSI 100 is provided with a PCI bus I / F 136. By using this, a hard disk (HDD) 125 connected to the IDE bus 135 via the PCI-IDE bridge 102 can be used.

  FIG. 2 is a block diagram illustrating the system LSI 100 in more detail.

  The processor 201 can contain a maximum of 32 Kbytes of instruction, 16 Kbytes of data each, a total of 32 Kbytes of cache memory, FPU (floating point arithmetic unit), MMU (memory management unit), user-definable coprocessor, etc. is there. Further, since it has the PCI bus interface 232, it can be used with a computer system having a PCI bus slot. In addition to the PCI satellite configuration, a PCI bus configuration can be issued in a PCI host bus bridge configuration. Furthermore, by combining with an inexpensive PCI peripheral device, it can be used as a main engine of a multifunction peripheral (multifunctional peripheral device). Furthermore, a rendering engine having a PCI bus interface and a compression / decompression engine can be combined.

  There are two independent buses, an IO bus (B bus) 221 for connecting a general-purpose IO core inside the chip, and a graphic bus (G bus) 220 optimized for image data transfer. Then, by connecting these buses to the memory 204 and the processor 201 via a system bus bridge 203 that is a crossbar switch, high-speed data transfer that is essential for simultaneous operation in a multi-function system is realized. . In addition, a memory controller 202 that supports a synchronous DRAM (SDRAM) having high cost performance with respect to continuous data string access represented by image data is incorporated. In addition, a scanner controller 205, a printer controller 206, a PCI controller 207, a USB controller 208, a UART 209, a MISC module 210 including a timer / GPIO function, a LAN controller 211, and the like are incorporated. Reference numerals 230 to 236 denote 205/211 I / O interfaces, which are the same as the interfaces having the same names in FIG.

  Here, the memory controller 202 supports access to the DDR-SDRAM with an open page policy. In this open page policy, once a certain page is opened (RAS command), it is not immediately closed (precharged) even if the memory access by the subsequent CAS command is completed. If the subsequent memory access is an access to the same page (page hit), the CAS device can be accessed continuously without issuing the RAS command. At this time, the bandwidth supplied by the memory device is Become the maximum.

  On the other hand, if the subsequent memory access is for another page (RAS address) in the same bank, a precharge command is issued to close the page, and then a RAS command is issued to open the page. Must. In such a situation, the bandwidth that the memory device can supply decreases.

  It is known that if the closed page policy is adopted and the page is closed (precharged) immediately after the memory access is completed, a higher bandwidth than the open page policy can be supplied for an access pattern in which page misses frequently occur. ing. However, the access pattern with many page hits is disadvantageous compared to the open page policy.

  Now consider a typical sequence of complex operations. A so-called copying operation in which the scanned original image is printed by the printer 123 while the original is scanned by the scanner 121 will be described as an example. Image data obtained by scanning the document is sent from the scanner 121 to the scanner controller 205 built in the system LSI 100 via the scanner interface 230 (131). The scanner controller 205 stores the received image data in the memory 204 by DMA. Next, the printer controller 206 reads the image data from the memory 204 by DMA, and sends it to the printer 123 via the printer interface 231 for printing.

  At this time, PDL data is further transmitted from the PC 124 via the USB interface 233 (134). This PDL data is received by the USB device controller 208 and temporarily stored in the memory 204 by DMA. Thereafter, the image image interpreted and developed by the processor 201 of the system LSI 100 is stored in the memory 204 again. Finally, the data is read from the memory 204 by the printer controller 206, sent to the printer 123 via the printer interface 231 and printed.

  FIG. 3 is a diagram for explaining the physical address space of the memory handled by the processor 201 at this time.

  Actually, the processor 201 is compatible with MIPS-R4000, and the software of the processor 201 operates using a virtual address. The processor 201 always operates in the kernel mode, and the physical addresses “0x0000_0000” to “0x1fff_ffff” are the virtual addresses “0x8000_0000” to “0x9fff_ffff” (kseg0: cached) and “0xa000_0000” to “0xbfff_ffff” (kseg1 : uncached).

  In this conventional example, the capacity of the memory 204 is 32 MB, and one 256 Mbit SDRAM of 16 bit × 4 bank × 4 M word configuration is mounted. Therefore, the physical address space that can be used as the RAM is from “0x0000_0000” to “0x01ff_ffff”.

  When composite operation is performed, software operating on the processor 201 manages the buffer area of the memory 204 used by each hardware. Normally, a memory area is allocated in the Heap area using a memory allocation function (system function provided by the OS: malloc, etc.) as in the case of dynamically allocating a memory area by software. In the case of this example, the buffer areas that the scanner controller 205 writes by DMA and the printer controller 206 reads by DMA are the same. If there is only one buffer area, the printer controller 206 reads the address written by the scanner controller 205 later. However, since the reading speed from the scanner 121 is different from the printing speed of the printer 123, there is a possibility that the reading address may overtake the writing address in the middle unless there is a mechanism for synchronization between the scanner controller 205 and the printer controller 206. is there.

  To avoid this, it is common to have double buffers. In other words, while the scanner controller 205 is writing to one buffer area by DMA, the printer controller 206 reads from the other buffer area by DMA. When both DMA transfers are completed in this way, the buffers to be used are replaced and the next DMA is started. For example, when 1 MB of data is continuously sent from the scanner 121 to the scanner controller 205, the memory allocation function is first called with an argument of 1 MB. The returned address is converted into a physical address because it is a virtual address, and is set as the DMA start address of the scanner controller 205. Here, addresses “0x0080_0000” to “0x008f_ffff” are secured, and the address “0x800_0000” which is the head address is set as the DMA start address. Next, when data arrives, the scanner controller 205 stores data continuously from the start address by DMA. When this DMA is completed, the address “0x0080_0000” is set in the printer controller 206 as the DMA start address. Thereafter, when the start of DMA is instructed by software, the data is sequentially read from the start address set in accordance with the signal of the printer interface 231, and the data is transferred to the printer 123 via the printer interface 231. At the same time, the next DMA is set for the scanner controller 205. Then, the memory allocation function is called again with an argument of 1 MB, and when addresses “0x0090_0000” to “0x009f_ffff” are secured, the address “0x0090_0000” which is the head address is set as the DMA start address. As a result, when data arrives from the scanner interface 230, the scanner controller 205 stores data continuously from the start address by DMA. In this manner, the DMA operation is repeatedly performed between the scanner controller 205 and the printer controller 206 while alternately using the two areas “0x0080_0000” to “0x008f_ffff” and “0x0090_0000” to “0x009f_ffff”.

  On the other hand, in the case of the USB controller 208, addresses “0x00b0_0000” to “0x00bf_ffff” are secured, and the address “0x00b0_0000” that is the head address is set as the DMA start address. When PDL data is sent from the PC (USB host) 124, the USB controller 208 stores data continuously from the start address by DMA. When all transfers are completed, the software is notified by an interrupt, and then the PDL data is interpreted by the software and print image data is generated. The finally generated print image data is stored in a newly secured buffer area. In this case, the memory allocation function is called again, and 3 MB areas “0x00c0_0000” to “0x00ef_ffff” are secured. Next, the printer controller 206 is activated with the address “0x00c0_0000” as the start address of the DMA. The DMA transfer of the printer controller 206 at this time is performed exclusively with the DMA transfer of the printer controller 206 during the above-described scanner printer operation. As described above, when access to the scanner 121, the printer 123, and the HDD 125 occurs simultaneously, a plurality of pieces of hardware within the system LSI 100 are simultaneously performing DMA access to the memory 204.

  In this case, the probability of a page hit in the memory device is lower than when one piece of hardware accesses alone. This is because even if the memory 204 access from individual hardware is continuous, access to the memory from the memory controller 202 is not continuous by a plurality of hardware accessing the memory 204 alternately. is there. As hardware that simultaneously accesses the memory 204 increases in this way, the access pattern to the memory device approaches random access. In random access, a page miss occurs almost every time access is performed, and therefore the memory controller 202 must issue a page close (precharge) and page open (RAS) command. As a result, the bandwidth that can be supplied by the memory is greatly reduced compared to the peak time (when the page hits).

  The buffer areas assigned to the scanner controller 205, printer controller 206, and USB controller are all in the same bank and all on different pages. Accordingly, when each DMA transfer is alternately performed at the same time, each DMA transfer always causes a page miss in the memory. For this reason, the system performance is lowered due to the reduction in the memory bandwidth, and print data cannot be supplied at a speed required by the printer 123, which may limit the printing speed.

  In the above example, the relationship between the physical address (Addr [31: 0]) and the bank address / row address / column address of the memory 204 is continuously assigned in this order from the upper bits as shown in FIG. Occurs when

  In order to solve this, as shown in FIG. 5, a method is adopted in which the relationship between the physical address and the bank address / row address / column address of the memory 204 is fixedly replaced. If the relationship between the physical address and the bank address / row address / column address of the memory 204 is assigned as shown in FIG. 5, when the DMA access is performed from the bus master to the continuous physical address, the bank is always changed at the page boundary. At this time, a page miss occurs as in the case of FIG. However, as described above, in a state where a plurality of bus masters simultaneously cause DMA access, the banks accessed by each bus master are switched randomly. Since each bank of the memory 204 can be accessed independently, a page miss occurs in one bank, and even when a page close or open process is performed, another bank can be accessed, so the page miss overhead is hidden. It becomes possible to do. However, if the memory controller 202 processes the memory access requests from the respective bus masters in the order in which they are received, if the access requests for the same bank are consecutive, subsequent accesses cannot be processed until the previous access processing is completed. As a result, the overhead when a page miss occurs cannot be concealed. This occurs with a probability of 1/4 when the number of banks is four, and has a large effect on performance in a situation where there are many page misses.

  This situation can be improved if the memory controller has a function of accessing the memory device in an out-of-order manner.

  FIG. 6 is a block diagram showing an example of the configuration of a conventional memory controller.

  In FIG. 6, reference numeral 601 denotes a bus interface, which is connected to the system bus 610 and receives a read / write request from a bus master. More specifically, a command signal such as an address bus signal and a read / write signal is received, and the address information and the read / write information are stored in the command queue 602 as a set. Further, when data is written, the data driven by the data bus signal is stored in the write data buffer 603. When reading data, the data held in the read data buffer 604 is driven to the data bus signal. The memory control circuit 605 reads a necessary command from the command queue 602, and drives the CS, RAS, CAS, and WE signals to the memory device according to the command at an appropriate timing. In the case of data writing, the write data corresponding to the write command is read from the write data buffer 604, and a write operation is performed on the memory device. In the case of reading data, the data read from the memory device is stored in the read data buffer 604. This read buffer is necessary for the reason described later when a plurality of memory controllers are provided in the system LSI.

  The command queue 602 and the write data buffer 603 are configured to be able to read the stored information in any order regardless of the order in which the bus interface 601 queues. The command issuance control unit 606 uses the fact that the four banks of the memory 204 can operate independently, and even when one or more banks are being accessed, there are banks that are not being accessed. A command for the bank is selected from the command queue 602. If it exists, the command is selected from the command queue 602 and transferred to the memory control circuit 605 so that the access to the bank can be started immediately without waiting for the access to the other bank to end. By accessing a plurality of banks in a concurrent manner, even if a page miss continues, it is possible to access other banks while one bank is performing page close and open operations. Overhead can be concealed and memory access efficiency can be improved.

  As described above, there are several methods for scheduling the command issue order in order to improve the memory access efficiency, in addition to avoiding the bank collision described above. For example, Sonics' MemMax ™ (registered trademark) supports scheduling based on six conditions such as command bank, thread, chip select, and read / write.

  As described above, the bank-to-bank scheduling is to access banks in which commands issued successively are different. In scheduling between threads, a priority is set for each thread, and the thread with the highest priority is issued first. Scheduling between chip selects is performed by accessing a memory device assigned to a chip select in which commands issued successively are different. Scheduling between read and write is performed so that commands issued continuously are read and written as much as possible. That is, scheduling is performed so as to minimize switching from read to write and from write to read. In MemMaxTM, these schedulings are combined to retrieve commands from the command queue in an optimal order so that the memory can be accessed.

  However, even if the memory access command is reordered in the memory controller and the memory utilization efficiency is improved, if the required memory bandwidth is not yet obtained, further measures must be taken. One method is to increase the operating frequency of the memory, but it is not easy to significantly increase the operating frequency using the same semiconductor process technology. A simpler method is to increase the number of memory systems to, for example, two.

FIG. 7 is a diagram illustrating a configuration example of a system LSI having two memory devices. In FIG. 7, for comparison with FIG. 2, the same component is indicated with a numeral “′”. 7 is different from FIG. 2 in that a memory controller 240 and a memory 241 are added. Thus, by providing two systems of memory in the system, the total memory bandwidth of the system can be easily doubled, and the system performance can be improved.
JP 2000-21112 A

  Thus, when there are a plurality of memory controllers in the system, there is a problem that must be considered. In the case where a single master performs read access to a plurality of memory controllers at the same time, the read response time from each memory controller is not fixed but takes a certain time range. For this reason, read responses from a plurality of memory controllers may collide. In particular, when a complex scheduler is used as described above, it is more difficult to predict the response time. There are two approaches that have been taken in the past to address this problem.

  The first method is a method for prohibiting simultaneous read access from a single master to a plurality of memory controllers. However, this method significantly reduces the degree of freedom of the master for memory access. The master must always be aware of which memory controller the read address to be accessed is assigned to. If the next read address is assigned to a memory controller different from the currently read memory controller, the next read command must be issued until the current read is completed.

  In the second method, each memory controller is provided with a read / return buffer having a sufficient capacity, and if read responses collide with each other, arbitration is performed between them. Further, while another memory controller is transferring data to the master, the read response is retained in the read / return buffer. Further, when transfer to the master is permitted, the read response is extracted from the read / return buffer and transferred to the master. In this method, the circuit scale of the read / return buffer to be held in each memory controller becomes a problem.

  The memory controller is pipelined to maximize memory utilization efficiency. Now, when one read command is taken out from the command queue and the memory device is accessed, the result is transferred to the master as a read response. At this time, it is assumed that this read response collides with the read response of another memory controller, and as a result of arbitration, the read response must stay in the read return buffer. In this case, since the memory controller is performing a pipeline operation, it is considered that a plurality of subsequent commands are already taken out from the command queue and accessed to the memory device at this point. Furthermore, these may be read commands issued from the same master as the preceding read command. Since access to the memory device cannot be stopped halfway, the read response corresponding to these subsequent read commands needs to stay in the read return buffer as well.

  Therefore, when the second method is adopted, the necessary capacity of the read / return buffer must be secured by the maximum number of data read by a series of a plurality of read commands. For example, when a memory device having a memory bus width of 64 bits is accessed using 4-beat burst transfer, 64 bits × 4 = 256 bits per access are transferred. When DDR-SDRAM is used for the memory device, transfer of 2 beats per clock is performed. For this reason, the clock cycle required for this 4-beat burst access is 2 clocks. Considering the case of reading, it is necessary to issue a read command prior to the CAS latency cycle prior to the transfer of 4 beats on the memory bus. The CAS latency is generally 2 to 2.5 to 3. Considering the case where the CAS latency is 3, the number of cycles from when the read command is issued to when the data is read is 3 + 2 = 5 cycles. If the next read command is issued after this read is completed, the memory bus can use only 2 clock cycles per 5 cycles. Therefore, in order to increase the memory utilization efficiency, the next read command is issued during this time to cause a pipeline operation. Since the memory bus is occupied by two clocks per command, it is necessary to issue a read command once every two clocks in order to maximize the memory utilization efficiency. Therefore, two more read commands can be issued during five clock cycles. Usually several more cycles are required until the read from the memory device is completed and the read data can be transferred to the master. For this reason, the number of read commands issued in the pipeline during this period may further increase. When the first read response collides with a read response from another slave and the result of the arbitration is that it stays in the read return buffer, these subsequent read commands may all be commands from the same master. . Therefore, it is possible that all read responses of the subsequent read commands are also retained in the read return buffer. Even though such a situation rarely actually occurs, it must be able to cope with such a worst case in order to guarantee full operation. As a result, each memory controller needs to be provided with a read return buffer having a capacity of at least 256 bits × 4 = 1024 bits.

  An object of the present invention is to solve the above conventional problems.

  A feature of the present invention is to provide a technique that eliminates the need for a read return buffer for a bus master and prevents collision of read responses from a plurality of bus slaves.

In order to achieve the above object, a memory controller according to an aspect of the present invention has the following arrangement. That is,
A memory controller that accepts an access request to a memory from a bus master and accesses the memory,
An access means for accessing the memory upon receiving an access request to the memory from the bus master;
When the access request to the memory is a read, transfer means for transferring data read from the memory to the bus master;
Determining means for determining whether or not there is a collision with a read response from another bus slave to the bus master when the data is transferred by the transfer means;
A delay means for delaying access by the access means to the memory, when the determination means determines that there is a collision;
It is characterized by having.

In order to achieve the above object, an information processing apparatus according to an aspect of the present invention has the following arrangement. That is,
At least one bus master,
A plurality of bus slaves each including the memory controller according to any one of claims 1 to 7,
At least one memory;
It is characterized by having.

In order to achieve the above object, a memory control method according to an aspect of the present invention includes the following steps. That is,
A memory control method for receiving an access request to a memory from a bus master and accessing the memory,
An access step of accessing the memory upon receiving an access request to the memory from the bus master;
When the access request to the memory is a read, a transfer step of transferring data read from the memory to the bus master;
A determination step of determining whether or not there is a collision with a read response from another bus slave to the bus master when the data is transferred by the transfer step;
If it is determined that there is a collision in the determination step, a delay step for delaying access by the access step to the memory;
It is characterized by having.

  According to the present invention, it is possible to prevent a read response to the bus master from colliding with a read response from another slave, and a read return buffer provided in a conventional memory controller can be eliminated.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the present embodiments are essential to the solution means of the present invention. Not exclusively.

[Embodiment 1]
FIG. 8 is a block diagram illustrating a system configuration according to Embodiment 1 of the present invention.

  In the figure, reference numeral 800 denotes a system LSI, which includes a processor, a memory controller, a plurality of hardware engines having a DMA function, and a plurality of functional modules not shown for simplicity of explanation. The memories 801 and 802 are controlled by a memory controller built in the system LSI 800, and two sets of four 256M bits having a 4-bank configuration are mounted. Reference numerals 803 to 806 denote external I / O interfaces. Here, reference numeral 803 denotes a scanner interface, 804 denotes a printer interface, 805 denotes a PCI interface, and 806 denotes a USB interface, which are connected to a plurality of hardware engines inside the system LSI 800. The scanner 810 is connected to the system LSI 800 by a scanner interface 802. The printer engine 811 is connected to the system LSI 800 by a printer interface 804. The USB host 812 is connected to the system LSI 800 via the USB interface 806. The PCI expansion slot 813 is connected to the system LSI 800 via the PCI interface 805.

  More specifically, the hardware engine is a scanner controller, a printer controller, a PCI interface, a USB device interface, or the like. However, not only those related to the I / O interface, but also a hardware engine that performs image processing, image coding and decoding, data compression / decompression, and the like. These include both a read DMA controller and a write DMA controller. This will be described in detail with reference to FIG.

  FIG. 9 is a diagram for explaining a more specific configuration of the system LSI 800 according to the first embodiment.

  In FIG. 9, a processor 901 has a function compatible with MIPS-R4000. The scanner controller 906 is connected to an external scanner via the scanner interface 930. The printer controller 907 is connected to an external printer engine via the printer interface 931. The USB device controller 909 is connected to an external USB host via the USB interface 933. The PCI controller 908 has a PCI host bridge function, and is connected to one or more external PCI target devices via the PCI interface 932.

  Each of the memories 904 and 905 has a total capacity of 128 MB, and is composed of one 256 Mbit DDR SDRAM of 16 bits × 4 banks × 4M words. The JPEG compression / decompression engine 910 reads JPEG code data in the memory 904 or 905 by read DMA, decodes it, and writes the raw image data in the memory 904 or 905 by write DMA. Further, after the raw image data on the memories 904 and 905 is read and encoded by the read DMA, the code data can be written into the memory 904 or 905 by the write DMA. The system bus 920 connects a processor that is a bus master, each hardware engine, a memory controller that is a bus slave, and the like. Instead of a shared bus, a multi-layer structure is employed that allows multiple connections between multiple bus masters and multiple bus slaves. The memory controllers 902 and 903 support DDR-SDRAM, and these have the same configuration in the first embodiment. These are substantially the same in configuration as the memory controller shown in FIG. 6, but are changed in the present embodiment.

  FIG. 10 is a diagram for explaining the memory controllers 902 and 903 according to the first embodiment in more detail. Here, for comparison with FIG. 6, the same component is indicated by adding a '.

  FIG. 10 is significantly different from FIG. 6 in that the read data buffer 604 is removed in FIG. Also, the command issue control unit 606 ′ receives command issue timing information 620, and the command issue control unit 606 ′ outputs command issue timing information 621. These pieces of information 620 and 621 are exchanged between the memory controllers 902 and 903. The effect will be described later.

11 and 12 are diagrams for explaining the bus protocol of the system bus 920 according to the present embodiment. FIG. 11 shows read transfer, and FIG. 12 shows write transfer. As described above, the system bus 920 has a multi-layer configuration, and can be regarded as being connected one-to-one with an arbitrary bus slave when viewed from the bus master. The system bus 920 includes the following signals.
clk system bus clock
ts Bus Transaction Start Master → Master
addr [31: 2] Address Bus Master → Slave
mid [3: 0] Master ID Master → Slave
rd_not_wr Read (H) / Write (L) Master → Slave
b_size [3: 0] Access Size Master → Slave
rd_byteen [3: 0] Read Data Byte Enable Master → Slave
wr_data [31: 0] Write Data Bus Master → Slave
wr_byteen [3: 0] Write Data Byte Enable Master → Slave
srdy Slave Ready Slave → Master
rrdy Read Return Ready Slave → Master
rmid [3: 0] Return Master ID Slave → Master
rd_data [31: 0] Read Data Bus Slave → Master
rd_error Read Error Slave → Master
clk System Bus Clock The system bus 920 is a synchronous bus, and all signals of the system bus 920 are asserted / deasserted in synchronization with the rising edge of this signal.
ts [slave_num-1: 0] Transaction Start Master → Slave
Each bus master starts asserting when it wants to initiate a bus transfer and continues asserting until srdy (slave ready) is asserted. Then, it is deasserted in the next clock (Clock) cycle in which srdy is asserted. The bus transfer is started in a cycle in which both ts (bus transaction start) and srdy are asserted. The bus master can assert again after a deassertion period of ts for the next bus transfer. This signal is an independent signal for each slave.
addr [31: 2] Address Bus Master → Slave
It is determined at the same time as ts and held until the cycle one cycle after deassertion of ts.
mid [3: 0] Master ID Master → Slave
This is the ID of the bus master performing access. It is determined at the same time as ts and held until the cycle one cycle after deassertion of ts.
rd_not_wr Read (H) / Write (L) Master → Slave
Indicates bus transfer read / write. It is determined at the same time as ts and held until the cycle one cycle after deassertion of ts. A high level (High) indicates read, and a low level indicates write.
b_size [3: 0] Burst size Master → Slave
The number of bus transfer bursts on the system bus 920 is shown. 1 to 16 beats can be specified. It is determined at the same time as ts and held until the cycle one cycle after deassertion of ts. “0000” indicates one beat. Hereinafter, “0001” indicates 2 beats,..., “1111” indicates 16 beats.
rd_byteen [3: 0] Read Data Byte Enable Master → Slave
Indicates byte enable when reading. When b_size [3: 0] indicates single, it indicates to which byte position the 32 bits are read. When b_size indicates 2 beat burst or more, this signal is invalid and all are treated as enabled.
wr_byteen [3: 0] is valid in the Data Phase at the time of writing, but this signal is valid in the Address Phase at the time of reading. It is determined at the same time as ts and held until the cycle one cycle after deassertion of ts.
wr_data [31: 0] Write Data Bus Master → Slave
Write data from the master to the slave that is output to a 32-bit data bus. It becomes valid from the cycle following the cycle in which both ts and srdy are asserted. In the single transaction, only the first beat data is valid. In the 2 beat burst transaction, both the first and second beat data are valid. Which byte is valid is indicated by wr_byteen [3: 0]. Since the system bus 920 is a Big Endian Bus, the MSB side is 0 address.
wr_byteen [3: 0] Write Data Byte Enable Master → Slave
Indicates which byte position of the write data is valid. Similar to wr_data [31: 0], it is valid from the cycle following the cycle in which both ts and srdy are asserted. In single transaction, only the first beat is valid for all beats when transferring 2 beat bursts or more.

The correspondence between wr_byteen [3: 0] and wr_data is as follows.
wr_byteen [3] wr_data [31:24]
wr_byteen [2] wr_data [23:16]
wr_byteen [1] wr_data [15: 8]
wr_byteen [0] wr_data [7: 0]
srdy [slave_num-1: 0] Slave Ready Slave → Master
Indicates that the slave buffer is ready to accept bus transfers from the master. If this signal is asserted, the master can initiate a bus transfer at any time and the slave must accept the bus transfer. This signal corresponds to ts and is an independent signal for each slave.
rrdy Read Return Ready Slave → Master
This signal indicates a read return from the slave. The slave asserts this signal when read data is ready and starts a read return. This signal may be asserted at any time. Read data is returned in the same cycle as this signal is asserted. In the case of 2 beat burst, this signal is asserted for 2 cycles and read data for 2 beats is returned. At this time, this signal does not need to be continuously asserted, and a wait cycle can be interposed therebetween.
rmid [3: 0] Return Master ID Slave → Master
Indicates the ID of the master that should receive a read return. It holds mid [3: 0] asserted when a read request is accepted, and returns the same ID. The master decodes this signal when ts is asserted, and determines that the read return is a read return to itself when it is its own master ID. This rmid [3: 0] is asserted simultaneously with rrdy (read return ready).
rd_data [31: 0] Read Data Bus Slave → Master
Read data from a slave to a master on a 32-bit data bus. Valid data is returned in the cycle where rrdy is asserted.
rd_error Read Error Slave → Master
Notify the master of errors from the slave. If an error occurs, the slave asserts in the same cycle as rrdy on a read return.
Transaction type
(a) write transaction
Basic protocol
(1) Cycle-2: When a master starts a write (write) bus transfer, it asserts ts (bus transaction start) corresponding to the target slave. At the same time, b_size [3: 0], rd_not_wr, mid [3: 0], and addr [31: 2] are asserted.
(2) Cycle-3: Since srdy corresponding to the target slave is asserted, write bus transfer starts and ts is deasserted. Also, wr_data [31: 0] and wr_byteen [3: 0] are asserted to output the 1st bit write data.
(3) Cycle-4: b_size [3: 0], rd_not_wr, mid [3: 0], addr [31: 2] are deasserted. Also, wr_data [31: 0] and wr_byteen [3: 0] are switched and the second beat write data is output.
(4) Cycles 5 and 6: Transfer 3rd and 4th beats.
(5) Cycle-7: Write bus transfer end
(6) Cycles 7, 8: Even if the master asserts ts, if srdy is deasserted, the master continues to assert ts.
(7) Cycle-10: When srdy is asserted, ts is deasserted.
(8) Cycle-11: The master can assert again after a deassertion period of one cycle of ts to initiate the next bus transfer.

In the case where the write bus transfer is continuous and the interval between the bus transfers is most congested, it is possible to continue writing data without leaving an interval.
(b) Read transaction
The read bus transfer is divided into a read command bus transfer from the master to the slave and a read return of read data from the slave to the master. Each is independent, and the signal lines are also independent.
Basic Protocol
(1) Cycle-2: When the master starts a read bus transfer, it asserts ts corresponding to the target slave. At the same time, b_size [3: 0], rd_not_wr, rd_byteen [3: 0], mid [3: 0], and addr [31: 2] are asserted.
(2) Cycle-3: Since srdy corresponding to the target slave is asserted, read bus transfer starts and ts is deasserted.
(3) Cycle-4: b_size [3: 0], rd_not_wr, rd_byteen [3: 0], mid [3: 0], addr [31: 2] are deasserted.

Read command bus transfer end of read bus transfer
(4) Cycle-6: When read data is ready, the slave asserts rrdy and rmid [3: 0] and starts read return. In rmid [3: 0], the master ID received from the master by the read command is placed. Also, rd_data [31: 0] is asserted, and the 1st Beat read data is output.
(5) Cycles 7, 8, 9: Transfer 2nd to 4th beats.
(6) Cycle-9: Deassert rrdy. Deassert rmid [3: 0].
(7) Cycle-10: Read return completed If srdy is deasserted even if the master asserts ts (cycles-8 and 9), the master continues to assert ts. When srdy is asserted, ts is deasserted (cycle-10).
(8) Cycle-11: The master can assert again after a deassertion period of one cycle of ts to initiate the next bus transfer.
(9) Cycle-13: rrdy does not need to be continuously asserted, and any wait cycle can be inserted.
(10) Cycle-16: If there is more data to return, the slave can continuously assert rrdy to initiate the next read return. When the read bus transfer is continuous, it is possible to continue reading data without leaving an interval on the read data bus.

  Next, an embodiment of the present invention will be described by taking an actual operation as an example.

  FIG. 13 shows a timing chart when the processor 901 reads data from the memory controllers 902 and 903 in FIG. 9 at the same time. The correspondence between the physical address and the bank address, row address, and column address of the memory device is the same as in FIG. Hereinafter, the processor 901 is called a master, the memory controller 902 is called a slave 1, and the memory controller 903 is called a slave 2.

  In FIG. 13, the master first asserts the ts signal (1300) and starts data transfer (cycle 1). On the other hand, slave 1 asserts srdy (1301) and accepts this command (cycle 2). In this case, the address is “0x00000400”. Although not shown due to space limitations, this command is read (rd_not_wr = 1) and 8 beats (b_size = 0111). Subsequently, the master asserts the ts signal again (1302), and starts the second transfer (cycle 4). On the other hand, the slave 2 asserts srdy (1303) and accepts this command (cycle 5). The address at this time is “0x00037bfc”. This command is also an 8-beat read command.

  Upon receiving these read commands from the processor 901, the memory controller 902 temporarily stores them in the command queue (602 ′ in FIG. 10). Here, the bank collision is judged. In this example, the command queue 602 ′ has only one command and there is no bank collision. Therefore, this read command is immediately sent to the memory control circuit 605 ′ to perform read access to the memory 904. If this command causes a bank collision, the read command stays in the command queue 602 ′ until the bank becomes accessible again. During this time, another command is input to the command queue 602 ′, and if the command does not cause a bank collision, the command is issued first.

  As a result of the read access, the memory 904 sequentially returns the read data to the memory controller 902. Upon receiving this, the memory controller 902 transfers it to the master (processor 901) (cycle 9 to cycle 16).

  In this embodiment, since the system bus is composed of 32 bits, the master accesses the system bus in units of 32 bits. Here, since the bus width of the memory 904 is 16 bits, the memory controllers 902 and 903 issue 16-beat read access to the memory 904 or 905 in response to 8-beat transfer on the system bus. The read result is returned to the master every 32 bits.

  Here, it should be noted that the memory 904 is composed of DDR-SDRAM. That is, for a 2-beat access to the memory 904, data is transferred with one system bus clock. Therefore, the time required to transfer 8-beat data on the system bus 920 is equal to the time required to transfer 16-beat data on the memory bus.

  If the memory controller 903 also performs a read access to the memory 905 as soon as the memory controller 903 receives a read command, like the memory controller 902 performs for the memory 904, the read responses collide with each other. This is evident in FIG. In FIG. 13, it takes 6 clocks from when the slave 1 receives a command from the master to when the first beat of the read response is transferred to the master. Thus, under the same conditions, the slave 2 returns a read response from the cycle 12 (1304) after 6 clocks from the cycle 5 in which the slave 2 receives the command from the master. However, this leads to collision of read responses.

  In order to avoid this, in the present embodiment, the command issue timing information is exchanged between the memory controllers 902 and 903 as described above. As an example, the command issue timing information includes read command issue prohibition period information for each master.

  In the present embodiment, the read command issuance prohibition period information uses the same type of memory controller and the same type of memory device, and further adopts a close page policy, so all timings are similar. Can be easily generated. That is, it is only necessary to prohibit the issuance of commands during the data burst length period.

  FIG. 14 is a sequence diagram illustrating these relationships.

  When the slave 1 receives a read command from the master, the slave 1 starts read access to the memory 1 and outputs read command issue prohibition period information to the slave 2 at the same time. When the slave 2 receives this command issuance prohibition period information, the slave 2 holds it in a down counter held for each internal master, and counts down every cycle. When the slave 2 receives the read command from the master, the slave 2 delays the start of the read access to the memory 2 during this read command issuance prohibition period, that is, until the counter is decremented to “0”. In this way, it is possible to prevent the read responses from the two slaves from colliding. As a result, it is possible to eliminate the need for the read / return buffer provided in the conventional memory controller.

  It should be noted that the memory use efficiency does not immediately decrease by providing the command issuance prohibition period here. That is, commands from other masters and write commands from the same master can be issued even during this command issuance prohibited period. After all, the command issue prohibition period may be used as a condition for scheduling command queues that can be issued out of order.

  While the invention has been illustrated and described with respect to specific embodiments, it will be appreciated that other modifications and improvements are possible.

  For example, in the present embodiment, the case where two memory controllers are provided in the system LSI has been described. However, the number of memory systems is not limited to this number, and is limited to memory controllers as slaves. not. For example, in the present embodiment, the case where a bus having a specific signal and protocol is used as the system bus has been described. However, the present invention is not limited to this, and any bus is used as the system bus. It may be configured.

  Also, for example, in this embodiment, for the sake of simplicity, the priority setting method between masters has not been described in detail, but for example, in units of transfer using a system bus including a priority signal. You may make it give a priority.

  For example, in this embodiment, the case where a DDR-SDRAM is used as a memory device has been described as an example, but it is needless to say that the present invention is not limited to this.

  For example, in the present embodiment, the case where the beat length when accessing the memory device is 8 has been described, but it goes without saying that the present invention can be applied to any beat length.

  As described above, according to the first embodiment, the timing at which the memory controller issues the read command is delayed as necessary. Thereby, it is possible to prevent the read response from the memory controller to the bus master from colliding with the read response from another slave. As a result, the read / return buffer provided in the conventional memory controller can be eliminated, and the circuit scale of the system LSI including the memory controller can be reduced and realized at low cost.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. Since the hardware configuration of the system according to the second embodiment is the same as that of the first embodiment, the description thereof is omitted.

  FIG. 15 is a diagram for explaining the memory controllers 902 and 903 according to the second embodiment in more detail. Here, for comparison with FIG. 6 according to the above-described first embodiment, the same components are indicated by adding a '.

  15 differs greatly from FIG. 6 in that the read / return buffer 604 is removed in FIG. Further, in FIG. 15, a reserve queue 607 is added. The effect will be described later.

16 and 17 are diagrams for explaining the bus protocol of the system bus 920 according to the second embodiment. Here, FIG. 16 shows read transfer, and FIG. 17 shows write transfer. As described above, the system bus 920 has a multi-layer structure, and can be regarded as being connected one-to-one with an arbitrary bus slave when viewed from the bus master. Since signals constituting the system bus 920 are the same as those in the first embodiment, the description thereof is omitted. However, in this second embodiment,
rd_accept Read Accept Master → Slave
Is added. This indicates that the master can receive a read return from the slave.

  In the second embodiment, the read transaction is slightly different from that of the first embodiment, and the protocol will be described.

Read transaction
The read bus transfer is divided into a read command bus transfer from the master to the slave and a read return of read data from the slave to the master. Each is independent, and the signal lines are also independent.
Basic Protocol
(1) Cycle-2: When the master starts a read bus transfer, it asserts ts corresponding to the target slave. At the same time, b_size [3: 0], rd_not_wr, rd_byteen [3: 0], mid [3: 0], and addr [31: 2] are asserted.
(2) Cycle-3: Since srdy corresponding to the target slave is asserted, read bus transfer starts and ts is deasserted.
(3) Cycle-4: b_size [3: 0], rd_not_wr, rd_byteen [3: 0], mid [3: 0], addr [31: 2] are deasserted.

Read command bus transfer end of read bus transfer
(4) Cycle-5: The slave asserts rrdy (read return ready) when read data is ready.
(5) Cycle-6: Assert rmid [3: 0] and start read return. In rmid [3: 0], the master ID received from the master by the read command is placed. Also, rd_data [31: 0] is asserted, and the 1st Beat read data is output. Since rd_accept is asserted, this transfer is accepted by the master.
(6) Cycles 7, 8, and 9: The second beat, the third beat, and the fourth beat are transferred. Similarly, since rd_accept is asserted, these transfers are received by the master.
(7) Cycle-9: Deassert rrdy.
(8) Deassert cycle-10: rmid [3: 0]. End of transfer.

If the master asserts ts but srdy is deasserted (cycles-7, 8), the master continues to assert ts. When srdy is asserted, ts is deasserted (cycle -10)
(9) The master can assert again after a deassertion period of one cycle of ts to initiate the next bus transfer. rrdy does not need to be continuously asserted and can have any wait cycle (cycle-13)
(10) Cycle-15: If there is more data to return, the slave can continuously assert rrdy to initiate the next read return. When the read bus transfer is continuous, data can be continuously read on the read data bus without any interval.

  Next, how the rd_accept signal is generated will be described.

  FIG. 18 is a block diagram showing a read / return arbitration circuit.

  As many read return arbitration circuits as the number of masters are provided in the system bus 920. This is arranged on a path through which a read response is transferred from each slave to the master, and selects one of the read responses returned from a plurality of slaves. Rd_accept is asserted for the slave that has transmitted the read response thus selected, and rd_accept is deasserted for the other slaves. When a plurality of read responses reach the read return arbitration circuit at the same time, only one of them is selected according to a predetermined priority.

  Next, the second embodiment of the present invention will be described by taking an actual operation as an example.

  FIG. 19 is a timing chart when the processor 901 reads from the memory controllers 902 and 903 at the same time in FIG. The correspondence between the physical address and the bank address, row address, and column address of the memory device is the same as in FIG. Hereinafter, the processor 901 is called a master, the memory controller 902 is called a slave 1, and the memory controller 903 is called a slave 2.

  In FIG. 19, first, the master asserts the ts signal and starts transfer (1901). As a result, slave 1 asserts srdy (1902) and accepts this command. The address at this time is “0x00000400”. Although not shown due to space limitations, this command is read (rd_not_wr = 1) and 8 beats (b_size = 0111). Subsequently, the master asserts the ts signal again and starts the second transfer (1903). As a result, the slave 2 asserts srdy and accepts this command (1904). The address at this time is “0x00037bfc”. This command is also an 8-beat read command.

  When accepting this read command, the memory controller 902 temporarily stores it in the command queue (602 ′ in FIG. 15). Here, the bank collision is judged. In this example, since there is only one command in the command queue 602 ′ and there is no bank collision, it is immediately sent to the memory control circuit 605 ′ to perform read access to the memory 904. At this time, the read command is stored in the reserve queue 607. If this command has caused a bank collision, the command will remain in the command queue 602 ′ until the bank becomes accessible again. During this time, if another command is input into the command queue 602 ′ and the command does not cause a bank collision, the command is issued first. The memory 904 sequentially returns the data read as a result of the read access to the memory controller 902. Upon receiving this, the memory controller 902 transfers it to the master (cycle 9 to cycle 16). Since rd_accept is asserted at this time, transfer of these read responses is received by the master. As a result, the memory controller 902 deletes the read command from the reserve queue 607.

  In the second embodiment, since the system bus is composed of 32 bits, the master accesses the system bus in units of 32 bits. On the other hand, since the bus width of the memory 904 is 16 bits, it corresponds to 8-beat transfer on the system bus, and the memory controllers 902 and 903 issue a 16-beat read access to the memory 904 or 905. The read result is returned to the master every 32 bits. Here, it should be noted that the memory 904 is composed of DDR-SDRAM. That is, in the 2-beat access to the memory 904, data is transferred by one clock of the system bus clock. Accordingly, the time required for transferring 8-beat data on the system bus is equal to the time required for transferring 16-beat data on the memory bus.

  As the memory controller 902 performs access to the memory 904, the memory controller 903 also performs read access to the memory 905 immediately upon receiving the read command. At this time, it is clear in FIG. 19 that the read responses collide with each other.

  In FIG. 19, 6 clocks are required from when the slave 1 receives a command from the master to when the first beat of the read response is transferred to the master. Therefore, under the same condition, the slave 2 returns a read response from the cycle 12 after 6 clocks from the cycle 5 in which the slave 2 receives the command from the master.

  However, in FIG. 19, rd_accept is “0” in cycle 12. Therefore, the memory controller 903 recognizes the collision of the read response, and discards the data read from the memory without transferring it to the master. Since the DDR-SDRAM memory has a property that once reading is started, it cannot be interrupted halfway, so this continues for cycles 12-19.

  At this time, the memory controller 903 holds the read command at this time in the reserve queue 607. Therefore, the memory controller 903 performs rescheduling when it recognizes a read response collision. Thus, the read command is extracted from the reserve queue 607 so that the read response can be transferred from the cycle 20 to the master, and the memory 905 is read-accessed again in the cycle 20. In this case, since rd_accept is “1” in cycle 20, this read response is transferred to the master.

  As described above, in the second embodiment, even when read responses from a plurality of slaves including the memory controller collide, the memory controller once discards the read responses and performs the same read to the memory. Repeat access. Thereby, the timing at which the read response collides can be shifted. As a result, the read / return buffer provided in the conventional memory controller can be eliminated.

  While the invention has been illustrated and described with respect to particular embodiments, it will be appreciated that other modifications and improvements are possible.

  For example, in the second embodiment, the case where two memory controllers are provided in the system LSI has been described. However, the number of memory systems is not limited, and the memory controller is not limited to a memory controller. Further, for example, in the second embodiment, the case where a bus having a specific signal and protocol is used as the system bus has been described. However, the present invention is not limited to this, and any bus may be used as the system bus. May be.

  Further, for example, in the second embodiment, the method for setting the priority between masters has not been described in detail for the sake of simplicity. However, for example, by using a system bus including a priority signal, a transfer unit is used. You may make it give a priority.

  For example, in the second embodiment, the case where a DDR-SDRAM is used as a memory device has been described as an example, but it is needless to say that the present invention is not limited to this.

  Further, for example, in the second embodiment, the case where the beat length when accessing the memory device is 8 has been described, but any beat length can be applied.

  Further, the present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), or an apparatus composed of a single device (for example, a copier, a facsimile machine, etc.). It may be applied.

  Another object of the present invention is to mount a storage medium recording software program codes for realizing the functions of the above-described embodiments in a system or apparatus, and read and execute the installed program codes from the storage medium. Is also achieved. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention. Further, the functions of the above-described embodiment are realized by executing the program code read by the computer. In addition, the operating system (OS) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing. It is.

  Furthermore, the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, and the CPU of the main body executes part or all of the processing. Thus, the functions of this embodiment may be realized.

  The storage medium for supplying the program includes, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, and nonvolatile memory. There are cards. Furthermore, ROM and DVD (DVD-ROM, DVD-R) are also included.

  Alternatively, the browser of the client computer may be used to connect to a homepage on the Internet, and the computer program itself of the present invention or a compressed file including an automatic installation function may be downloaded from the homepage to a storage medium. It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the claims of the present invention.

  Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

It is a figure which shows an example of a structure which implement | achieves the embedded system of OA apparatus using the conventional system LSI. It is a block diagram explaining the system LSI of a prior art example in detail. It is a figure explaining the physical address space of the memory which the processor in a prior art example handles. It is a figure explaining an example of the relationship between the physical address in a prior art example, a bank address, a row address, and a column address. It is a figure explaining another example of the relationship between the physical address in a prior art example, a bank address, a row address, and a column address. It is a block diagram which shows an example of a structure of the conventional memory controller. It is a figure which shows the structural example of system LSI provided with two memory devices. It is a block diagram explaining the system configuration | structure which concerns on Embodiment 1 of this invention. It is a figure explaining the more specific structure of the system LSI which concerns on this Embodiment 1. FIG. It is a figure explaining the structure of the memory controller which concerns on this Embodiment in detail. , It is a figure explaining the bus protocol of the system bus concerning this Embodiment 1. FIG. 10 is a timing chart when the processor of FIG. 9 simultaneously reads from the memory controller. It is a sequence diagram explaining operation | movement of the master and slave which concern on this Embodiment 1. FIG. It is a figure explaining the structure of the memory controller which concerns on this Embodiment 2 in detail. , It is a figure explaining the bus protocol of the system bus concerning this Embodiment 2. FIG. It is a block diagram which shows the structure of the read return arbitration circuit which concerns on this Embodiment 2. 10 is a timing chart illustrating a case where the processor according to the second embodiment controls reading from two memory controllers simultaneously.

Claims (15)

A memory controller that accepts an access request to a memory from a bus master and accesses the memory,
An access means for accessing the memory upon receiving an access request to the memory from the bus master;
When the access request to the memory is a read, transfer means for transferring data read from the memory to the bus master;
Determining means for determining whether or not there is a collision with a read response from another bus slave to the bus master when the data is transferred by the transfer means;
A delay means for delaying access by the access means to the memory, when the determination means determines that there is a collision;
A memory controller comprising: A command queue for sequentially storing access requests received from the bus master;
Means for executing access by the access means in response to a command taken out from the command queue,
The memory controller according to claim 1, wherein the delay unit delays access to the memory by prohibiting the extraction of the command from the command queue.   3. The memory controller according to claim 1, wherein the transfer unit transfers the read data with the identifier of the bus master when transferring the read data to the bus master.   4. The memory controller according to claim 1, wherein the determination unit determines whether or not the collision occurs based on read access timing information from another bus slave. A memory controller that accepts an access request to a memory from a bus master and accesses the memory,
An access means for accessing the memory upon receiving an access request to the memory from the bus master;
Storage means for storing an access request to the memory;
Transfer means for transferring data read from the memory to the bus master when the access request to the memory is read;
When the data is transferred by the transfer unit, if there is a collision with a read response from another bus slave to the bus master, the access unit accesses the memory based on the access request stored in the storage unit. Re-execution means to be executed;
A memory controller comprising:   6. The memory controller according to claim 5, wherein the transfer unit transfers the read data with an identifier of the bus master when transferring the read data to the bus master.   7. The memory controller according to claim 5, further comprising means for deleting an access request stored in the storage means in response to a read response receipt signal from the bus master. At least one bus master,
A plurality of bus slaves each including the memory controller according to any one of claims 1 to 7,
At least one memory;
An information processing apparatus comprising: A memory control method for receiving an access request to a memory from a bus master and accessing the memory,
An access step of accessing the memory upon receiving an access request to the memory from the bus master;
When the access request to the memory is a read, a transfer step of transferring data read from the memory to the bus master;
A determination step of determining whether or not there is a collision with a read response from another bus slave to the bus master when the data is transferred by the transfer step;
If it is determined that there is a collision in the determination step, a delay step for delaying access by the access step to the memory;
A memory control method comprising: A command queue for sequentially storing access requests received from the bus master;
Accessing the memory in response to a command retrieved from the command queue,
The memory control method according to claim 9, wherein in the delaying step, access to the memory is delayed by prohibiting the extraction of the command from the command queue.   11. The memory control method according to claim 9, wherein in the transfer step, when the read data is transferred to the bus master, the identifier is assigned to the bus master.   12. The memory control method according to claim 9, wherein in the determination step, it is determined whether or not the collision occurs based on read access timing information from another bus slave. A memory control method for receiving an access request to a memory from a bus master and accessing the memory,
An access step of accessing the memory upon receiving an access request to the memory from the bus master;
A storage step of storing an access request to the memory;
A transfer step of transferring data read from the memory to the bus master when the access request to the memory is a read;
During the transfer of the data in the transfer step, if there is a collision with a read response from another bus slave to the bus master, the access to the memory is accessed based on the access request stored in the storage step. A re-execution step to be executed;
A memory control method comprising:   14. The memory control method according to claim 13, wherein in the transfer step, when the read data is transferred to the bus master, the identifier is assigned to the bus master.   15. The memory control method according to claim 13, further comprising means for deleting an access request stored in the storage step in response to a read response reception signal from the bus master.

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