JP5094050B2 - Memory control device, memory control method, and embedded system - Google Patents

Description

  The present invention relates to a memory control apparatus and method.

  Due to advances in semiconductor technology and microprocessor technology, the application fields of embedded systems are steadily expanding, and embedded systems are used in almost all electronic and electrical devices around us. In recent years, as the degree of integration of LSIs has improved, so-called system LSIs in which controller functions of embedded devices are integrated in one LSI have become common.

  FIG. 7 is a diagram showing an example of a configuration that realizes an embedded system of OA equipment using a system LSI disclosed in Patent Document 1, for example.

  In FIG. 7, reference numeral 110 denotes an embedded system board on which a system LSI 100, a memory 101, and various IO interfaces are mounted. The system LSI 100 is a single chip scanning printing engine. More specifically, the system LSI 100 includes a processor core, a processor peripheral controller, a memory controller, a scanner controller, a printer controller, a PCI interface, a USB device interface, and the like.

  The IO interface provided in the embedded substrate 110 includes a scanner IF 131, a FAX IF 132, a USB IF 134, a printer IF 133, and the like. These IO interfaces are connected to the scanner 121, the FAX 122, the PC 124, and the printer engine 123, respectively, to constitute the entire system. Further, the system LSI 100 is provided with a PCI bus IF 136. By using this, the HDD 125 connected to the IDE bus 135 via the PCI-IDE bridge 102 can be used.

  FIG. 2 is a diagram for explaining the system LSI 100 in more detail.

  In the processor 201, it is possible to incorporate a maximum of 32K bytes of instruction, 16K bytes each of data, FPU (floating point arithmetic unit), MMU (memory management unit), user-definable coprocessor, etc. is there.

  Since it has a PCI bus interface 232, it can be used with a computer system having a PCI bus slot. In addition to the PCI satellite configuration, a PCI bus configuration can be issued in a PCI host bus bridge configuration. Therefore, it can be used as a main engine of a multifunction peripheral (multifunctional peripheral device) by combining with an inexpensive PCI peripheral device. Further, it can be combined with a rendering engine having a PCI bus interface and a compression / decompression engine.

  There are two independent buses, an IO bus (B bus) 221 for connecting a general-purpose IO core inside the chip, and a graphic bus (G bus: Graphics Bus) 220 optimized for image data transfer. Then, the memory 204 (101) and the processor 201 are connected to these buses via a system bus bridge 203 which is a crossbar switch. With this configuration, high-speed data transfer with high parallelism necessary for simultaneous operation in the multifunction system is realized.

  In addition, a memory controller 202 that supports a synchronous DRAM (SDRAM) having high cost performance with respect to continuous data string access represented by image data is incorporated.

  In addition, a scanner controller 205, a printer controller 206, a PCI controller 207, a USB controller 208, a UART 209, a MISC module 210 including a timer / GPIO function, a LAN controller 211, and the like are incorporated. Reference numerals 230 to 233 denote IO interfaces 205 to 208, respectively. The interfaces 131, 133, 134, and 136 of the same name in FIG.

  FIG. 3 is a diagram for explaining a typical composite operation sequence. Here, while the original is scanned by the scanner 121, a so-called copying operation for printing the read original from the printer engine 123 is performed. Image data obtained by scanning the document is sent from the scanner 121 to the scanner controller 205 built in the system LSI 100 via the scanner interface 131 (230) (301). The scanner controller 205 stores the received image data in the memory 204 (101) by DMA (302). Next, the printer controller 206 reads this data from the memory 204 by DMA (303) and sends it to the printer engine 123 via the printer interface 231 (133) (304). The printer engine 123 prints this.

  At this time, PDL data is further transmitted from the PC 124 via the USB interface 134 (233) (311). The PDL data is received by the USB device controller 208 and temporarily stored in the memory 204 by DMA (312). Thereafter, the image 201 interpreted and expanded by the processor 201 in the system LSI 100 is stored again in the memory 204 (313). Finally, it is read from the memory 204 by the printer controller 206 (314), sent to the printer engine 123 via the printer interface 231 (133) (315), and printed.

  FIG. 4 shows a physical address space handled by the processor 201 at this time. Actually, the processor 201 is compatible with MIPS R4000, and the software on the processor 201 operates using a virtual address. The processor 201 always operates in the kernel mode, and the physical addresses 0x0000 — 0000 to 0x1fff_ffff are associated with the virtual addresses 0x8000 — 0000 to 0x9 fff_ffff (kseg0: cached) and 0xa000 — 0000 to 0xbfff_ffff (kseg1: uncached).

  In this conventional example, the capacity of the memory 204 is 32 MB, and one 256 Mbit SDRAM having a 16 bit × 4 bank × 4 M word configuration is mounted. Therefore, the physical address space that can be used as the RAM is from 0x0000 — 0000 to 0x01ff_ffff.

  When the composite operation of FIG. 3 is performed, software operating on the processor 201 manages a buffer area on the memory 204 used by each hardware. Normally, as in the case where a memory area is dynamically secured by software, a memory area function (system function provided by the OS: malloc or the like) is used to secure an area of a necessary size in the Heap area.

  In the case of the composite operation of FIG. 3, the buffer area that the scanner controller 205 writes by DMA and the buffer area that the printer controller 206 reads by DMA are the same. If there is only one buffer area, the printer controller 206 reads the address written by the scanner controller 205 later. However, the reading speed from the scanner is usually different from the printing speed of the printer. Therefore, unless there is a mechanism for synchronization between the scanner controller 205 and the printer controller 206, the read address may overtake the write address in the middle.

  In order to avoid this, a double buffer is generally used. That is, while the scanner controller 205 is writing to one buffer area by DMA, the printer controller 206 reads from the other buffer area by DMA. When both DMA transfers are completed, the buffers to be used are replaced and the next DMA is started.

  For example, when 1 MB of data is continuously sent from the scanner 121 to the scanner controller 205, the memory allocation function is first called with an argument of 1 MB. The returned address is converted into a physical address because it is a virtual address, and is set as the DMA start address of the scanner controller 205. Here, addresses 0x0080_0000 to 0x008f_ffff are secured, and the address 0x800_0000 which is the head address is set as the DMA start address. Next, when data arrives, the scanner controller 205 stores data continuously from the start address by DMA. When this DMA is completed, the address 0x0080_0000 is set in the printer controller 206 as the DMA start address. After that, when the DMA start is instructed by the software, the data is sequentially read from the set start address in accordance with the signal of the printer interface 231, and the data is transferred to the printer engine 123 via the printer interface 231.

  At the same time, the next DMA is set for the scanner controller 205. When the memory allocation function is called again with the argument set to 1 MB and the addresses 0x0090_0000 to 0x009f_ffff are secured, the address 0x0090_0000 which is the head address is set as the DMA start address. When data arrives from the scanner interface 230, the scanner controller 205 stores data continuously from the start address by DMA.

  In this way, the DMA operation is repeatedly performed between the scanner controller 205 and the printer controller 206 while alternately using the two areas 0x0080_0000 to 0x008f_ffff and 0x0090_0000 to 0x009f_ffff.

  On the other hand, in the case of the USB controller 208, addresses 0x00b0_0000 to 0x00bf_ffff are secured, and the start address 0x00b0_0000 is set as the DMA start address. When PDL data is sent from a PC (USB host) 124, the USB controller 208 stores data continuously from the start address by DMA. When all transfers are completed, the software is notified by an interrupt, and then the PDL data is interpreted by the software and print image data is generated. The finally generated print image data is stored in a newly secured buffer area. For this, the memory allocation function is called again, and a 3 MB area 0x00c0_0000 to 0x00ef_ffff is secured. Next, the printer controller 206 is activated with the address 0x00c0_0000 as the start address of the DMA. The DMA transfer of the printer controller 206 at this time is performed exclusively with the DMA transfer of the printer controller 206 during the above-described scanner printer operation.

As described above, when access to the scanner, the printer, and the HDD occurs simultaneously, a plurality of hardwares simultaneously perform DMA access to the memory inside the system LSI.
JP 2000-21112 A

  As described above, when a plurality of masters issue access requests to only one memory resource in the system LSI, the access requests may always overlap with a certain probability. When data must be continuously supplied to the printer engine as in a printer controller, latency must be increased when access conflicts. Therefore, it is necessary to make the FIFO capacity for buffering the data rate large enough to be safe even in the worst case of the delay value. For this reason, the circuit scale is increased, the chip price is increased, and various adverse effects such as an increase in heat generation and a decrease in reliability are caused.

  For example, in a certain DMA transfer, 32 bytes are transferred per transfer. At this time, if the FIFO memory has only 32 bytes, the next transfer can be started only after the FIFO becomes empty. This configuration cannot be applied when it is necessary to supply data to the printer engine without interruption once the printer operation is started, as in the printer controller described above. The FIFO is required to have a capacity capable of storing a plurality of DMA transfers. A capacity of at least two DMA transfers, that is, 64 bytes is required.

  Assume that the printer interface includes a FIFO having a capacity of 64 bytes. When the FIFO content is 32 bytes or less, the printer interface can issue the next DMA transfer request to the memory controller. If the next data is read from the memory and written to the FIFO by DMA transfer before the FIFO is emptied, the data can be supplied to the printer engine without interruption.

  When the printer interface issues a DMA transfer request to the memory controller, if there is no other master requesting memory access at the same time, data can be read and stored in the FIFO before the FIFO becomes empty. However, at this time, if another master has issued an access request to the memory controller immediately before, the printer controller cannot read the data from the memory and store it in the FIFO until the memory access request is processed.

  Depending on the conditions, the increase in the delay time may cause a situation in which the printer controller cannot read the data in time, and the FIFO becomes empty during this time.

  In order to avoid such a case, the FIFO capacity of the printer controller is provided with a capacity of, for example, 128 bytes so that there is no problem even in the worst case. If there is little memory contention, in most cases it will be in time if it has a capacity of 64 bytes or 96 bytes at most, but the circuit scale has been increased in order to cope with rare cases.

An object of the present invention is to suppress an increase in memory access latency experienced by a master having a high priority even when memory accesses from a plurality of masters compete, and to reduce the capacity of a buffer FIFO.

The memory control device of the present invention includes a receiving unit that receives a plurality of read requests from a plurality of request sources, an access unit that accesses a memory according to the read request received by the receiving unit, and a result of access by the access unit. Storage means for storing the read data; and transfer means for transferring the read data stored in the storage means to the request source that requested the read data. The transfer means sends the read data to the first request source. If the storage means stores read data to a second request source having a higher priority than the first request source during data transfer, the transfer means interrupts data transfer to the first request source. The data transfer to the second request source is started .

  According to the present invention, even when memory accesses from a plurality of masters compete, an increase in memory access latency experienced by a master with high priority can be suppressed and the capacity of the buffer FIFO can be reduced.

  In addition, according to the present invention, even when memory access requests from a plurality of masters in the system LSI compete with each other, the memory access efficiency of the high priority master is increased at the same time without reducing the memory access efficiency. It becomes possible to suppress.

  Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 8 is a diagram for explaining a block diagram of the first embodiment of the present invention. In FIG. 8, reference numeral 800 denotes a system LSI, which includes a processor, a memory controller, a plurality of hardware engines having a DMA function, and a plurality of functional modules not shown for the sake of simplicity. Reference numeral 801 denotes a memory controlled by a memory controller built in the system LSI 800, and four 256Mbits having a 4-bank configuration are mounted. 802 to 805 are external IO interfaces, 802 is a scanner interface, 803 is a printer interface, 804 is a PCI interface, and 805 is a USB interface. Each of the external IO interfaces 802 to 805 is connected to the plurality of hardware engines inside the system LSI 800. A scanner 810 is connected to the system LSI 800 via a scanner interface 802, and a printer engine 811 is connected to the system LSI 800 via a printer interface 803. A USB host 812 is connected to the system LSI 800 via the USB interface 805, and a PCI expansion slot 813 is connected to the system LSI 800 via the PCI interface 804.

  More specifically, the hardware engine is a scanner controller, a printer controller, a PCI interface, a USB device interface, or the like. However, this hardware engine is not necessarily related to the IO interface, but includes a hardware engine that performs image processing, image coding and decoding, data compression / decompression, and the like. These include both a read DMA controller and a write DMA controller. This will be described in detail with reference to FIG.

  FIG. 9 is a diagram for explaining a more specific configuration of the system LSI 800 of FIG. 9 in the present embodiment.

  In FIG. 9, reference numeral 901 denotes a processor having a function compatible with MIPS R4000. A scanner controller 905 is connected to an external scanner 810 via a scanner interface 930. A printer controller 906 is connected to an external printer engine 811 via a printer interface 931. A PCI controller 907 has a PCI host bridge function, and is connected to one or more external PCI target devices via a PCI interface 932. A USB device controller 908 is connected to an external USB host 812 via the USB interface 933.

  Reference numeral 904 denotes a memory having a total capacity of 128 MB and is configured by four 256 Mbit DDR SDRAMs having a 16 bit × 4 bank × 4 M word configuration. The memory 904 corresponds to the memory 801 in FIG.

  Reference numeral 909 denotes a JPEG compression / decompression engine, which has a function of reading JPEG code data on the memory 904 by read DMA, decoding it, and writing raw image data to the memory 904 by write DMA. The JPEG compression / decompression engine 909 also has a function of reading the raw image data on the memory 904 by read DMA and encoding it, and then writing the code data to the memory 904 by write DMA.

  A system bus 920 connects a processor 901 that is a bus master, each hardware engine, a memory controller 902 that is a bus slave, and the like. Instead of a shared bus, a multi-layer structure is employed that allows multiple connections between multiple bus masters and multiple bus slaves.

  Reference numeral 902 denotes a memory controller that supports DDR SDRAM, which is shown in detail in FIG.

  5 and 6 are diagrams for explaining the bus protocol of the system bus 920 in the first embodiment of the present invention. FIG. 5 shows read transfer, and FIG. 6 shows write transfer. As described above, the system bus 920 has a multi-layer configuration, and can be regarded as being connected one-to-one with an arbitrary bus slave when viewed from the bus master.

In this embodiment, the system bus 920 includes the following signals.
clk system bus clock
ts Bus Transaction Start Master → Slave
addr [31: 2] Address Bus Master → Slave
mid [3: 0] Master ID Master → Slave
rd_not_wr Read (H) / Write (L) Master → Slave
one_not_two Access Size Master → Slave
rd_byteen [3: 0] Read Data Byte Enable Master → Slave
wr_data [31: 0] Write Data Bus Master → Slave
wr_byteen [3: 0] Write Data Byte Enable Master → Slave
srdy Slave Ready Slave → Master
rrdy Read Return Ready Slave → Master
rmid [3: 0] Return Master ID Slave → Master
rd_data [31: 0] Read Data Bus Slave → Master
rd_error Read Error Slave → Master

  Hereinafter, each signal will be described.

  The system bus 920 is a synchronous bus, and all signals of the system bus 920 are asserted / deasserted in synchronization with the rising edge of the system bus clock clk.

  Each bus master starts asserting Transaction Start (ts) when it wants to start bus transfer, and continues asserting Transaction Start (ts) until srdy is asserted. Transaction Start (ts) deasserts in the next Clock cycle in which srdy is asserted. Bus transfer starts in a cycle in which both ts and srdy are asserted. The bus master can reassert Transaction Start (ts) after a deassertion period of ts for the next bus transfer.

  Address Bus (addr [31: 2]) (Master → Slave) is determined at the same time as ts and held until one cycle after deassertion of ts.

  Master ID (mid [3: 0]) (Master → Slave) is an ID of a bus master performing access. Master ID (mid [3: 0]) is determined at the same time as ts and held until one cycle after deassertion of ts.

  Read (H) / Write (L) (rd_not_wr) (Master → Slave) indicates Read / Write of bus transfer. Read (H) / Write (L) is determined at the same time as ts and is held until one cycle after deassertion of ts. High: Read and Low: Write.

  Single or 2 beat Burst (one_not_two) (Master → Slave) indicates whether the bus transfer on the system bus 920 is a Single Transaction or a 2-beat Burst Transaction. In the case of Single, only the first 1-beat Data is valid. Single or 2 beat Burst (one_not_two) is determined at the same time as ts and held until one cycle after the deassertion of ts. High: Single, Low: 2 beat Burst.

  Read Data Byte Enable (rd_byte [3: 0]) (Master → Slave) indicates Byte Enable at the time of Read. Read Data Byte Enable (rd_byte [3: 0]) indicates to which byte position in the 32 bits the Read is read when one_not_two indicates Single. When one_not_two indicates 2 beat burst, all Read Data Byte Enable (rd_byte [3: 0]) must be set to Enable. wr_byteen [3: 0] is valid in Data Phase at Write, but Read Data Byte Enable (rd_byte [3: 0]) is valid in Address Phase at Read. Read Data Byte Enable (rd_byte [3: 0]) is determined at the same time as ts, and is held until one cycle after deassertion of ts.

  A 32-bit Data Bus, Write Data Bus (wr_data [31: 0]) (Master → Slave) is Write Data from the master to the slave. Write Data Bus (wr_data [31: 0]) is valid from the cycle following the cycle in which both ts and srdy are asserted. Further, Write Data Bus (wr_data [31: 0]) is valid only for the first 1-beat data during Single Transaction, and for both 1-beat and 2-beat data during 2 Beat Burst Transaction. Which Byte is valid is indicated by wr_byteen [3: 0]. Since the system bus 920 is Big Endian Bus, the MSB side is address 0.

  Write Data Byte Enable (wr_byte [3: 0]) (Master → Slave) indicates which byte position of Write Data is valid. Write Data Byte Enable (wr_byte [3: 0]) is valid from the cycle following the cycle in which both ts and srdy are asserted, as in wr_data [31: 0]. Further, Write Data Byte Enable (wr_byte [3: 0]) is effective only in the first 1-beat at the time of Single Transaction, and effective at both 1-beat and 2-beat at the time of 2 Beat Burst Transaction.

Correspondence with wr_data is as follows.
wr_byte [3] wr_data [31:24]
wr_byte [2] wr_data [23:16]
wr_byteen [1] wr_data [15: 8]
wr_byte [0] wr_data [7: 0]
Slave Ready (srdy) (Slave → Master) indicates that the slave Buffer is ready to receive a bus transfer from the master. If Slave Ready (srdy) is asserted, the master can initiate a bus transfer at any time and the slave must accept the bus transfer.

  Read Return Ready (rrdy) (Slave → Master) is a signal indicating Read Return from the slave. When the slave is ready for Read Data, the slave asserts Read Return Ready (rrdy) and starts Read Return. Read Return Ready (rrdy) may be asserted at any time. Read Data is returned in the same cycle as assertion of Read Return Ready (rrdy). If it is 2 beat Burst, Read Return Ready (rrdy) is asserted for 2 cycles, and Read data for 2 beats is returned. At that time, Read Return Ready (rrdy) does not need to be continuously asserted, and a wait cycle can be interposed therebetween.

  Return Master ID (rmid [3: 0]) (Slave → Master) is an ID of a master that should receive Read Return. It holds mid [3: 0] asserted when Read Request is received, and returns the same ID. The master decodes the Return Master ID (rmid [3: 0]) at the time of assertion of rs, and determines that the Read Return is the Read Return to itself when it is its Master ID. Return Master ID (rmid [3: 0]) is asserted simultaneously with rrdy.

  A 32-bit Data Bus and Read Data Bus (rd_data [31: 0]) (Slave → Master) is Read Data from the slave to the master. Valid data is returned in the cycle in which rrdy is asserted.

  Read Error (rd_error) (Slave → Master) notifies the master of an error from the slave. When an error occurs, the slave asserts Read Error (rd_error) in the same cycle as rrdy at Read Return.

  The above is the description of the signal.

  Next, the transaction type will be described.

  In the system bus 920, both Read Write and Single Beat Transaction and 2-beat Transaction exist.

  Switching between Single Transaction and 2-beat Transaction is performed by one_not_two.

one_not_two Access Size
0 2 beat
1 single
All bus transfers (bytes, half words) of 32 bits (4 bytes) or less are performed by single bus transfer. In the case of Write, control is performed in wr_byte [3: 0], and in the case of Read, control is performed in rd_byte [3: 0]. Do.
At the time of 2-beat burst read, all rd_byteen [3: 0] must be enabled.
In addition, at the time of 2-beat burst access, the address must be aligned with a 64-bit boundary. That is, addr [2] is 0.

  Next, the write transaction will be described with reference to FIG.

  The basic protocol is as follows.

  In cycle-2, the master asserts ts corresponding to the target slave when starting a write bus transfer. At the same time, one_not_two, mid [3: 0], addr [31: 2] are asserted.

  In cycle-3, since srdy corresponding to the target slave is asserted, the write bus transfer is started, and the master deasserts ts. Further, the master asserts wr_data [31: 0] and wr_byte [3: 0], and outputs Write Data for the first beat.

  In cycle-4, the master deasserts one_not_two, mid [3: 0], addr [31: 2]. Further, the master switches wr_data [31: 0] and wr_byte [3: 0], and outputs the second beat Write Data.

  In cycle-5, the write bus transfer ends.

  Even if the master asserts ts, if srdy is deasserted (cycle-8), the master continues to assert ts. When srdy is asserted (cycle-9), ts is deasserted (cycle-10).

The master can assert again after a one-cycle deassertion period of ts to initiate the next bus transfer. (Cycle-11)
When the write bus transfer is continuous and the interval between the bus transfers is clogged, the data can be continuously written without leaving an interval.

  Next, Read transaction will be described with reference to FIG.

  Read bus transfer is divided into read command bus transfer from the master to the slave, and read return of the read data from the slave to the master. Each is independent, and the signal lines are also independent.

  The basic protocol is as follows.

  In cycle-2, the master asserts ts corresponding to the target slave when it starts Read bus transfer. At the same time, one_not_two, rd_not_wr, rd_byte [3: 0], mid [3: 0], addr [31: 2] are asserted.

  In cycle-3, since srdy corresponding to the target slave is asserted, Read bus transfer starts and ts is deasserted.

  In cycle-4, the master deasserts one_not_two, rd_not_wr, rd_byte [3: 0], mid [3: 0], addr [31: 2].

  The completion of Read Command bus transfer of Read bus transfer is as follows.

  In cycle-6, when the slave is ready for Read Data, it asserts rrdy and rmid [3: 0] and starts Read Return. In rmid [3: 0], the Master ID received from the master by Read Command is placed.

  Also, rd_data [31: 0] is asserted, and Read Data of the first Beat is output.

  Next, in cycle-7, the slave deasserts rrdy. Deassert rmid [3: 0].

  In cycle-8, the slave asserts rrdy again. Here, one cycle wait is included, but any wait cycle can be inserted. Also, Read data of the second beat is output to rd_data [31: 0].

  In cycle-9, the slave deasserts rrdy. The slave also deasserts rmid [3: 0].

  In cycle-10, Read Return ends.

Even if the master asserts ts, if srdy is deasserted (cycles -8, 9), the master continues to assert ts. When srdy is asserted, ts is deasserted. (Cycle-10)
The master can assert again after a one-cycle deassertion period of ts to initiate the next bus transfer. (Cycle-11)
The slave can continuously assert rrdy to start the next Read Return when there is more Data to Return. (Cycle-16)
When Read bus transfer continues, Data can continue to be read without leaving an interval on the read data bus.

  Next, an actual operation will be described as an example to describe the first embodiment of the present invention.

  FIG. 10 shows a timing chart when the processor 901 and the printer controller 906 in FIG. 9 simultaneously read from the memory controller 902. The correspondence between the physical address and the bank address, row address, and column address of the memory device is as shown in FIG.

  Hereinafter, the processor 901 is called a master 1, the printer controller 906 is called a master 2, and the memory controller 902 is called a slave.

  In FIG. 10, first, the master 1 starts transfer (cycle 1). The slave asserts srdy and accepts this command. The address is 0x00004000. Although not shown due to space limitations, this command is read (rd_not_wr = 1) and 2 beats (one_not_two = 0).

  At the same time, the master 2 starts transfer (cycle 2). The slave asserts srdy and accepts this command (cycle 4). The address is address 0x00037bfc. This command is also a 2-beat read command.

  Thereafter, in the same manner, the slave receives 2-beat read commands from the master 2 and the master 1 to the address 0x00037c00 and the address 0x000000410, respectively.

  When the memory controller 902 accepts the read command, it temporarily stores it in the command queue (702 in FIG. 1), and accesses the memory 904 in the accepted order. I do. In this embodiment, since the system bus is composed of 32 bits, access is performed in units of 32 bits. Since the bus width of the memory 904 is 16 bits, it issues a 2-beat read access to the memory, and operates to collect the read results into 32 bits and return them to the master. Here, it should be noted that the memory 904 is composed of DDR SDRAM.

  That is, in the 2-beat access to the memory 904, data is transferred by one system bus clock.

  In the DDR memory, access to the same page of the same device or a page existing in another bank of the same device can be performed in a continuous cycle.

  Now, the address 0x00004000 which is the address of the first read request of the master 1 and the address 0x00037bfc which is the address of the first read request of the master 2 are in the same device (same chip select) and in pages existing in different banks.

  Therefore, these pages can be accessed in a continuous cycle.

  Therefore, in the memory controller 902 according to the first embodiment of the present invention, each 2-beat (32 bits × 2 = 64 bits) access from the master 1 and the master 2 is divided into 32-bit access, It works to do them alternately. Even in this way, each memory access can be performed in a continuous cycle, so that no wasteful waiting cycle occurs.

  FIG. 11 shows the timing relationship on the system bus and the memory bus at this time. As shown here, the memory controller 902 generates a plurality of commands whose transfer unit is smaller than the transfer unit (64 bits) of the memory access request. When a memory access request is made from a plurality of request sources (masters 1 and 2), the memory controller 902 issues a plurality of commands to the memory 904 alternately for each request source. In this way, a plurality of memory access requests are executed in a time division parallel manner. Note that the memory controller 902 issues a plurality of commands alternately to the memory 904 for each request source only when the memory access request is a memory read request. The command queue 701 (FIG. 1) stores received memory access requests in order, and only the first and second access requests in the command queue 701 are candidates for alternately issuing the plurality of commands.

  As a result of the operation described above, in cycle 11, the slave asserts rrdy and returns a read return of 1 beat. At this time, MID = 1, and the master 1 receives this read return. Then in cycle 12, the slave asserts rrdy and returns a 1-beat read return. At this time, MID = 2, and the master 2 receives this read return.

  The next cycle 13 includes one wait cycle, which depends on the internal timing generation method in the implementation of the memory controller in this embodiment, but is not directly related to the description of the present invention. Description is omitted. Of course, this cycle is not necessary depending on the mounting method of the memory controller.

  Further, in cycle 14, the slave asserts rrdy and returns a one-beat read return. At this time, MID = 1, and the master 1 receives this read return, which is data of the second beat for the first read access request issued by the master 1. Then in cycle 15, the slave asserts rrdy and returns a 1-beat read return. At this time, MID = 2, and the master 2 receives this read return. This is the second beat data for the first read access request issued by the master 2.

  That is, in the conventional example, the first read return data for the master 2 is the 13th to 14th cycles after all the read returns for the access request of the master 1 are completed. On the other hand, in the first embodiment of the present invention, the first read return data is returned to the master 2 in a cycle earlier than that.

  Thereafter, similarly, in response to the second read access request of the masters 1 and 2, 1-beat data is alternately returned for each master in cycles 22, 23, 25, and 26.

  In this way, in the first embodiment of the present invention, when memory access requests are simultaneously generated from a plurality of masters in the system LSI, those transfer units are divided and memory access is performed alternately. As a result, the average latency of the first return data for each master can be reduced.

  Therefore, it is possible to reduce the capacity of the FIFO required for each, and the circuit scale can be suppressed.

  Although the present invention has been shown and described with respect to particular embodiments, further modifications and improvements are possible.

  For example, in the first embodiment of the present invention, the burst transfer of the system bus has been described for the case of 1 beat to 2 beats for the sake of simplicity, but the present invention is not limited to this. In fact, it should be understood that the longer the beat length, the more pronounced the effect of the present invention.

  For example, in the first embodiment of the present invention, the case where the beat length when accessing the memory device is 2 has been described. However, the present invention can be applied to any beat length.

  Next, a second embodiment of the present invention will be described. The block diagram of the present embodiment, the diagram explaining the configuration of the system LSI 800, and the details of the memory controller are the same as those in FIGS. 8, 9, and 1, respectively.

  12 and 13 are diagrams for explaining the bus protocol of the system bus 920 in the second embodiment of the present invention. FIG. 12 shows read transfer, and FIG. 13 shows write transfer. As described above, the system bus 920 has a multi-layer configuration, and can be regarded as being connected one-to-one with an arbitrary bus slave when viewed from the bus master.

Hereinafter, signals constituting the system bus 902 will be described. However, in the present embodiment, description of signals constituting the system bus 902 is omitted for signals common to the first embodiment.
b_size [3: 0] Access Size Master → Slave
Burst size (b_size [3: 0]) (Master → Slave) indicates the number of bus transfer bursts on the system bus 920. 1 to 16 beats can be specified. It is determined at the same time as ts and held until one cycle after the deassertion of ts.

  0000 is 1 beat, 0001 is 2 beat, and 1111 is 16 beat.

  Read Data Byte Enable (rd_byte [3: 0]) ((Master → Slave)) indicates Byte Enable at the time of Read.

  When b_size [3: 0] indicates Single, it indicates which byte position in the 32 bits is Read. When b_size indicates 2 beat burst or more, this signal is invalid and is treated as all enabled. wr_byteen [3: 0] is valid in Data Phase at Write, but Read Data Byte Enable (rd_byte [3: 0]) is valid in Address Phase at Read. Read Data Byte Enable (rd_byteen [3: 0]) is determined at the same time as ts and held until one cycle after the deassertion of ts.

  Next, the write transaction will be described with reference to FIG.

  The basic protocol is as follows.

  In cycle-2, the master asserts ts corresponding to the target slave when starting a write bus transfer. At the same time, b_size [3: 0], rd_not_wr, mid [3: 0], and addr [31: 2] are asserted.

  In cycle-3, since srdy corresponding to the target slave is asserted, the write bus transfer starts and the master deasserts ts. In addition, the master asserts wr_data [31: 0] and wr_byte [3: 0] and outputs Write Data for the first beat.

  In cycle-4, the master deasserts b_size [3: 0], rd_not_wr, mid [3: 0], addr [31: 2]. In addition, the master switches wr_data [31: 0] and wr_byte [3: 0], and outputs the second beat Write Data.

  In cycle-5, the Write bus transfer ends.

Even if the master asserts ts, if srdy is deasserted (cycles -8, 9), the master continues to assert ts. When srdy is asserted, ts is deasserted. (Cycle-10)
The master can assert again after a one-cycle deassertion period of ts to initiate the next bus transfer. (Cycle-11)
When the write bus transfer is continuous and the interval between the bus transfers is clogged, the data can be continuously written without leaving an interval.

  Next, Read transaction will be described with reference to FIG.

  Read bus transfer is divided into read command bus transfer from the master to the slave, and read return of the read data from the slave to the master. Each is independent, and the signal lines are also independent.

  The basic protocol is as follows.

  In cycle-2, when the master starts Read bus transfer, it asserts ts corresponding to the target slave. At the same time, the master asserts b_size [3: 0], rd_not_wr, rd_byteen [3: 0], mid [3: 0], addr [31: 2].

  In cycle-3, since srdy corresponding to the target slave is asserted, Read bus transfer starts, and the master deasserts ts.

  In cycle-4: the master deasserts b_size [3: 0], rd_not_wr, rd_byteen [3: 0], mid [3: 0], addr [31: 2].

  The completion of Read Command bus transfer of Read bus transfer is as follows.

  In cycle-6, when the slave is ready for Read Data, it asserts rrdy and rmid [3: 0] and starts Read Return. In rmid [3: 0], the Master ID received from the master by Read Command is placed.

  Further, the slave asserts rd_data [31: 0] and outputs Read Data of the first beat.

  In cycle-7, the second beat Read Data is output to rd_data [31: 0].

  In cycle-10, the slave deasserts rrdy. The slave also deasserts rmid [3: 0].

  In cycle-10, Read Return ends.

Even if the master asserts ts, if srdy is deasserted (cycles -8, 9), the master continues to assert ts. When srdy is asserted, ts is deasserted. (Cycle-10)
The master can assert again after a one-cycle deassertion period of ts to initiate the next bus transfer. (Cycle-11)
The slave can continuously assert rrdy to start the next Read Return when there is more Data to Return. (Cycle-16)
When the read bus transfer is continued, it is possible to continue reading data without leaving an interval on the read data bus.

  Next, an embodiment of the present invention will be described by taking an actual operation as an example.

  FIG. 14 shows a timing chart when the processor 901 and the printer controller 906 in FIG. 9 simultaneously read from the memory controller 902. The correspondence between the physical address and the bank address, row address, and column address of the memory device is as shown in FIG.

  Hereinafter, the processor 901 is called a master 1, the printer controller 906 is called a master 2, and the memory controller 902 is called a slave.

  In this embodiment, the master 2 is given higher priority than the master 1. In the present embodiment, the method of giving priority will not be described in detail, but it may be fixed in advance or configured so that it can be dynamically specified at the time of execution.

  In FIG. 14, first, the master 1 starts transfer (cycle 1). The slave asserts srdy and accepts this command. The address is 0x00004000. Although not shown due to space limitations, this command is read (rd_not_wr = 1) and 8 beats (b_size = 0111). At the same time, the master 2 starts transfer (cycle 2). The slave asserts srdy and accepts this command (cycle 4). The address is address 0x00037bfc. This command is also an 8-beat read command.

  When the memory controller 902 accepts the read command, it temporarily stores it in the command queue (702 in FIG. 1). Here, the bank collision is judged. In this example, since there is no bank collision in the memory access of the master 1 and the master 2, the memory 904 is accessed in the accepted order. If the memory access of the master 1 causes a bank collision and the memory access of the master 2 does not cause a bank collision, the memory access request of the master 2 is processed first.

  In the present embodiment, since the system bus is composed of 32 bits, the master performs access in units of 32 bits on the system bus. Since the bus width of the memory 904 is 64 bits, it corresponds to 8-beat transfer on the system bus, and the memory controller 902 issues 4-beat read access to the memory 904, and the read result is sent to the master every 32 bits. Operates to return.

  Here, it should be noted that the memory 904 is composed of DDR SDRAM. That is, in the 2-beat access to the memory 904, data is transferred by one system bus clock.

  In the DDR memory, access to the same page of the same device or a page existing in another bank of the same device can be performed in a continuous cycle.

  Now, the address 0x00004000 which is the address of the first read request of the master 1 and the address 0x00037bfc which is the address of the first read request of the master 2 are in the same device (same chip select) and in pages existing in different banks. Therefore, these pages can be accessed in a continuous cycle.

  FIG. 16 shows the timing relationship on the system bus and the memory bus at this time.

  In FIG. 16, the memory controller 902 according to one embodiment of the present invention first issues a read command to the memory 904 in cycle 4 in response to an 8-beat (32 bits × 8 = 256 bits) access from the master 1. . Transfer of 64 bits × 4 beats is performed on the memory bus, and the read data is temporarily stored in the read data buffer 704 (FIG. 1) (cycle 8 to cycle 11). At the same time, the prepared data is returned to the master 1 in order of 32 bits (cycle 9 to cycle 12).

  During this time, the memory controller 902 issues a read command to the memory 904 again in cycle 8 in order to process an access of 8 beats (32 bits × 8 = 256 bits) from the subsequent master 2. As a result, a transfer of 64 bits × 4 beats is performed on the memory bus subsequent to the previous transfer (cycle 12 to cycle 15). At this time, since the priority of the master 2 is higher than that of the master 1, when the first read data is read in the cycle 12, the memory controller 902 interrupts the read return to the master 1, and from the cycle 13 to the master 2 Operates to return read data. When all the 8-beat read / return operations for the master 2 are completed, the memory controller 902 resumes the read / return operation to the master 1 from the cycle 21. That is, in this embodiment, read data obtained as a result of accessing the memory 904 in accordance with read requests from a plurality of request sources (masters 1 and 2) is stored in the read data buffer 704, and read data is read from the read buffer 704 by a plurality of requests. Transfer in the order according to the priority set in the original (master 1, 2). In addition, the received read requests are sequentially stored in the command queue 702, and a command is extracted from the command queue 702 so as to avoid a bank collision, and the memory 904 is accessed.

  As described above, the first read return data for the master 2 is returned before all the read returns for the access request of the master 1 are completed (before the cycle 17).

  As described above, in the second embodiment of the present invention, even when memory access requests from a plurality of masters in the system LSI compete with each other, the memory access efficiency is not lowered, and at the same time, the priority is high. An increase in the memory access latency of the master can be suppressed.

  Although the present invention has been shown and described with respect to particular embodiments, further modifications and improvements are possible.

  For example, in the second embodiment of the present invention, the case where a bus having a specific signal and protocol is used as the system bus has been described. However, the present invention is not limited to this, and an arbitrary bus is used as the system bus. It may be configured. Further, a plurality of memory controller bus interfaces may be provided as necessary.

  Also, for example, in the second embodiment of the present invention, the method for setting the priority between masters has not been described in detail for the sake of simplicity. For example, a system bus having a priority signal is used. Alternatively, priority may be given in units of transfer.

  For example, in the first and second embodiments of the present invention, the case where a DDR SDRAM is used as a memory device has been described as an example, but the present invention is not limited to this.

  Further, for example, in the second embodiment of the present invention, the case where the beat length when accessing the memory device is 8 has been described, but any beat length can be applied.

  Accordingly, the invention is not limited to the specific forms shown in the foregoing embodiments, and covers all modifications that do not depart from the spirit and scope of the invention in the appended claims. It should be understood that

It is a figure explaining the structure of the memory controller in 1st Example of this invention. It is a figure explaining one structural example of a prior art example. It is a figure explaining the composite operation | movement sequence of an embedded device. It is a figure explaining the usage method of the memory in a prior art example. It is a figure explaining the protocol of the system bus | bath in 1st Example of this invention. It is a figure explaining the protocol of the system bus | bath in 1st Example of this invention. It is a figure explaining one structural example of a prior art example. It is a figure explaining the system configuration | structure of the 1st Example of this invention. It is a figure explaining the system LSI of 1st Example of this invention. It is a figure explaining the operation timing on the system bus in the 1st example of the present invention. It is a figure explaining the operation timing on a system bus and a memory bus in the 1st example of the present invention. It is a figure explaining the protocol of the system bus in one Example of this invention. It is a figure explaining the protocol of the system bus in one Example of this invention. It is a figure explaining the operation timing on the system bus in one Example of this invention. It is a figure explaining an example of the relationship between a physical address, a bank address, a row address, and a column address. It is a figure explaining the operation timing on a system bus and a memory bus in one example of the present invention.

Claims (9)

Receiving means for receiving a plurality of read requests from a plurality of request sources ;
Access means for accessing the memory according to the read request received by the receiving means ;
Storage means for storing read data as a result of access by the access means;
Transfer means for transferring the read data stored in the storage means to the request source that requested the read data;
During the data transfer to the first request source by the transfer means , the storage means stores the read data to the second request source having a higher priority than the first request source. A memory control device, wherein data transfer to a first request source is interrupted and data transfer to the second request source is started . 2. The command queue according to claim 1, further comprising a command queue for storing the plurality of read requests in the order of acceptance, wherein the access unit retrieves a command from the command queue and accesses the memory so as to avoid a bank collision. Memory controller. Receiving a plurality of read requests from a plurality of request sources ;
An access step of accessing the memory according to the read request received in the reception step ;
A storage step of storing read data as a result of access in the access step ;
A transfer step of transferring the read data stored in the storage step to a request source that requested the read data;
In the transfer step, if read data to a second request source having a higher priority than the first request source is stored during data transfer to the first request source, data to the first request source is stored. A memory control method characterized by interrupting transfer and starting data transfer to the second request source . An embedded device including a memory controller, a system bus, and a memory,
The memory controller includes: a receiving unit that receives a plurality of read requests from a plurality of request sources; an access unit that accesses a memory in accordance with the read request received by the receiving unit; and read data obtained as a result of accessing by the access unit A buffer for temporarily storing; and a transfer means for transferring the read data stored in the buffer to the request source that requested the read data. During the data transfer to the first request source by the transfer means When the buffer stores the read data to the second request source having a higher priority than the first request source, the transfer means interrupts the data transfer to the first request source, and the second request source Embedded system characterized by initiating data transfer to the requester . 5. The memory controller according to claim 4, further comprising a command queue for sequentially storing received read requests, wherein the access means takes out a command from the command queue and accesses the memory so as to avoid a bank collision. The described embedded system. 5. The embedded system according to claim 4, wherein the system bus transfers an identifier of the bus master to the slave, and the slave returns the identifier together with the identifier of the bus master when returning read data to the bus master. The embedded system according to claim 4, wherein the memory is constituted by a DDR SDRAM. The embedded system according to claim 4, wherein the system bus has a multilayer structure. 5. The embedded system according to claim 4, wherein the memory controller and the system bus are built in one system LSI.

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