JP3425421B2 - Multiprocessor system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors and a shared memory are connected via an address bus and a data bus.

[0002]

2. Description of the Related Art A multiprocessor which accesses a shared memory having only one bank is disclosed in, for example, April 20, 1990.
It is conventionally known from pages 25 to 32 (hereinafter referred to as document 1) of "Computer System Research Group Report" CPSY90-4 issued by the Institute of Electronics, Information and Communication Engineers on the day.

According to this document 1, after a transmission unit such as a processor transmits an order (address / data), the system bus is temporarily released, and a reception unit obtains a right to use the system bus when an answer is ready. , Has proposed a split method of sending an answer back to the transmitting unit.

Further, this document 1 assumes that an order is sent from a plurality of units such as a processor, a memory device, an input / output device, etc., and stores a plurality of orders and answers in a system bus interface control circuit (communication). It is proposed to provide a buffer), and more specifically, this system bus interface control circuit is provided in the bus input / output unit of the processor unit.

In this way, another data transfer such as an address transfer from the unit C to the unit B is executed between the address transfer from the unit A to the unit B and the data transfer from the unit B to the unit A. be able to.

As a result, one unit does not monopolize the shared system bus for a long time, so that high transfer capability can be expected in a multiprocessor system.

On the other hand, in "Computer Architecture" pages 179 to 184 (hereinafter referred to as reference 2) issued by Ohmsha Co., Ltd. on August 30, 1988, the memory access precedes the completion of the memory access. Unnecessary memory access pipeline processing is disclosed, in which the memory is divided into a plurality of banks, and an access queue is provided to buffer access requests input one after another and read results output one after another. It is disclosed to add a data queue and a memory.

In this way, if adjacent access requests access different banks of the memory, it is not necessary for the subsequent requests to wait for the completion of the previous request, so that high speed memory access can be achieved.

Reference 2 also discloses hardware that enables pipeline access to a memory divided into a plurality of banks. As this hardware,
Pipeline access has been proposed in which a plurality of memory address registers and a plurality of data latches are arranged corresponding to a plurality of banks.

[0010]

However, in the prior art described in the above-mentioned Document 1, there is only one bank of shared memory, and the address and data are multiplexed and transferred to the system bus in a time-shared manner. Therefore, in this case, it was made clear by the study of the present inventors that the throughput of access to the shared memory from a plurality of processors is low.

Further, in the prior art described in the above-mentioned document 2, since only one memory address register is arranged in one bank of the memory, adjacent access requests from the processors are the same bank of the memory. It has been clarified by the inventors of the present invention that the subsequent access requests have to wait until the completion of the previous access request, and in this case, the access throughput decreases.

Therefore, it is an object of the present invention to improve the throughput of access from a plurality of processors to a shared memory and to allow adjacent access requests from the processors to continuously access the same bank of the shared memory. Even in the case of doing so, it is to provide a multiprocessor system in which the subsequent access request does not have to wait for the completion of the earlier access request.

[0013]

Among the inventions disclosed in the present application, typical features of the invention are as follows.

That is, (1) address bus (170)
And (2) a data bus (180), (3) a plurality of processors connected to the address bus (170) and the data bus (180), and sending an access request address to the address bus (170) ( 110, 120)
(4) A plurality of access queues (13) connected to the address bus (170) and the data bus (180)
5, 145, 155, 165) and (5) a shared memory (130, 130) divided into a plurality of banks corresponding to the plurality of access queues (135, 145, 155, 165).
140, 150, 160) and the plurality of access queues (135, 145, 155, 165)
Comprises a first in first out (FIFO) memory for buffering a plurality of access request addresses (410) transmitted via the address bus (170).

According to a preferred embodiment of the present invention, when the plurality of processors send an access request address to the address bus, the processor identification number and a read / write signal of an access request are sent to the address bus. And the above-mentioned FIF that constitutes the above-mentioned plurality of access queues.
The O memory further buffers read / write signals of a plurality of access requests, processor identification numbers of access requests, and write data of write access requests,
When one bank of the shared memory sends data to the data bus, the corresponding one FIFO memory sends the buffered processor identification number to the data bus.

According to a preferred embodiment of the present invention, the plurality of processors send a first circuit for holding the processor identification number sent to the address bus and the one bus from the one FIFO memory to the data bus. A second processor for comparing the processor identification number stored in the first circuit with the stored processor identification number, and instructing latching of data on the data bus into the processor when both processor identification numbers match. And a circuit.

According to a more specific embodiment of the present invention,
A first arbiter is connected to the address bus to determine a bus right to use the address bus in response to a request on the address bus, and a bus right to use the data bus in response to the request on the data bus. The second arbiter to be determined is connected to the data bus.

According to the above-described representative embodiment of the present invention, since the shared memory is divided into a plurality of banks, a separate bus system in which the address bus and the data bus are physically separated is adopted. Therefore, the throughput of access from the plurality of processors to the shared memory divided into the plurality of banks can be significantly improved.

Furthermore, regarding a plurality of access request addresses to the shared memory buffered in the FIFO memory, after the bus use right of the data bus is acquired on a first-in first-out basis, data transfer between the bank of the shared memory and the processor is performed one after another. Therefore, even if adjacent access requests continuously access the same bank of shared memory, subsequent access requests do not have to wait for the completion of data transfer of the previous access request, and throughput is significantly improved. Can be done.

According to the more preferred embodiment of the present invention, a plurality of processors that access the shared bus are assigned processor ID (identification) numbers in advance, and the ID numbers are output at the same time when the address is sent, Since the data reception is also controlled by this ID number, even if a plurality of accesses are buffered on the shared memory side, each processor does not confuse the data.

According to the above specific embodiment of the present invention,
Since the data bus and the address bus each have a dedicated arbiter circuit that determines the right to use the bus, the source of the data bus can be determined independently of the address bus, and the transfer of read data is independent of the address bus. This can be done using only the data bus.

Other objects and features of the present invention will be apparent from the following examples.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of a multiprocessor system which is an embodiment of the present invention.

System Outline A multiprocessor system according to an embodiment of the present invention shown in FIG.

Address bus 170 and data bus 180
And the first and second processors 110 and 120 connected to the address bus 170 and the data bus 180 and sending the access request address to the address bus 170, and the four accesses connected to the address bus 170 and the data bus 180. Shared memories 130, 14 divided into four banks corresponding to the queues 135, 145, 155, 166 and the four access queues (135, 145, 155,).
0, 150, and 160, and the four access queues 135, 145, 155, and 165 buffer the plurality of access request addresses 410 transmitted via the address bus 170, and first-in first-out (FIFO).
It is characterized by being composed of a memory.

Therefore, the two processor elements 11
0 and 120 are memories 130 divided into four banks,
140, 150, 160 are connected to each other via an address bus 170, a data bus 180, and four access queues 135, 145, 155, 165 composed of FIFO memories.

In this way, the shared memories 130, 140,
Since 150 and 160 are divided into multiple banks,
further. Since the address bus 170 and the data bus 180 are physically separated from each other, the shared bus system is accessed from the plurality of processors 110 and 120 to the shared memories 130, 140, 150 and 160 divided into a plurality of banks. Throughput can be significantly improved.

Further, the shared memories 130, 140, 15 buffered in the four access queues 135, 145, 155, 165 composed of FIFO memories.
Regarding multiple access request addresses to 0,160,
After the bus usage right of the data bus is acquired on a first-in first-out basis, data transfer between the banks of the shared memories 130, 140, 150, 160 and the processors 110, 120 is executed one after another, so that adjacent access requests are shared. Even if the same bank is continuously accessed, the subsequent access request does not have to wait for the completion of the data transfer of the previous access request, and the throughput can be remarkably improved.

Hereinafter, each component of the processor system shown in FIG. 1 will be described in detail.

Processor Element (PE) Configuration Processor element 110 is a central processing unit (CPU).
1) 111 and instruction cache (IC1) 112, operand cache (OC1) 113, instruction bus 114, and operand bus 115, which are connected as shown in FIG.

The instruction cache IC1 (112) of the PE is searched by the address of the instruction fetch request of the CPU1 (111), and a copy of the corresponding instruction data is obtained as the instruction cache I.
It is determined whether or not it exists in C1 (112).

When the requested instruction exists in the instruction cache (hits), the shared memory 13 outside the PE is used.
The instruction data is read from the instruction cache IC1 (112) and transferred to the CPU 1 using the instruction bus 114 without being accessed.

When a copy of the instruction data corresponding to the instruction fetch request from the central processing unit CPU1 (111) does not exist (misses) in the instruction cache IC1 (112), the instruction cache IC1 (112) is external. The memory 130, 140, 150, 160 of the above to read the corresponding data, and execute the instruction cache IC1 (112).
Store the read data to the instruction bus 1 at the same time
14 to the central processing unit CPU1.

The central processing unit CPU1 (111) is an instruction cache IC1 (112) or an external memory 130,1.
The instruction data read from 40, 150, 160 is decoded as an instruction, and the instruction is executed according to the instruction.

Similar to the PE operand cache instruction cache IC1 (112), the operand cache OC1 (113) also has a central processing unit CPU1 (11).
It is determined whether or not a copy of the corresponding operand data, which is searched by the address of the operand access request of 1), exists in the operand cache OC1 (113).

When the requested operand data exists in the operand cache, the shared memory memories 130, 140, 150 and 160 outside the PE are not accessed and the operand data is read from the operand cache OC1 (113). Bus for operand 1
15 is used to transfer to the CPU 1.

When a copy of data corresponding to the operand access request from the central processing unit CPU1 (111) does not exist in the operand cache OC1 (113) (misses), the operand cache OC1 (11).
3) accesses the external memories 130, 140, 150, 160, reads the corresponding data, stores it in the operand cache OC1 (113), and at the same time, transfers it to the central processing unit CPU1 using the operand bus 115.

The central processing unit CPU1 (111) uses the operand cache OC1 (113) or the external memory 13
Instructions are executed using the data read from 0, 140, 150, 160 as an operand.

Like the processor element 110, the processor element 120 also has a central processing unit (CPU2).
121 and an instruction cache (IC2) 122, an operand cache (OC2) 123, an instruction bus 124, and an operand bus 125, which are connected as shown in FIG. 1, and their operations are similar to those of the processor element 110.

Shared Memory and Access Queue Shared memory consists of four banks 130, 140, 150, 1
It is divided into 60, and access queues 135 and 14
5, 155, 165, address bus 170, data bus 180, processor elements 110, 120
It is connected to the.

Access queues 135, 145, 155,
Reference numeral 165 denotes a first in first out (FIFO) that latches memory access requests from the instruction caches (IC1, IC2) 112, 122 and the operand caches (OC1, OC2) 113, 123 of the processor elements 110, 120. Is the buffer.

Bus Abiters Abiters 190 and 195 are address buses 17 respectively.
0 is an arbitration circuit that determines the bus right of 0 and the data bus 180.

Configuration of Address Bus FIG. 2 is a diagram illustrating in detail the configuration of address bus 170 shown in FIG.

The address bus 170 is the request signal line 2
10 and grant signal line 220, address signal line 23
0, read / write signal line 240, ID number signal line 25
It consists of zero.

FIG. 2 shows the instruction cache 1 (IC1) 112.
Although only the 0th bank memory (SC0) 130 is described, as is apparent from FIG. 1, another instruction cache (122) or operand cache (113, 123) and another bank memory (140, 150). , 160) are similarly connected.

The eight request signal lines 210 and the eight grant signal lines 220 are connected to the instruction cache IC1 (11
2), IC2 (122), operand cache OC1 (1
13), OC2 (123), memory bank SC0 (13
0), SC1 (140), SC2 (150), SC3 (16
It corresponds to the device 0). That is, each of the signal lines 210 and 220 is connected to each of the above devices.
It corresponds to one-to-one.

The ID number signal line 250 is composed of three signal lines for identifying the above eight devices.

The instruction cache IC1 (112) is a memory
The operation of each component will be described below by taking as an example the case where the reading of the data in the bank SC0 (130) is activated.

The instruction cache IC1 (112) first obtains a bus right which is a right to use the address bus 170. Therefore, one signal corresponding to the instruction cache IC1 (112) of the eight request signal lines 210 is used. Assert the line.

After asserting one signal line corresponding to the request signal line 210, the instruction cache IC1 (112) monitors the signal line corresponding to itself in the grant signal line 220, and the address bus arbiter 190 Waiting for the bus right.

The arbiter 190 for the address bus checks all the signal lines (8 lines) of the request signal line 210,
Depending on the priority of the device requesting the bus right,
Give bus right. It is now assumed that the bus right can be given to the instruction cache IC1 (112). The address bus arbiter 190 asserts one signal line of the eight grant signal lines 220 corresponding to the instruction cache IC1 (112) to give the bus right.

The instruction cache IC1 (112) acquires the bus right when the signal line corresponding to itself in the grant signal line 220 is asserted, and acquires the address signal line 230, the read / write signal line 240, and the ID number signal. Send a predetermined value on line 250. Here, in the ID number signal line 250,
The ID number of the instruction cache IC1 (112) is output.

The access queue 135 for the memory bank SC0 (130) is the lower 2 bits of the address signal line 230.
It is determined from the bit that the access is to the memory bank SC0 (130), and the address signal line 230, read / read
The contents of the write signal line 240 and the ID number signal line 250 are latched. The access requests latched in the access queue 135 are sequentially processed when the memory bank SC0 (130) becomes accessible.

Structure of Data Bus FIG. 3 is a detailed diagram illustrating in detail the structure of the data bus 180 shown in FIG.

The data bus 180 is the request signal line 3
10 and grant signal line 320, data signal line 330,
It comprises an ID number signal line 350.

FIG. 3 shows the instruction cache 1 (IC1) 11
Although only the memory (SC0) 130 of the 2nd and 0th banks is described, as is apparent from FIG. 1, another instruction cache (122) and an operand cache (113, 12).
3) and other banks of memory (140, 150, 160)
Are connected as well.

The eight request signal lines 310 and the eight grant signal lines 320 are connected to the instruction cache IC1 (11
2), IC2 (122), operand cache OC1 (1
13), OC2 (123), memory bank SC0 (13
0), SC1 (140), SC2 (150), SC3 (16
It corresponds to the device 0). That is, each signal line 310, 320 is connected to each of the above devices.
It corresponds to one-to-one.

ID number signal line 25 of the address bus 170
As with 0, the ID number signal line 350 of the data bus 180
Consists of three signal lines.

The operation of each component will be described below by taking as an example the case where the data read from the memory bank SC0 (130) is transferred to the instruction cache IC1 (112) in accordance with the request of the instruction cache IC1 (112). explain.

The memory bank SC0 (130) first acquires the bus right that is the right to use the data bus 180. Therefore, one of the eight request signal lines 310 corresponding to the memory bank SC0 (130) is used. Assert the signal line of.

After asserting one signal line corresponding to the request signal line 310, the memory bank SC0 (130) monitors the signal line corresponding to itself among the grant signal lines 320, and by the data bus arbiter 195. Waiting for the bus right.

The arbiter 195 for the data bus checks all the signal lines (8) of the request signal line 310 and gives the bus right to the device requesting the bus right according to the priority order. Now, assume that the bus right can be given to the memory bank SC0 (130). The arbiter 195 for the address bus corresponds to the memory bank SC0 (130) of the eight grant signal lines 320.
The bus right is given by asserting the signal line of the book.

The memory bank SC0 (130) acquires the bus right when the signal line corresponding to itself among the grant signal lines 320 is asserted, and the data signal line 330 and the ID number signal line 350 have predetermined values. Is sent. Here, the ID number signal line 350 has the instruction cache IC1 which is the access request source latched in the access queue 135.
The ID number of (112) is output.

On the other hand, the instruction cache IC1 (112) releases the address bus 170 after sending the address, monitors the ID number signal line 350 of the data bus 180, and reads the read data from the memory bank SC0 (130). Waiting to be transferred. Therefore, the instruction cache IC1
(112) detects the ID number sent from the memory bank SC0 (130), and the instruction cache IC1 (112)
The data on the data signal line 330 is latched after confirming that it is a response cycle to.

Configuration of Access Queue FIG. 4 is a detailed diagram for explaining the configuration of the access queue shown in FIG. 1, which is one of the access queues (AQ0) 1.
35 will be described in detail. Other access queue (AQ1) 1
45, (AQ2) 145, and (AQ3) 165 have the same configuration as the access queue (AQ0) 135.

The access queue 135 is a 4-entry first-in first-out (FIFO) buffer. Each entry has an address part 410 and a read / write part 420, I.
It comprises a D number section 430 and a write data section 440. The address section 410 latches the contents of the address signal line 230 of the address bus 170, the read / write section 420 similarly latches the contents of the read / write signal line 240, and
The D number section 430 latches the content of the ID number signal line 250, and the write data section 440 latches the content (write data) of the data signal line 330 of the data bus 180 when writing to the memory.

A memory access request to the memory bank SC0 (130) from a device such as the instruction cache IC1 (112) is once latched in the access queue 135. Therefore, the address bus 170 can be opened to other devices without waiting for the transfer of read data from the memory bank SC0 (130).

Further, even if an access request is issued to the same memory from another device during processing of a memory access request from one device, the access queue has a plurality of entries, so that the same request from another device is obtained. Requests to access the memory can be buffered in the access queue.

In this embodiment, the memory access request is the instruction cache IC of the processor element 110.
1 (112) and operand cache OC1 (113),
Instruction cache IC2 of processor element 120
4 of (122) and operand cache OC2 (123)
The number of buffers in the access queue, because one device does not issue multiple access requests at the same time (the next access is issued before the previous access is completed). As for, 4 stages are sufficient.

In the embodiment in which a plurality of access requests are issued simultaneously from one device, the number of buffer stages of the access queue is further increased, and means for identifying the access requests issued at the same time is provided. Can be dealt with.

The plurality of access requests latched in the access queue 135 are processed in order from the one latched first by the characteristics of the first-in first-out (FIFO) buffer.

The address decoder 450 decodes the lower 2 bits of the address signal line 230 of the address bus 170, and the access request is sent to the memory bank SC0 (130),
This is to determine which of the SC1 (140), SC2 (150) and SC3 (160) the memory is, and latch the access request in the access queue of the corresponding memory. For example, the address decoder 450 causes the access queue 135 to latch an access request when the lower 2 bits of the address signal line 230 of the address bus 170 are “00”.

Device Data Acquisition FIG. 5 is a diagram illustrating that the device that issued the memory read request acquires the read data.

In FIG. 5, the instruction cache IC1 (112)
Is issuing a read request and fetching read data.

The instruction cache IC1 (112) has a device ID number register 510 and an ID number comparator 52.
0, data latch 530. The device ID number register 510 is preset with a number unique to each device and holds it.

When the instruction cache IC1 (112) acquires the address bus and sends the access address, the contents of the device ID number register 510 are transferred to the address bus 17
It outputs to the ID number signal line 250 of 0. After that, the instruction cache IC1 (112) opens the address bus to another device and monitors the ID number signal line 350 of the data bus 180. That is, the contents of the ID number signal line 350 of the data bus 180 and its own ID number (ID number register 5
The contents of 10) are compared by the comparator 520. As a result of the comparison,
If they match, the content of the data signal line 330 of the data bus 180 is latched in the data latch 530. The instruction cache IC1 (112) uses the contents of the data latch 530 to
1 (111) and store it in the cache memory.

Configuration of Bus Arbiter FIG. 6 is a diagram for explaining the configuration of the arbiters 190 and 195 shown in FIG. 1 in detail.

The data bus arbiter 195 is an arbitration circuit that determines the bus use right of the data bus, and comprises eight circuit blocks 610 to 617 and an OR gate 630 corresponding to each device.

Each of the circuit blocks 610 to 617 corresponds to one signal line of the request request signal 310 of the data bus 180 and one signal line of the grant signal line 320. That is, the circuit blocks 610 and 611 have operand caches OC1 (113) and OC2 (123), respectively.
The instruction blocks IC1 (112) and IC2 (122) correspond to the circuit blocks 612 and 613, respectively, and the memory banks SC0 (130) to SC3 (160) correspond to the circuit blocks 614 to 617, respectively. ing.

Since the internal configurations of the circuit blocks 610 to 617 are common, the internal configuration will be described using the circuit block 610. The circuit block 610 is the inverter 6
40, AND gates 641 and 642, OR gate 64
3, 644 and flip-flop 645, which are connected as shown. It is assumed that one of the circuit blocks of the flip-flop 645 is set to “1” and the other circuit blocks are set to “0”.

The operation of the data bus arbiter 195 will be described below. Memory in the previous cycle
Bank SC0 (130) owns the bus right, and now memory bank SC2 (150) and memory bank SC3
It is assumed that (160) requests the bus right through the request signal line 310. The data bus arbiter 195 determines to give the bus right to the memory bank SC2 (150) by the operation of the circuit blocks 610 to 617, and outputs the grant signal line 320.

According to the data bus arbiter 195, the method of determining the bus right is as follows: in the closed loop of the circuit blocks 610 to 617, the request signal line is checked in order from the device that has the bus right in the immediately preceding cycle. This is a method of granting the bus right to the requesting device found at the beginning.

According to this determination method, since one device does not occupy and use the bus, it is possible to provide a bus arbiter that can give the bus right to each device with a uniform probability.

The operand cache OC1 (11
3) and the request signal line of the data bus from OC2 (123) are asserted when the operand data is stored.

Further, the OR gate 630 generates a signal 631 for synchronizing the arbitration of the address bus 170 with the arbitration of the data bus 180 when the operand data is stored from the operand cache OC1 (113) or OC2 (123). belongs to.

The address bus arbiter 190 is an arbitration circuit that determines the bus usage right of the address bus, and has eight circuit blocks 620 corresponding to each device.
To 627 and an inverter 632.

Each of the circuit blocks 620 to 627 corresponds to one signal line of the request request signal 210 of the address bus 170 and one signal line of the grant signal line 220. That is, the circuit blocks 620 and 621 have operand caches OC1 (113) and OC2 (12), respectively.
3), the instruction blocks IC1 (112) and IC2 (122) correspond to the circuit blocks 622 and 623, respectively, and the memory banks SC0 (130) to SC3 (160) correspond to the circuit blocks 624 to 627, respectively. It corresponds.

Since the internal configurations of the circuit blocks 620 to 627 are common, the internal configuration will be described using the circuit block 620. The circuit block 620 is the inverter 6
50 and AND gates 651, 652, 656, 65
7, OR gates 653, 654, 658, and flip-flop 655, which are connected as shown. It is assumed that one of the circuit blocks of the flip-flop 655 is set to "1" and the other circuit blocks are set to "0".

The operation of the address bus arbiter 190 is the same as that of the data bus arbiter 195 when the signal 631 is "0" (that is, when the operand data is not stored from the operand cache OC1 (113) or OC2 (123)). Is. That is, in the closed loop of the circuit blocks 620 to 627, the request signal line is sequentially inspected from the device which has the bus right in the immediately preceding cycle, and the bus right is given to the first requesting device found. A method of determining the right is realized.

According to this determination method, since one device does not occupy and use the bus, it is possible to provide a bus arbiter that can give the bus right to each device with a uniform probability.

On the other hand, when the signal 631 is "1" (that is, the operand cache OC1 (113) or OC2).
(For storing operand data from (123)),
Inverter 632 and each circuit block 620 to 627
AND gates 656, 657 and OR gate 658 in
Causes the output of the data bus arbiter 195 of the data bus 180 (contents of the grant signal line of the data bus 180) to be set in the flip-flops 655 in the circuit blocks 620 to 627, and the contents thereof to the grant signal of the address bus 170. Output as line 220.

That is, the arbitration of the address bus 170 is synchronized with the arbitration of the data bus 180.

Operation of Multiprocessor System FIG. 7 shows an operation time chart of the multiprocessor system of this embodiment described with reference to FIGS.

In the cycle C1, the instruction cache I
When it is determined that there is no desired data (miss) in C1 (112), the instruction cache IC1 (112) asserts the request signal line 210 to request the bus right of the address bus 170.

In the cycle C2, the address bus arbiter 190 at this point in time, the instruction cache IC1 (112)
Since other devices do not request the bus right of the address bus 170, the grant signal line 220 is asserted to give the bus right to the instruction cache IC1 (112). The instruction cache IC1 (112) receives the grant signal line 220 and outputs the address signal line 230 and the ID number signal line 250.

In cycle C3, memory bank S
C0 (130) knows that it is being accessed from the lower 2 bits of the address signal line 230,
Data is read from the bank SC0 (130). This reading takes 2 cycles.

In cycle C4, data bank S
Since C0 (130) transfers read data, it asserts the request signal line 310 to request the bus right of the data bus 180.

In cycle C5, the data bus arbiter 195 asserts the grant signal line 320 and asserts the memory bank because the devices other than the memory bank SC0 (130) have not requested the bus right of the data bus 180 at this time. The bus right is given to SC0 (130). The memory bank SC0 (130) receives the grant signal line 320,
The respective signals are output to the data signal line 330 and the ID number signal line 350. The ID number of the instruction cache IC1 (112) is output to the ID number signal line 350.

In cycle C6, the instruction cache I
C1 (112) knows that the data accessed by itself has been transferred from the ID number signal line 350, and latches the content of the data signal line 330.

In the cycle C2, in parallel with the series of processes from the cycle C1 to the cycle C6, the operand caches OC1 (113) and OC2 (123) are executed.
Both request the address bus 170, the request of the operand cache OC1 (113) is processed earlier in the cycle C3 by the function of the address bus arbiter 190,
Operand cache OC2 in the next cycle C4
The request (123) is being processed.

Further, in the cycles C5 and C6, even if the access to the memory bank SC2 (150) is continuous, the access queue 155 functions to buffer and sequentially process.

Furthermore, even if both the memory banks SC1 (140) and SC2 (150) request the data bus 180 in the cycle C8, the memory bank SC1 (140) request is cycled by the function of the data bus arbiter 195. It is processed first in C8, and in the next cycle C9, the request of the memory bank SC2 (150) is processed.

According to the present embodiment described above, due to the functions of the memory and the access buffer divided into four banks, no malfunction occurs even if the access is concentrated in one bank.
Further, with respect to the access to the other bank, there is an effect that the access of the other bank can be executed irrespective of the access which is concentrated and waited in one bank. That is,
According to the shared bus control method of this embodiment, the memory banks divided into four can be effectively used.

It is needless to say that the present invention is not limited to the above embodiments, and various modifications can be made according to the technical idea thereof.

For example, in the above embodiment, the shared memories 130 to 160 are simple storage elements (for example, main memory), but in another embodiment, the shared memories 130 to 160 are cache memories. Can be considered. FIG. 8 shows a block diagram of a multiprocessor system in that case.

Memory banks SC0 (130), SC1
Reference numerals (140), SC2 (150) and SC3 (160) are cache memories, which hold a copy of the main memory 810. In addition, the main memory 810 and the cache memory banks SC0 (130), SC1 (140), SC
The second shared bus 8 is provided between 2 (150) and SC3 (160).
Connected by 20.

Although the implementation of the processor system has not been described above, the main memory 81 of the system memory of FIG. 1 or the system of FIG.
The circuit part except 0 can be realized on one semiconductor substrate by using the recent ULSI technology.

The above-described embodiment of the present invention has the following advantages.

Since the data bus is provided with a dedicated arbiter circuit for determining the right to use the bus, the source of use of the bus can be determined independently of the address bus, and in the transfer of read data, only the data bus is independent of the address bus. Can be done using.

Since the device ID number is assigned to the device accessing the shared bus in advance, and this ID number is output at the same time as the address is sent, even if a plurality of accesses are buffered on the memory side, they should be confused. Disappears.

Since the memory is divided into a plurality of banks, the memory accesses to different banks can be processed in parallel.

Since the address bus latches the contents of the address bus in the access queue after sending the address, it can be opened immediately without waiting for a data response, and another device can start a new bus access.

[0114]

The present invention has the following effects.

According to the present invention, since the shared memory is divided into a plurality of banks, and the address bus and the data bus are physically separated, the separated bus system is adopted. It is possible to significantly improve the throughput of access to the shared memory divided into a plurality of banks.

Further, regarding a plurality of access request addresses to the shared memory buffered in the FIFO memory, after the bus usage right of the data bus is acquired on a first-in first-out basis, data transfer between the bank of the shared memory and the processor is performed one after another. Therefore, even if adjacent access requests continuously access the same bank of shared memory, subsequent access requests do not have to wait for the completion of data transfer of the previous access request, and throughput is significantly improved. Can be done.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a multiprocessor which is an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of an address bus 170 shown in FIG.

FIG. 3 is a diagram showing the configuration of a data bus 180 of FIG. 1 in detail.

FIG. 4 is a diagram showing the configuration of an access queue 135 shown in FIG. 1 in detail.

5 is a diagram showing a part of the configuration of the instruction cache IC (112) in FIG. 1 in detail.

FIG. 6 is a diagram showing in detail a configuration of bus arbiters 190, 195 of FIG.

FIG. 7 is a time chart diagram showing the operation of the multiprocessor system according to the embodiment in FIGS. 1 to 6;

FIG. 8 is a block diagram showing a system configuration of a multiprocessor which is another embodiment.

[Explanation of symbols]

110, 120 ... Processor element, 111, 1
21 ... Central processing unit (CPU), 112, 122 ... Instruction cache, 113, 123 ... Operand cache, 130, 140, 150, 160 ... Memory, 13
5, 145, 155, 165 ... Access queue, 17
0 ... Address bus, 180 ... Data bus, 190 ...
Address bus arbiter, 195 ... Data bus arbiter, 250 ... Address bus ID number signal line, 35
0 ... ID number signal line for data bus.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Osamu Nishii               1-280, Higashikoigokubo, Kokubunji, Tokyo               Central Research Laboratory, Hitachi, Ltd. (72) Inventor Makoto Suzuki               1-280, Higashikoigokubo, Kokubunji, Tokyo               Central Research Laboratory, Hitachi, Ltd.                (56) References JP-A-58-58666 (JP, A)                 JP-A-2-22757 (JP, A)                 Okada Soga 3 "Split transfer system               Bus characterization "computer system               Report of Study Group CPSY90-4, Electronic Information               IEICE (1990-4-20) P. 25-32

Claims (2)

(57) [Claims] 1. A plurality of processors, an address bus connected to the plurality of processors, and a data bus connected to the plurality of processors, each of which is one of the plurality of processors via the address bus. An address signal is received from a processor, and data in the memory is given to a corresponding one of the plurality of processors via the data bus, or data is stored from a corresponding one of the plurality of processors. A memory having a plurality of banks and connected to the address bus, arbitrating a request for use of the address bus from the plurality of processors, deciding and giving a right of use of the address bus to one of the plurality of processors; 1 arbiter and the above data bus, Arbitration of use requests of the data bus from the plurality of banks, and use of the data bus in one of the plurality of processors and the plurality of banks independently of the determination of the right of use of the first arbiter. A second arbiter for determining and granting the right, the first arbiter assigning the right to use the data bus to the one of the plurality of processors for storing data. A multiprocessor system, wherein the second arbiter comprises a synchronization means for simultaneously giving the right of use of the address bus to the processor which gives the right of use of the data bus when determined. 2. The same arbiter synchronization means detects a signal indicating that the second arbiter has determined the right to use the data bus to a specific one of the plurality of processors, and the same processor. 2. The multiprocessor system according to claim 1, further comprising circuit means for determining the right to use the address bus.