JP2002024007A - Processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce main storage access latency and to improve system performance when a load instruction processed by instruction processors brings about a data cache error before the request of leading prefetch instruction is completed. SOLUTION: The instruction processors 1 and 2 issue a request with an attached signal for distinguishing a load from a prefetch to a main storage controller 3, the controller 3 registers a load request and a prefetch request into different queues, a priority circuit 22 skips the preceding prefetch request and processes the subsequent load request by notifying a priority circuit 23 or 24 that the load request is currently processed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system of an instruction processor having a data cache, and more particularly to a storage access control for operating an instruction processor at high speed.

[0002]

2. Description of the Related Art In recent years, due to advances in semiconductor processes and logic systems, the operating speed of instruction processors has been remarkably improved. On the other hand, since it is important to increase the capacity of the main memory, it is difficult to increase the speed, and the main memory access performance is a bottleneck. As a means for solving this problem, there is a method in which a small-capacity data cache that operates at a high speed near an instruction processor is provided and a part of the main memory is copied.

When an instruction processor processes a load instruction, data is read from the main memory, written to a register, and simultaneously registered in a data cache. Once a load instruction is issued for data registered in the data cache, the instruction processor can perform high-speed load processing on the data cache without accessing the main memory. In consideration of the locality of the main memory access pattern, data registration in the data cache is not performed only for data that is truly necessary (critical data), but data of several tens of bytes with consecutive addresses is In general, a method of collectively registering data in block units (lines) is used.

[0004] When data to be used in a load instruction can be predicted in advance, there is a method of registering data in a data cache in advance by using a prefetch instruction as shown in JP-A-10-283192. . When processing a load instruction, if the prefetch instruction can be issued long enough before data registration has been completed, the instruction processor can obtain necessary data from the data cache.

If the data used in the load instruction cannot be predicted in advance, or even if the data can be predicted, necessary data may be evicted from the data cache after data registration by the prefetch instruction is completed and before the load instruction is processed. A state in which the data requested to be loaded is not in the data cache is called a cache miss. Until the reading of the load data is completed, the execution of the subsequent instruction using the load data is suspended. Therefore, it is important for performance to complete the reading of the load data with the cache miss in a short time. As means for solving this problem, Japanese Patent Application Laid-Open
As disclosed in Japanese Patent No. 233422, a method of shortening the load processing time by giving priority to load processing over store processing in a main storage control device is known.

[0006]

If a subsequent load instruction causes a cache miss before a prefetch instruction issued earlier by the instruction processor is completed, the processing of the load request is delayed due to the influence of the prefetch request processing. Become. As a result, the time during which the instruction processor that has sent the load request is suspended while waiting for the load processing is lengthened, and the performance of the system is reduced.

[0007]

A signal for discriminating between a prefetch request and a load request is added to the request, and a request is issued from the instruction processor to the main storage controller. The main storage controller gives priority to the load request. Processing.

Specifically, the instruction processor and the main storage controller have separate queues for load requests and prefetch requests, and the selector selects the load request preferentially.
Also, the fact that the load request is being executed is transmitted to the previous processing circuit in advance, so that the load request is processed with priority.

[0009]

FIG. 1 shows a processor system according to an embodiment of the present invention.

The present system comprises an instruction processor 1 and an instruction processor 2, a storage controller 3 for processing load requests, store requests and prefetch requests from these instruction processors, and a main storage device 4 accessed from the storage controller 3.
Consists of The instruction processor 1 and the main memory controller 3
An address path 11 for transmitting (request), a bidirectional switching data path 12 for transmitting and receiving data, and a signal line 17 for switching control are connected. Similarly, the instruction processor 2 and the main memory control device 3 include an address path 13, a bidirectional switching data path 14, and a signal line for switching control.
18 tied. The storage control device 3 and the main storage device 4 are connected by an address path 15 and a bidirectional switching data path 16.

The address unit 38 processes a load instruction, a store instruction, and a prefetch instruction.

When the address unit 38 processes the store instruction, the address of the store request is stored in the store request queue 31, and the store data is stored in the store data queue 34 from the register 36. When registering a request in the store request queue 31, the address of the store request to be registered, the load request queue 32, and the prefetch request queue 33
If the addresses match with the addresses of all the requests, the requests in the load request queue 32 and the prefetch request queue 33 are sent out, and the registration is suspended until there are no more matching addresses.

When the address unit 38 processes a load instruction, it first checks whether the requested data is registered in the data cache 37. If the requested data has been registered, the data registered in the data cache 37 is transferred to the register 36 via the address unit 38, and the process is completed. If the request data was not registered,
The request address is stored in the load request queue 32, the data is returned to the reply buffer 35, and the process is completed when the data is stored in the register 36.

When the address unit 38 processes a prefetch instruction, it first checks whether or not the requested data has been registered in the data cache 37. If the request data has been registered, the processing is completed without doing anything. If the request data has not been registered, the request address is stored in the prefetch request queue 33, and the process is completed.

The priority circuit 21 is a circuit for determining in which order the requests stored in the queues 31 to 33 are sent to the address path 11. At this time, in addition to the address, 2-bit information indicating which type of instruction (load, prefetch, store) is made is transmitted to the request. Specifically, as shown in FIG. 3, the load request is transmitted in the format of FIG. 2A, the prefetch request is transmitted in the format of FIG. 2B, and the store request is transmitted in the format of FIG. 2C. The instruction processor adds a request processor number and ID to the request by the load instruction and the prefetch instruction.
A number is added and transmitted.

The selector 61 is a circuit for judging the type of instruction by referring to the first two bits of the request format and sending the request to a corresponding queue. The load request is a load request queue 42
In the prefetch request queue, the prefetch request queue
At 43, the store request is sent to the store request queue 41. When processing the store request, the selector 61 compares the address of the request registered in the load request queue 42 with the request registered in the prefetch request queue 43. If the addresses match, the preceding request of the same address is sent to the next request queue. The transmission of the subsequent request to the store request queue 41 is suspended until the request is completed.

A method for determining the order of the priority circuit 21 is shown in the flow chart of FIG.

Store request queue 41, load request queue 4
2. The processing is performed in a case where one or more entries are available in the prefetch request queue 43. If there is no free space, the process waits until a free space is formed.

If a request exists in the load request queue 32, the address of the oldest request in the load request queue 32 and the addresses of all requests in the store request queue 31 are compared. If there is no request with the matching address, the oldest request in the load request queue 32 is transferred to the address path 11
And to the load request queue 42 via the selector 61. If the address of the request matches, the data path
After securing the right to use the storage request queue 12, all the requests in the store request queue 31 are sent to the store request queue 41 via the address path 11 and the selector 61, and at the same time, all the store data in the store data queue 34 (format FIG. (f)) is stored in the store data queue 51 via the bidirectional data path 12, the switching control circuit 72, and the priority circuit 23.
After that, the oldest request in the load request queue 32 is transferred to the load request queue via the address path 11 and the selector 61.
Send to 42.

When there is no request in the load request queue 32 and there is a request in the prefetch request queue 33, the address of the oldest request in the prefetch request queue 33 is compared with the addresses of all requests in the store request queue 31. If there is no request whose address matches, the oldest request in the prefetch request queue 33 is sent to the prefetch request queue 43 via the address path 11 and the selector 61. If the request addresses match, after securing the right to use the data path 12, all requests in the store request queue 31 are sent to the store request queue 41 via the address path 11 and the selector 61, and at the same time, the store data queue All the store data of 34 are transferred to the data path 12, the switching control circuit 72 and the priority circuit 23.
Is stored in the store data queue 51 via the. afterwards,
The oldest request in the prefetch request queue 33 is sent to the prefetch request queue 43 via the address path 11 and the selector 61.

If no request exists in the load request queue 32 and no request exists in the prefetch request queue 33, the right to use the data path 12 is secured, and the oldest request in the store request queue 31 is transferred to the address path 11.
And the store data of the oldest request in the store data queue 34 via the data path 12, the switching control circuit 72 and the priority circuit 23.
To be stored.

Similarly, the address path 13 from the processor 2
The load request goes to the load request queue 45, the prefetch request goes to the prefetch request queue 46, and the store request goes to the store request queue via the selector 62.
Stored in 44. The store data is stored in the store data queue 54 via the data path 14, the switching control circuit 73, and the priority circuit 24.

Next, the request of the load request queue 42 from the instruction processor 1 and the request of the load request queue 45 from the instruction processor 2 are all loaded request queues 48.
Is stored in Similarly, the request of the prefetch request queue 43 from the instruction processor 1 and the instruction processor 2
From the prefetch request queue 46 are stored in the all prefetch request queue 49. Instruction processor
The request of the store request queue 41 from the first request and the request of the store request queue 44 from the instruction processor 2 are all stored request queues unless there is a request of the same address in all the load request queues 48 and all the prefetch request queues 49. Stored in 47. At the same time, the data in the store data queue 51 from the instruction processor 1 and the instruction processor
The data of the store data queue 54 from 2 is stored in the all store data queue 57.

The priority circuit 22 determines the request processing order in the same order determination method as the priority circuit 21. However, in this case, the request is executed by sending the request to the main storage device 4 via the address path 15 instead of sending the request to the request queue. The switching control circuit 71 switches the direction of the data path determined by the priority circuit 22.

When the request of the full load request queue 48 is executed, the main storage device 4 stores the load data in the data path 1
Returned to the selector 63 via 6 and the switching control circuit 71.
The selector 63 receives the signal from the priority circuit 22 and returns the signal to the load data queue 52 when the request is from the processor 1 and to the load data queue 55 when the request is from the processor 2.
In addition, the priority circuit 22
Notifies the priority circuit 23 that the request being executed is a load from the processor 1. If the request being executed is a load from the processor 2, the priority circuit 24 is notified that the request is being executed.

When the request of the all prefetch request queue 49 is executed, the main storage device 4 returns the prefetch data to the selector 63 via the data path 16 and the switching control circuit 71. The selector 63 receives the signal from the priority circuit 22 and returns the signal to the prefetch data queue 53 when the request is from the processor 1 and to the prefetch data queue 56 when the request is from the processor 2.

When the request of the all store request queue 47 is executed, the main storage control device 3 sets the all store data queue 5
The data of 7 is stored in the request address of the main memory via the switching control circuit 71 and the data path 16.

A method for determining the order of the priority circuit 23 is shown in the flowchart of FIG.

When even one load data exists in the load data queue 52 for the processor 1, the switching control circuit 72 secures the right to use the data path 12, and switches all the load data in the load data queue 52 to the switching control circuit.
The data is transmitted to the reply buffer 35 of the processor 1 via the data path 12 and the switching control circuit 74 (format diagram
2 (d)). At the same time, when the priority circuit 21 tries to secure the right to use by using the switching control circuit 74 in order to transmit the store data, the transmission of the load data is prioritized. The usage right information is transmitted via signal line 17,
The switching control circuits 72 and 74 are transmitted to each other.

There is no load data in the load data queue 52 to the processor 1, no notification that the load request is being executed from the priority circuit 22 to the priority circuit 23, and no more than the line of prefetch data in the prefetch data queue 53 to the processor 1. If it exists, reserve the right to use data path 12 and prefetch data queue
All 53 prefetch data are sent out to the reply buffer 35 of the processor 1 via the data path 12 (format figure 2 (e)). At this time, the priority circuit 2
Even when 1 attempts to secure the right to use the data path 12 to transmit the store data, the transmission of the prefetch data is prioritized.

There is no load data in the load data queue 52 to the processor 1, no notification that the load request is being executed from the priority circuit 22 to the priority circuit 23, and less than the line of prefetch data in the prefetch data queue 53 to the processor 1. If it exists, reserve the right to use data path 12 and prefetch data queue
The 53 oldest prefetch data is sent to the reply buffer 35 of the processor 1 via the data path 12.
At the same time, if the priority circuit 21 attempts to secure the right to use the data path 12 to transmit the stored data, the transmission of the stored data is prioritized.

The load data queue 55 for the processor 2, the prefetch data queue 56 for the processor 2, the priority circuit 24, the switching control circuit 73, the data path 14, and the signal line 18 perform the same processing as the processing for the processor 1. Do for 2.

When the critical data by the load instruction is stored in the reply buffer 35, the critical data is sent from the reply buffer 35 to the register 36. The data according to the prefetch instruction and the data according to the load instruction are registered in the data cache 37 when the data of the same line is prepared in the reply buffer 35.

FIG. 6 shows another embodiment. In the embodiment of FIG. 6, the instruction processor and the main memory control device are connected by a bus. As the bus arbitration protocol, a protocol with a priority shown in "Parallel Computer Architecture" written by Satoshi Okukawa is used. At this time, the load miss request is handled as a protocol having a higher priority than the prefetch request and the store request.

In this embodiment, the number of instruction processors is 2,
The number of main storage controllers was 1, and the number of main storage devices was 1.
Any number of instruction processors, main storage control devices, and main storage devices can be implemented. Further, the connection form of the instruction processor, the main storage control device, and the main storage device is not limited to the illustrated one.

[0036]

Even when a large number of prefetch requests have been issued to the main storage controller in advance, the subsequent load requests are processed preferentially, and the processor is suspended while waiting for the load processing. Can be reduced. It is possible to improve performance by several tens of percent in memory latency and several percent in execution time.

As a result, the processing time of the preceding prefetch request may increase. However, since the prefetch request does not write to the register, a decrease in performance due to delay in completion is small. The data of the prefetch request is data that is required after the data of the load request, whereas the data of the load request is data that is directly needed by the processor. Therefore, the effect of preferentially processing a load request is significant.

[Brief description of the drawings]

FIG. 1 is a detailed diagram of a processor system according to an embodiment of the present invention.

FIG. 2 shows a request format and a data format used in the processor system of FIG. 1;

FIG. 3 is a detailed diagram of a procedure for generating a request format generated by the instruction processor when a request is issued.

FIG. 4 is a flowchart of an order determination procedure of the priority circuit 21 of FIG. 1;

FIG. 5 is a flowchart of an order determination procedure of the priority circuit 23 of FIG. 1;

FIG. 6 is a detailed view of a processor system according to another embodiment of the present invention.

[Explanation of symbols]

 1,2: instruction processor 3: storage controller 4: main storage 11,13,15: address path 12,14,16: data path 17,18: signal line 21,22,23,24: priority circuit 31: Store request queue 32: Load request queue 33: Prefetch request queue 34: Store data queue 35: Reply buffer 36: Register 37: Data cache 38: Address unit 41,44: Store request queue 42,45: Load request queue 43,46 : Prefetch request queue 47: All store request queue 48: All load request queue 49: All prefetch request queue 51, 54: Store data queue 52, 55: Load data queue 53, 56: Prefetch data queue 57: All store data queue 61 , 62, 63: selector 71, 72, 73, 74: switching control circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yuichi Nishigan 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Incorporated Enterprise Server Division, Hitachi, Ltd. (72) Inventor Masaya Nakahata 1- 1 Horiyamashita, Hadano-shi, Kanagawa Japan F-term in the Enterprise Server Division of Ritsusei Seisakusho (reference) 5B005 JJ11 MM01 NN22 5B013 AA01 AA05 DD00 5B060 CA05 CA06

Claims (7)

[Claims] At least one instruction processor for issuing a storage access request by adding identification information for identifying a storage access request by a load instruction and a storage access request by a prefetch instruction, and an object of the storage access request A sending device that receives a storage access request issued from the one or more processors and sends it to the storage device, and a return that returns an access result returned from the storage device to the requesting instruction processor. Wherein at least one of the sending circuit and the returning circuit identifies the identification information and processes a storage access request by a load instruction in preference to a storage access request by a prefetch instruction. Processor system. 2. The processor system according to claim 1, wherein the sending circuit notifies the returning circuit that the storage access request by the load instruction is being processed. 3. The method according to claim 1, further comprising: receiving one or a plurality of instruction processors, one or a plurality of storage devices to which a storage access request is issued from the instruction processor, and a storage access request issued from the instruction processor. A storage controller used in a processor system having one or more storage controllers for sending a storage access request to a storage device and returning an access result to a requesting processor. Storage control having processing means for distinguishing a storage access request issued from one or more instruction processors into a storage access request by a prefetch instruction or a storage access request by a load request, and processing the storage access request by a load instruction with priority apparatus. 4. The processing means forms a request queue by distinguishing a storage access request issued from the one or more instruction processors into a storage access request by a prefetch instruction and a storage access request by a load request, respectively. 4. The storage control device according to claim 3, further comprising a sending circuit for sending a storage access request by a load request to said storage device with priority. 5. The processing unit forms a queue by distinguishing an access result obtained from the storage device for each processor of an access request source and according to a result of an access request by a prefetch instruction or a result of an access request by a load instruction. And a return circuit for giving priority to the result of the access request by the load instruction and returning the result to the access request source.
The storage control device according to any one of the preceding claims. 6. An apparatus according to claim 1, further comprising: receiving one or a plurality of instruction processors, one or a plurality of storage devices to which a storage access request is issued from said instruction processor, and a storage access request issued from said instruction processor. An instruction processor for use in a processor system having one or more storage controllers that send a storage access request to a storage device, wherein the instruction processor issues the storage access request to the storage controller. A processor system, wherein information indicating the identification of a storage access request by a prefetch instruction or a storage access by a load instruction is added to a storage access format and issued. 7. A method according to claim 1, further comprising: receiving one or more instruction processors, one or more storage devices to which a storage access request is made from said instruction processor, and a storage access request issued from said instruction processor. An instruction processor for use in a processor system having one or more storage controllers for sending a storage access request to a storage device, wherein the instruction processor includes a storage access request and a load request by a prefetch instruction among the storage access requests. An instruction processor comprising: an access request issuing circuit that distinguishes a storage access request by a load instruction and issues a storage access request by a load instruction to the storage control device with priority.