JP2586061B2 - Cache memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a cache memory control device in a two-bus system, and to improve a reduction in processing speed due to a cache memory invalidation process performed when a main memory is DMA-written. A main memory directly accessed by the input / output control unit via the common bus, a common bus control unit for controlling bus contention of the common bus, and a part of data stored in the main memory. A cache memory which is transferred and accessed by a processor via a memory bus, a memory bus controller for controlling bus contention of the memory bus, and address data at the time of writing when the input / output controller writes to the main memory And obtains the permission to use the memory bus, outputs the address data to the memory bus, and corresponds to the address data. A cache memory control device that performs a process of invalidating data in a cache memory and outputs a standby signal for waiting for a bus use request from the input / output control unit until the invalidation process is completed. A first-in first-out memory for sequentially storing address data output at the time of writing by the input / output control unit; and the invalidation processing unit controls the memory bus control when the address data is stored in the first-in first-out memory. A bus use request is output to the memory section, and after obtaining permission to use the memory bus, the address data is sequentially extracted from the first-in first-out memory to invalidate the cache memory, and the first-in-first-out memory becomes full. In this case, the standby signal is output when the invalidation processing has not been completed.

[Industrial applications]

 The present invention relates to an improvement in a cache memory control device.

In order to increase the speed of a processor, a cache memory system has been widely used in which a high-speed and small-capacity memory is provided near the processor, and a part of data, programs, and the like of a main memory is stored in the memory and accessed at high speed.

In this cache memory system, when writing (DMA write) to the input / output control unit (I / O device) main memory by direct memory access, the contents of the main memory do not match the contents of the cache memory, and the processor In order to prevent malfunction, every time a DMA write is performed, the data in the corresponding cache memory is invalidated, and then the next DMA request is permitted.

However, a two-bus system (memory bus and common bus) that allows the operation of the processor and the operation of the I / O device to be performed in parallel
In, when the processor is accessing another I / O device connected to the memory bus, even if the common bus is available, the bus use is waited for invalidation processing, and therefore the next DMA request is waited. There is a point.

Therefore, there is a need for a cache memory control device that solves the above-mentioned problem that the DMA transfer speed is reduced due to invalidation processing.

[Conventional technology]

FIG. 3 is a block diagram of a conventional cache memory system, FIG. 4 is a time chart of a conventional DMA operation, FIG. 5 is a diagram showing another system example, and FIG. 6 is an explanatory diagram of the cache memory.

FIG. 3 shows a cache memory system having two buses, a memory bus 100 and a common bus 101. The memory bus 100 includes a processor CPU1, a cache memory 2, and an I / O bus.
The I / O device 3 and the invalidation processing unit 8 are connected, and the common bus 101
Is connected to the main memory 5 and the I / O device 6.

Here, the memory bus control unit 4 performs bus contention control of the memory bus 100. When a bus use request is output from each unit, the memory bus control unit 4 gives permission to use the memory bus 100 based on a predetermined priority. The common bus control unit 7 similarly performs contention control on the common bus 101, and the transceiver TR13 is opened when the memory bus 100 accesses the common bus 101.

Therefore, the operation of the processor CPU1 accessing the I / O device 3 and the operation of the I / O device 6 accessing the main memory 5 are performed in parallel using the respective buses.

When the processor CPU1 accesses the main memory 5, the access is performed with permission to use the memory bus 100 and the common bus 101.

In the above cache memory system, when the I / O device 6 writes data to the main memory 5 by DMA, the following operation is performed. Refer to FIG. 4. (1) The I / O device 6 outputs a DMA request (bus use request) to the common bus control unit 7.

(2) The common bus control unit 7 gives permission to use the common bus 101
When output to the / O device 6, the I / O device 6 writes, for example, 1-byte data to the main memory 5.

(3) The invalidation processing unit 8 executes the DMA output to the common bus 101
After the address data is latched in the register 9 and a bus use request of the memory bus 100 is output to the memory bus control unit 4 to obtain the use permission, the latched address data is output to the memory bus 100 and invalidated in the cache memory 2. A signal is output and the corresponding data is invalidated.

The I / O device 6 subsequently outputs a DMA request to write the next byte data, but the common bus control unit 7 confirms that the previous invalidation processing has been completed (an invalidation processing end signal 70).
After that, give DMA permission.

As described above, the invalidation process is performed every time the I / O device 6 writes the main memory 5, and when the processor CPU1 accesses the data in the cache memory 2, it becomes a mishit and is transferred from the main memory 6, Data mismatch is resolved.

Here, when the invalidation request (bus use request of the memory bus 100) is output to the memory bus control unit 4, if the processor CPU1 is accessing the I / O device 3, the invalidation is performed until the access ends. Request is awaited.

Therefore, if the processing speed of the I / O device 3 is slow (FIG. 4), invalidation is waited, and the next DMA request of the I / O device 6 is waited during that time (FIG. 4), so that the DMA speed is reduced.

The above operation is the same in the case of the multiprocessor system shown in FIG. 5, and if the processor CPU1 has obtained the permission to use the first bus and is waiting for the permission to use the second bus, the processor is invalidated during that time. The request was awaited, so I / O device 6
DMA speed decreases.

In order to facilitate understanding of the present invention, an outline of the cache memory will be described below with reference to FIG.

The cache memory 2 includes a data memory 36 and a cache control unit 31, and a tag unit 32 includes a processor.
Lower address data of address data 60 output by CPU1
The upper address data 60a is stored using the address 60b as an address, and the data output to the data bus using the lower address data 60b as an address is stored in the data memory 36.

Here, when the processor CPU1 accesses and outputs the address data to the memory bus 100, the tag section 32 is addressed with the lower address data, and the read upper access data 60a and the upper address data output by the processor are compared with the comparison circuit 33. Are compared by

As a result of the comparison, if the match and the V bit indicating data validity / invalidity are "1", a hit signal "1" is output from the AND circuit 34, and the data gate 37 opens to open the predetermined address addressed by the lower address data. Data is stored in data memory 36
Output.

The V bit is provided corresponding to each address of the tag unit 32, and is addressed by the lower address data 60b and read / read.
When the data is stored in the data memory 36, the valid signal "1" is set. When an invalidation request is output, the invalidation signal "0" is set by the invalidation processing unit 8. .

When the V bit is "0", a mishit signal "0" is output from the AND circuit 34, the data is transferred from the main memory 5 by the mishit processing unit 35 and stored in the cache memory 2, and the processor CPU 1 Is read in.

[Problems to be solved by the invention]

As described above, in the two-bus system, there is a problem that the invalidation processing by the DMA write of the I / O device is waited by the bus access of the processor, and as a result, the DMA speed is reduced.

The present invention has been made in view of the above problems, and has as its object to provide a cache memory control device that improves a decrease in DMA speed of an I / O device.

[Means for solving the problem]

As shown in the cache memory system block diagram of the embodiment of FIG. 1, the cache memory control device of the present invention is directly accessed by the input / output control unit (the input / output control device 6 of FIG. 1) via the common bus 101. A common bus controller 7 for controlling bus contention of the common bus 101, and a part of data stored in the main memory 5 and transferred by the processor (CPU of FIG. 1) via the memory bus 100. When the cache memory 2 to be accessed, the memory bus control unit 4 for controlling the bus contention of the memory bus 100, and the input / output control unit 6 writes to the main memory 5, the address data 50 at the time of writing is acquired and the memory bus 100 , The address data 50 is output to the memory bus 101, and the cache memory 2 corresponding to the address data 50 is invalidated and invalidated. And a invalidation processing unit 10 that outputs a standby signal 51 for waiting for a bus use request from the input / output control unit 6 until the end of the conversion processing. A first-in first-out memory 11 in which address data 50 to be sequentially stored is provided, and the invalidation processing unit 10 sends a bus request signal (invalidation request) to the memory bus control unit 4 when the address data 50 is stored in the first-in first-out memory 11. signal
52) is output, the address data 50 is sequentially extracted from the first-in first-out memory 11 after the use permission of the memory bus 100 is obtained, the cache memory 2 is invalidated, and the first-in-first-out memory 11 becomes full. And outputs the standby signal 51 as the invalidation processing not completed state.

(Operation)

The address data 50 output during the DMA write is sequentially stored (accumulated) in the first-in first-out memory (FIFO memory) 11,
A permission is given to the DMA request of the input / output controller 6 even if the previous invalidation processing has not been completed.

When the address data 50 is stored in the FIFO memory 11, the invalidation processing unit 10 sends an invalidation request signal to the memory bus control unit 4.
52 is output and the FIFO is
The invalidation processing is sequentially performed based on the address data 50 stored in the memory 11.

Here, when the memory bus 100 cannot be used, the invalidated address data 50 is stored in the FIFO memory 11. However, when the FIFO memory 11 is full (full), the address data 50 cannot be stored any more, so that the standby is performed. The common bus control unit 7 outputs a signal 51 to the common bus control unit 7, and upon receiving the standby signal 51, waits for a DMA request from the input / output control unit 6 without giving permission.

The invalidation request is normally set to the highest priority, and is preferentially accepted when the access of another I / O device by the processor CPU1 is completed, and the data mismatch is resolved when the processor CPU1 accesses next. You.

As described above, the address data for the invalidation processing is accumulated in the FIFO memory 11, and the DMA request of the input / output control unit 6 is transmitted until the FIFO memory 11 becomes full even if the previous invalidation processing is not completed. DMA speed is improved because it is configured to accept.

〔Example〕

 An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a cache memory system of an embodiment, and FIG. 2 is a time chart showing an operation example.

In FIG. 1, reference numeral 10 denotes an invalidation processing unit, which outputs an invalidation request signal (bus use request) 52 to the memory bus 100 when address data 50 is stored in the FIFO memory 11 to perform invalidation processing. At the same time, when the FIFO memory 11 becomes full, a standby signal 51 is output to the common bus control unit 7.

Reference numeral 11 denotes a FIFO memory (first-in, first-out memory) which is read out in the order of writing, has an output ready signal terminal which becomes active when data is stored, and an empty signal terminal which becomes active when full, and is provided on the common bus 101. The output address data 50 is sequentially stored based on an address strobe signal (not shown).

 The same reference numerals throughout the drawings denote the same object.

In the above configuration, the output ready signal output from the FIFO memory 11 is output as the invalidation request signal 52, and the empty signal is output as the standby signal 51 to the memory bus controller 4 and the common bus controller 7, respectively.

 The operation will be described below with reference to FIG.

(1) When the common bus control unit 7 receives the DMA request from the input / output control unit 6 and the standby signal 51 is not output,
A Give permission.

(2) The input / output control unit 6 writes, for example, 1-byte data to the main memory 5 with the DMA permission.

(3) The DMA write address data 50 output on the common bus 101 is stored in the FIFO memory 11.

(4) The invalidation request signal 52 is output to the memory bus control unit 4, and if the memory bus 100 is not used by the processor 1, an invalidation signal “0” is output to the cache memory 2 and invalidation processing is performed ( 2), if the memory bus 100 is in use, the invalidation processing is waited. FIG. 2 (5) During this time, if a DMA request is output from the input / output control unit 6, the DMA write is permitted unless the standby signal 51 is output, and the output address data 50 is FIFO
Stored in the memory 11.

(6) The DMA above until the access of processor CPU1 ends
When the FIFO memory 11 becomes full by writing, the standby signal 51 is output to the common bus 101, and DMA permission is given to the subsequent DMA request after the invalidation processing is performed and the standby is released. . FIG. 2 As described above, address data 50 for invalidation processing
Is stored in the FIFO memory 11 and DMA permission is given irrespective of the invalidation processing, so that the DMA write can be continuously performed until the FIFO memory 11 becomes full,
Processing speed is improved.

〔The invention's effect〕

The present invention uses address data for invalidation processing as FIFO
A cache memory control device that stores data in a memory and performs DMA writing until the FIFO memory becomes full irrespective of invalidation processing is provided. The effect of improving the speed of DMA in a cache memory system is enormous.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cache memory system of an embodiment, FIG. 2 is an operation time chart of the embodiment, FIG. 3 is a block diagram of a conventional cache memory system, FIG. FIG. 5 is a diagram showing another system example, and FIG. 6 is an explanatory diagram of a cache memory. In the figure, 1 is a processor CPU, 2 is a cache memory, 4 is a memory bus controller, 5 is a main memory, 6 is an input / output controller, an I / O device, 7 is a common bus controller, and 10 is an invalidation processor. 11 is a first-in first-out memory, FIFO memory, 50 is address data, 51 is a standby signal, 52 is an invalidation request signal and a bus use request.

Claims (1)

(57) [Claims] 1. A main memory directly accessed by an input / output control unit via a common bus, a common bus control unit for controlling bus contention of the common bus, and a part of data stored in the main memory. A cache memory transferred by the processor and accessed by the processor via the memory bus; a memory bus control unit for controlling bus contention of the memory bus;
When the input / output control unit writes data to the main memory, a cache memory corresponding to the address data is obtained by obtaining address data at the time of writing, obtaining permission to use the memory bus and outputting the address data to the memory bus. A cache memory control device comprising: an invalidation processing unit that performs a data invalidation process and outputs a standby signal for waiting for a bus use request from the input / output control unit until the invalidation process ends. A first-in first-out memory for sequentially storing address data output at the time of writing by the input / output control unit; the invalidation processing unit transmits a bus to the memory bus control unit when the address data is stored in the first-in first-out memory; A use request is output, and after obtaining permission for use of the memory bus, the address data is sequentially extracted from the first-in first-out memory. A cache memory controller for performing invalidation processing of the cache memory and outputting the standby signal as invalidation processing not completed when the first-in-first-out memory becomes full. apparatus.