JPH01112451A - System for controlling cash memory - Google Patents

Abstract

PURPOSE:To improve a process speed by accumulating address data, which execute a nullification processing, to a first-in first-out memory, allowing a DMA write and causing the DMA write to be stand-by when the first-in first-out memory goes to be full. CONSTITUTION:When address data 50 are stored to a first-in first-out memory 11, a nullification processing part 10 outputs a nullification requesting signal 52 to a memory bus control part 4 and obtains the bus using allowance of a memory bus 100. Then, the nullification processing is successively executed based on the data 50 to be accumulated in the memory 11. When the memory 11 goes to be full, since the data 50 can not be stored any more, a stand-by signal 51 is outputted to a sharing bus control part 7 and the control part 7 does not give the allowance to a DMA request from an input and output control part 6 and causes it to be stand-by. Thus, the address data for the nullification processing are accumulated to the memory 11 and even when the preceding nullification processing is not completed, the DMA request of the control part 6 is accepted until the memory 11 goes to be full. Then, the DMA speed is improved.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a cache memory control method in a two-bus system, and an object of the present invention is to improve the reduction in processing speed due to cache memory invalidation processing performed when main memory is DMA written. The processor and cache memory each connected to a memory bus, and the main memory connected to a common bus are DM.
A cache memory control method in a cache memory system comprising an input/output control unit that performs A writing,
A first-in, first-out memory that stores address data output by the input/output control unit during DMA write; and a first-in, first-out memory that stores the address data in the first-in, first-out memory and outputs the address data from the first-in, first-out memory after obtaining permission to use the memory bus. An invalidation processing unit is provided which performs invalidation processing and outputs a standby signal to the common bus control unit to make the input/output control unit wait for DMA write when the first-in first-out memory becomes full, thereby invalidating the first-in first-out memory. Accumulate address data to be processed and use the DMA of the input/output control unit
The configuration is such that the write is permitted and the DMA write is made to wait when the first-in, first-out memory becomes full.

[Industrial application field]

The present invention relates to improvements in cache memory control methods.

In order to increase the speed of processors, cache memory systems have become popular in which a high-speed, small-capacity memory is provided near the processor, and a portion of data, programs, etc. in the main memory is stored in the memory and accessed at high speed.

In this cache memory system, when the input/output control unit (device 10) writes to the main memory by direct memory access (DMA write), the contents of the main memory and the contents of the cache memory do not match, and the processor In order to prevent malfunctions, the device is configured so that each time a DMA write is performed, data in the corresponding cache memory is invalidated and then a subsequent DMA request is permitted.

However, in a two-bus system (memory bus and common bus) in which processor operations and I10 device operations occur in parallel, the processor
When accessing 10 devices, there is a problem that even if the common bus is available, the use of the bus is awaited due to invalidation processing, and therefore the next DMA request is awaited.

Therefore, there is a need for a cache memory control method that improves the above-mentioned problem in which the DMA transfer speed decreases due to invalidation processing.

[Conventional technology]

Figure 3 is a conventional cache memory system block diagram.
FIG. 4 is a conventional DMA operation time chart, FIG. 5 is a diagram showing another system example, and FIG. 6 is an explanatory diagram of a cache memory.

FIG. 3 shows a cache memory system equipped with two buses, a memory bus 100 and a common bus 101. The main memory 5 and the I10 device 6 are connected to the common bus 101.

The memory bus control unit 4 performs bus contention control on the memory bus 100, and when a bus use request is output from each unit, it grants permission to use the memory bus 100 based on a predetermined priority order. The common bus control unit 7 similarly performs contention control on the common bus 101, and the transceiver TR13 controls the communication from the memory bus 100 to the common bus 101.
opened when accessing.

Therefore, the operations in which the processor CPU 1 accesses the I 10 device 3 and the operations in which the I 10 device 6 accesses the main memory 5 are performed in parallel using their respective buses.

This is done with permission for use.

In the above cache memory system, ■10 When the device 6 writes data to the main memory 5 using DMA,
The following operations are performed. Refer to FIG. 4 (1) The I10 device 6 sends a DMA request (
bus usage request).

(2) Common bus control unit 7 grants permission to use common bus 101! When outputting to the I10 device 6, the I10 device 6 writes, for example, 1 byte of data to the main memory 5.

(3) The invalidation processing unit 8 launches the DMA address data output to the common bus 101 into the register 9, outputs a bus use request for the memory bus 100 to the memory bus control unit 4, and obtains permission to use the memory bus 100, and then The launched address data is output to the memory bus 100 and an invalidation signal is output to the cache memory 2 to invalidate the corresponding data.

The 110 device 6 then outputs a DMA request to write the next byte data, but the common bus control unit 7 confirms that the previous invalidation process has been completed (the invalidation process is performed every time there is no write). , when the processor CPU1 accesses the relevant data in the cache memory 2, it becomes a miss hint and is transferred from the main memory 6, and the data mismatch is resolved.

Here, when an invalidation request (a request to use the memory bus 100) is output to the memory bus control unit 4, if the processor CPU i is accessing the I10 device 3, the invalidation is performed until the access is completed. Requests are made to wait.

Therefore, if the processing speed of the I10 device 3 is slow (FIG. 4), invalidation is forced to wait, and the next DMA request from the I10 device 6 is forced to wait (FIG. 4), resulting in a decrease in DMA speed.

The above operation is the same in the case of the multiprocessor system shown in FIG. The request is made to wait, so I 10
The DMA speed of device 6 is reduced.

In order to facilitate understanding of the present invention, an overview of the cache memory will be explained below with reference to FIG. 6.

The cache memory 2 is composed of a data memory 36 and a cache control section 31, and the tag section 32 stores upper address data 60a using the lower address data 60b of the address data 60 output from the processor CPU 1 as an address. The data memory 36 stores data output to the data bus using the lower address data 60b as an address.

Here, when the processor CPU 1 accesses and outputs address data to the memory bus 100, the tag section 32 is addressed with the lower address data, and the read upper access data 60a and the upper address data output by the processor are compared to the comparison circuit. It is compared by 33.

As a result of the above comparison, if there is a match and the V bit indicating data validity/invalidity is 'l', the AND circuit 34 outputs a rehit signal "1", the data gate 37 is opened, and the predetermined address addressed by the lower address data is output. data is output from the data memory 36.

The V bit is provided corresponding to each address of the tag section 32, and is addressed by the lower address data 60b to read/write.
When the data is stored in the data memory 36i, the valid signal “l” is set, and when the invalidation request is output, the invalidation processing unit 8 outputs the invalidation signal “0”.
” is set.

When this V bit is “0”, the AND circuit 34 outputs a limit hit signal “0”, and the miss processing unit 35 transfers the data from the main memory 5 to the cache memory 2 and stores it in the processor CPU 1. Read.

[Problem 3 to be solved by the invention As explained above, in a two-bus system, I 10
There is a problem that the invalidation process by DMA write of the device is made to wait due to the bus access of the processor, resulting in a slow DMA speed.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a cache memory control method that improves the reduction in DMA speed of an I10 device.

[Means for solving problems]

The cache memory control method of the present invention, as shown in the cache memory system block diagram of the embodiment in FIG. When the address data is stored in the first-in, first-out memory, an invalidation request signal (52) is output to the memory bus control unit, and after obtaining permission to use the memory bus, the address data is output from the first-in, first-out memory to In addition to invalidating the cache memory, when the first-in, first-out memory becomes full with address data (50) that has not been invalidated, a standby signal (51) that causes the input/output control unit to wait for the writing is sent to the common bus. An invalidation processing section (10) for outputting to the control section is provided.

[For production]

The address data 50 output at the time of DMA write is sequentially stored (accumulated) in a first-in, first-out memory (FIFO memory) 11, and a DMA request from the input/output control device 6 is permitted even if the previous invalidation process has not been completed. Try to give.

When the address data 50 is stored in the FIFO memory 11, the invalidation processing unit 10 outputs the invalidation request signal 52 to the memory bus control unit 4, obtains permission to use the memory bus 100, and stores the address data in the FIFO memory 11. The invalidation process is performed sequentially based on the address data 50 that is currently in use.

Here, if the memory bus 100 cannot be used, the FIF
Address data 50 that has not been invalidated is stored in the O memory 11, but when the FIFO memory 11 becomes full, no more address data 50 can be stored, so a standby signal 51 is output to the common bus control unit 7. , the common bus control unit 7 receives the standby signal 51 and receives the D? from the input/output control unit 6.
The IA request is not granted and is left on standby.

Invalidation requests typically have the highest priority;
Other by processor CPU 1! When the access from 10 devices is completed, it is accepted preferentially and the processor CPU
The data mismatch will be resolved the next time l accesses.

As described above, the address data for the invalidation process is stored in the FIFO memory 11, and the input/output control unit 6 is operated until the FIr'O memory 11 becomes full even if the previous invalidation process is not completed. Since the configuration is configured to accept DMA requests, the DMA speed is improved.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a cache memory system according to an embodiment, and FIG. 2 is a time chart showing an example of operation.

In FIG. 1, reference numeral 10 denotes an invalidation processing unit, which outputs an invalidation request signal (bus use request) 52 to the memory bus 100 when address data 50 is stored in the FIFO memory January 1, and performs invalidation processing. At the same time, when the FIFO memory 11 becomes full, a standby signal 51 is output to the common bus control section 7.

11 is a FIFO memory (first-in, first-out memory) that is read in the order of writing, and has an output ready signal terminal that becomes active when data is stored and an empty signal terminal that becomes active when it is full;
The address data 50 output on the memory card 1 are sequentially stored based on an address strobe signal (not shown).

The same reference numerals represent the same objects throughout the design.

In the above configuration, the output ready signal output from the FIFO memory 11 is output as the invalidation request signal 52, and the empty signal is output as the standby signal 51 to the memory bus controller 4 and the common bus controller 7, respectively.

The operation will be explained below with reference to FIG.

(1) The common bus control unit 7 receives DM from the input/output control unit 6.
When a request A is received, if the standby signal 51 is not output, DMA permission is granted.

(2) The input/output control unit 6, for example,
Write byte data to main memory 5.

(3) The DM^ write address data 50 output on the common bus 101 is stored in the FIFO memory 11.

(4) The invalidation request signal 52 is output to the memory bus control unit 4, and if the memory bus 100 is not used by the processor l, the invalidation signal "0" is output to the cache memory 2 and invalidation processing is performed ( 2), if the memory bus 100 is in use, the invalidation process is made to wait. (5) During this period, when a DMA request is output from the input/output control unit 6, if the standby signal 51 is not output, DMA write is permitted, and the address data 50 is output based on it.
is stored in FIFO memo January 1st.

(6) When the FIFO memory 11 becomes full due to the above DMA write by the end of the access by processor cpu i, the standby signal 51 is output to the common bus 101, and invalidation processing is performed for subsequent DMA requests. DMA permission is granted after the wait is released. Figure 2■ As mentioned above, address data 50 for invalidation processing
is stored in the FIFO memory 11, and DMA permission is given regardless of whether the invalidation process is performed.0M parite can be performed continuously until the FIFO memory 11 is full, improving processing speed. .

〔Effect of the invention〕

The present invention provides address data for invalidation processing using FIF.
This provides a cache memory control method that stores data in O memory and causes DMA writes to be performed until the FIFO memory becomes full, regardless of invalidation processing, and has a significant effect on improving DMA speed in cache memory systems. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the cache memory system of the embodiment, FIG. 2 is an operation time chart of the embodiment, FIG. 3 is a block diagram of a conventional cache memory system, FIG. 4 is a conventional DMA operation time chart, and FIG. FIG. 5 is a diagram showing another example of the system, and FIG. 6 is an explanatory diagram of the cache memory. In the figure, 1 is a processor CPU. 2 is a cache memory, 4 is a memory bus control unit, 5 is a main memory, 6 is an input/output control unit, I10 device, 7 is a common bus control unit, IO is an invalidation processing unit, 11 is a first-in first-out memory, and a FIFO memory. , 50 is address data, 51 is a standby signal, and 52 is an invalidation request signal and a bus use request.

Claims (1)

[Claims] A cache memory (2) to which part of the data stored in the main memory (5) is transferred and accessed by the processor (1), and input/output control for writing and reading the main memory by direct memory access. a section (6), and an invalidation processing section (10) that invalidates data in the corresponding cache memory based on the address data (50) output when the input/output control section writes to the main memory; a memory bus control unit (100) that controls bus contention on a memory bus (100) to which the processor and the cache memory are connected;
4); and a common bus control unit (7) that controls bus contention on a common bus (101) to which the main memory and the input/output control unit are connected. , a first-in, first-out memory (11) for storing the output address data (50), and outputting an invalidation request signal (52) to the memory bus control unit when the address data is stored in the first-in, first-out memory; After obtaining permission to use the memory bus, the address data is output from the first-in, first-out memory and the cache memory is invalidated, and the first-in, first-out memory becomes full with uninvalidated address data (50). and an invalidation processing section (10) that outputs a standby signal (51) to the common bus control section to cause the input/output control section to wait for the writing, and the address data to be invalidated is stored in the first-in, first-out memory (11). A cache memory control method characterized by accumulating (50) and permitting the input/output control section to write into the main memory, and making the writing standby when the first-in, first-out memory becomes full.