JPH0457145A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To efficiently utilize a peripheral function with another processor by reading out the content of a condition incorporating the peripheral function from a register storing the condition and writing the content on a register in the inside of its own peripheral function with a processor incorporating the peripheral function. CONSTITUTION:An MPU 1 sets required DMA information on the internal register of a built-in DMA controller 8. Thereafter, the required DMA information is set on an I/O 7, and following that, a DMA requirement by a DREQ signal 32 is outputted. A bus arbitor 3 receiving the signal issues a requirement to release a bus to the MPU 1. The bus arbitor 3 outputs a DMA start-up signal 34 to the DMA controller 8 at a time when the release of the bus is informed by an ACK signal 24, and also, a DACK signal 33 is outputted to the I/O 7, which enbles DMA to start. In such a manner, it is possible to form a multi-processor with high efficiency by efficiently using the peripheral function with another processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system in an information processing device such as a personal computer, workstation, or office computer.

[Prior Art] Conventionally, processors with built-in peripheral functions have been known to reduce the number of parts and downsize the device.

Such a processor is disclosed in, for example, Japanese Patent Application Laid-Open No. 634197.
This method is disclosed in Japanese Patent Publication No. 0-1, Japanese Unexamined Patent Publication No. 1-298458, and the like.

On the other hand, a multi-processor processor system 1 uses multiple processors to improve performance by sharing functions or sharing loads.
2 is also public number 11. Even in a multiprocessor system, if you use a processor with built-in peripheral functions, you can eliminate the need for external peripheral functions and reduce the number of parts. However, having multiple peripheral functions in every processor is This is unreasonable both in terms of circuit scale and economics. Therefore, it is desirable to enable a processor without peripheral functions to share the peripheral functions of a processor with built-in peripheral functions. Such a multi-processor support system 11 is disclosed in Japanese Patent Laid-Open No. 60-233757.

In the multiprocessor system described in this publication, the operation of the processor with built-in peripheral functions is stopped by the master refresh 1~ signal from the external processor, and while this operation is stopped, the peripheral functions are connected to the external bus and control line, and processors can access it.

[Problems to be Solved by the Invention] 1] In the conventional multiprocessor system described in Japanese Unexamined Patent Publication No. 60-233757, when there is a conflict between requests to use a peripheral function, for example, if the peripheral function There is no consideration given to the case where multiple processors share 110. That is,
Forcibly rewriting the contents of the internal controller I-roll register that stores DMA information about the shared T/○ will interrupt the preceding DMA process, making it impossible to continue. waiting for internal con 1
Even if the contents of the servo register were to be rewritten, there was a problem in that the external processor had to wait until the DMA processing was completed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor system that solves these problems and allows other processors to efficiently utilize peripheral functions such as a DMA controller built in a processor.

[Means for Solving the Problems] In order to achieve the above object, a multiprocessor system according to the present invention includes a first processor having a built-in peripheral function and a second processor, and the second processor has a built-in peripheral function. In a multiprocessor system in which a peripheral function built in a first processor can be shared and used, a first processor storing information to be set in a control register of the peripheral function in a location that can be accessed from each of the first and second processors. and a second register for setting an interrupt factor indicating that it is a request to use the peripheral function; A predetermined content is set in a register, the first processor refers to the content of the second register, and sets the content of the first register to the control register of the peripheral function according to the content; It is designed to operate peripheral functions.

In this system, preferably, as a result of the first processor referring to the second register, if the interrupt factor is a request to use the peripheral function and the peripheral function is in a state where it can immediately respond, the first processor may refer to the second register. The first processor reads the contents of the first register and writes it to the control register, and when the interrupt factor is a request to use the peripheral function and the first processor is in a state where it cannot respond immediately. , the first processor reads out the contents of the first register and stacks it on the main memory, and when it becomes ready to respond to a request to use the peripheral function, the first processor reads out the contents of the first register and stacks it on the main memory. The stored information is read out and written to the control register.

The peripheral functions are, for example, DMA (-memory access) controllers 1 to 1.

When the peripheral functions are in a state where they can respond immediately,
For example, this corresponds to a case where the first processor and the second processor do not share an input/output device, and a case where the peripheral function is in a state where the peripheral function cannot immediately respond is, for example, a case where the first processor and the second processor do not share an input/output device. This corresponds to a case where the second processor shares an input/output device.

Preferably, the first processor accepts an interrupt for each section of the microprogram, and performs a series of processing related to writing to the controller register as interrupt processing for each section of the microprogram.

The system is, for example, a loosely coupled multiprocessor system that does not share a main memory, the peripheral function is a DMA controller, and the main memory of the second processor has an address when viewed from the first processor. "space" allocated to two addresses, said 1) M
When the A controller attempts to perform DMA on the main memory of the second processor, the A controller performs the DMA by simply setting the physical address seen from the second processor.
5. The system includes an adding means for adding a constant value to the DMA address so that The first and second registers may be provided within the bus arbiter that arbitrates for acquisition of usage rights.

[Function] In the present invention, a register that stores information to be set for a shared peripheral function and an interrupt factor indicating a request to use a shared peripheral function are set in a location that can be accessed from each processor that constitutes a multiprocessor. A register will be provided to A processor that wants to use a shared peripheral function writes information to be set for the peripheral function in the register, and at the same time sets the interrupt factor to cell 1. Thereafter, when a processor with a built-in peripheral function that receives an interrupt request determines that the cause is a request to use a shared peripheral function during interrupt processing, the internal peripheral function is ready to respond immediately. Determine whether it is true or not, and perform the following processing.

(1) If the peripheral function is ready to respond immediately when the register that sets the interrupt factor is referenced, the processor with the built-in peripheral function will read the contents from the register that stores the conditions set for the peripheral function. Read and write to registers inside its own peripheral. At this point, interrupt processing is completed, and the external processor is ready to start up additional peripheral functions.

(2) If the peripheral function is not able to respond immediately when the register for setting the interrupt factor is referenced,
A processor with a built-in peripheral function reads the contents from the register that stores article 11 to be set for the peripheral function, and
Form a stack in main memory. At this point, the interrupt processing ends. Then, when the peripheral function is ready to respond to usage requests, the processor with the built-in peripheral function reads out the conditions to be set for the peripheral function stacked in the main memory, and stores the internal functions of the white peripheral function. Write to register. At this point, is the peripheral function activated by an external processor? (0 preparations are now in place.

The means described above makes it possible to set information from an external processor to a shared peripheral function, and furthermore, even when requests for peripheral function use conflict, processing can be performed while sequentially setting information to the peripheral functions. You can go ahead and do it. That is, in a multiprocessor system, it becomes possible for other processors to efficiently utilize peripheral functions built into a processor.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention, in which 1 is an MPU, which is a first microprocessor with a built-in DMA controller, and 2 is a second microprocessor, MPU. 3 is a bus arbiter that arbitrates the right to use the lotus, 4 is a memory controller that controls the main memory of MPU 1, and 5 is a memory controller that controls the main memory of MPU 1.
6 is the main memory of the MPU 2 and is a local memory seen from the MPUI; 7 is the input/output device 1; 8 is the built-in DMA controller I-roller of the MPUI; 9 is the internal address bus of MPUI, ]O is MPUI
U]'s internal data bus, 1j, is the local memory 6
12 is a data latch register necessary for I) MΔ, 13 is MPl, J], , MP
From U2, read/write I - possible interrupt factor register, 14, address 1 with latch function - release direction control I - driver, 15, 3-stay I - bidirectional 1 - driver, which can put the lotus in a high impedance state; 16 is an address direction control 1-lime with a latch function, 17 is a 3-state bidirectional driver that can put the bus in a high impedance state,] 8 is a multiplex bus that multiplexes MPUI addresses and data, ] 9 is a system A1 address bus, 20 system data bus, 21 MPU2
, 22 is a data bus of MPU 2, 23 is a bus release request signal (REQ signal) from bus arbiter 3 to MPU l, 24 is a bus release signal (ΔCK signal''; j) from MPU, 1 to hash arbiter 3. ,
25 is a microsteel request signal that requests an interrupt at every break in the micro block of 84 PIJ3; 26
is an interrupt request signal from the MPU 2 requesting an interrupt to the bus arbiter 3, 27 is a read/write signal for accessing the main memory from the MPUI, a register or Ilo inside the path arbiter 3, and 28 is a register from the MPU 2 inside the bus arbiter 3. 2 are bus release request signals from MPU 2 to path arbiter 3, 30 are bus release signals from path arbiter 3 to MPU 2, and 31 are I10 read/write signals for conveying access signals from MPUI and MPU 2 to l107. Write signal, 32 is I from l107
) MA request signal (DREQ signal), 33 is l107
A DMA permission signal (DACK signal) 34 is a DMA1 movement signal for each channel from the bus arbiter 3 to the MPUI built-in DMA controller 8.

Figure 3 shows the M
The stack for DMA control of P T and J 2 is shown.

FIG. 4 is a detailed block diagram of the DMA controller 8 with built-in MPUI. In the figure, 101 is a DMA address register, and 102a and 102b are data registers for each channel, such as the transfer count, start address, and DMA transfer mode.
DMA information register for setting information necessary for MA, 10
3 is an adder that adds a constant value to the output of the DMA 71-less register.

In this embodiment, a loosely coupled multi-processor support system 11 in which MPU ] and MPU2 do not share the main memory is used.
However, it can be similarly applied to a multiprocessor system based on a convenience method. D inside
The MPUI having the MA controller 8 has a main memory 5 as a main storage device, and the memory controller 4 controls access to the main memory 5. On the other hand, the second processor M
PU2 has local memory 6 as a main storage device,
The memory controller 11 performs the access control.

FIG. 2 shows an address space map showing address allocation for MPU1 and MPU2.

The local memory 6 is allocated to addresses in the address space as viewed from the MPUI.

Regarding bus arbitration, the MPUI normally has the right to use the system address bus 19 and the system data bus 20, and in order for other bus masters including the MPU 2 to acquire bus rights, they must request the bus arbiter 3 to use the bus. Release request signal (bus release request signal 2 in case of MPU 2)
9) is asserted. The bus arbiter 3 requests the MPUI to release the bus using the REQ signal 23, and when notified of the release of the bus from the MPUI using the ACK signal 24, it performs internal priority control and uses the bus in descending order of priority. Control is performed to grant bus rights using a permission signal (bus release signal 30 in the case of MPU 2).

When MPUI and MPU2 perform DMA, MPU1
Built-in DMA controllers 1 to 8 are used. DMA in this system sets DMA information such as the number of transfer call 1, start address, DMA transfer mode, etc. in the internal register of the DMA controller 8, and the DMA controller 8 outputs only the address via the multiplex bus 18. This is the method.

The way the MPU 1 software performs DMA is as follows.

M P tJ ] is the built-in DMA controller 8
If necessary, set MA information in the internal register of .

Thereafter, necessary MA information is set in l107 by the ■/○ access command, and then a DMA request is output by the DREQ signal 32. Bus arbiter 3 that received this
uses the REQ signal 23 to request MI) TJ 1 to release the bus. At the time when bus release is notified by the ACK signal 24, the bus arbiter 3 outputs the DMA activation signal 34 to the DMA controller 1 to the roller 8, and also outputs the D ACK signal 33 to l107. , start DMA.

Next, a method for the rough 1 to wear of the MPU 2 to perform DMA will be explained.

First, the DMA method when Ilo is not shared with MPUI is as shown in the flowchart of FIG. At first,
The software of the MPU 2 sets necessary MA information in the I107 by the I10 access command (S51). Also, it is necessary to set the internal register of the DMA controller 8 with built-in MPUI, so set the MA information in the register 12 inside the bus arbiter 3, and set the fact that it is a DMA request by MP tJ 2 in the interrupt factor register 13. (S52). When the setting is completed, the bus arbiter automatically sends the MPU request signal 25.
An interrupt is placed at the break in the I microprogram. MPUI refers to the register inside the path arbiter 3 in the microsteel processing program, and if it determines that the cause is a DMA between MPUI and Ilo that is not shared, the MPUI is transferred from the register inside the bus arbiter 3.
Reads the DMA information set by U2 and connects the built-in DM
Set in the internal register of A controller 8 (S53)
.

After that, the MPUI software uses the T10 access command to activate ■107 and start DMA (
S54). At this time, the built-in DMA controller l-roller 8 simply sets the physical address seen from the MPU 2.
DM to the local memory area seen from vi P U ]
To enable A transfer, as mentioned above, adder 1.0
3, the structure is such that a fixed value can be added to the set value.

Next, DM when sharing 1/○ with M I) U]
Method A is as shown in FIG. At first, ■/○ is M.
Similar to the case where it is not shared with M P U 2
The software l-ware sets necessary MA information in the machine 107 by an I10 access command (S61). Also,
It is necessary to set it in the internal register of DMA controller 1-roller 8 built in MPU 1. Set M
, J2 l) If the interrupt cause register 13 is set to indicate that it is an M A request (S629. Setting or termination), the path arbiter 3 automatically issues a microsteal request (by Kichi-525 of the MPU1). Generate an interrupt at the break in the microprogram.M P L
J ] refers to the register inside the path arbiter 3 in the microsteel processing program, and the cause is the MPU.
If it is determined that the DMA is between Ilo and Ilo, which is shared by I, the DMA information set by the MPU 2 is read from the register inside the path arbiter 3 and stacked in the main memory 5''2 (S63). Next, update the pointer for the stutter (564) and the interrupt factor (shared with MPTJ2■/○
DMA request between the bus arbiter 3 and the bus arbiter 3 is set in the register 13 inside the bus arbiter 3 (865).

As a result, the path arbiter 3 outputs an interrupt request to the MPUI using the interrupt signal 26 (366).
. In this interrupt processing program, the MPUI refers to the register inside the bus arbiter 3 (567), and when it determines that the cause is a DMA between MPU 1 and Ilo, which is shared, the DMA controller 1-roller 8 interrupts the MPUI. When it is ready to accept DMA requests other than its own, the MPU 2 reads the I) MA information set in the register inside the hash arbiter 3 from the stack formed in the main memory 11J5. Built-in D
Set in the internal register of the MA controller 8. At this time, the stutter is usually a first-in-first I-out type, but it may also be a first-in-first I-out type. Continuing, the software is sent to software 1 of MPU1.
10 Access command activates D107 and D
MA is started (S68). Incidentally, if the interrupt cause is not a DMA request in step S67, the interrupt processing is performed (S69).

According to the present invention, in a multiprocessor system,
If a processor with a built-in DMA controller 1-roller is included among the plurality of processors, that DMA controller can be used without any inconvenience with another processor that does not have a DMA controller 1-roller built-in. This has the effect of increasing the efficiency of using built-in peripheral functions and building a multiprocessor system with high processing efficiency.

In the embodiment described in J-2, when sharing ■/○, the DMA information was stacked in the main memory, but instead of this, the path arbiter is configured to have multiple sets of registers 12 and 13, and the stack is stacked in the path arbiter. It may also be a method of forming.

[Effects of the Invention] According to the present invention, in a multiprocessor system,
When a processor with built-in peripheral functions is included, other processors can efficiently use the peripheral functions, so an efficient multiprocessor system can be constructed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the system configuration of the first embodiment of the present invention, and FIG. 2 is a block diagram showing the system configuration of the first embodiment of the present invention.
FIG. 3 is an address space map showing the address allocation of U2. FIG. P U ] Detailed block diagram of the built-in DMA controller 1 and roller 8, FIG. 5 is M I) U 2
but with an opening with Ilo that does not share with M PU 1
A flowchart of a series of procedures up to DMA activation when performing A. Figure 6 is a flowchart of a series of procedures up to DMA activation when MPU2 performs DMA between ■/○ shared with MPU1. Char 1-. 1. MPU which is the first microprocessor, 2.
MPU which is a microprocessor, 3 hash arbiter,
4 Memory controller, 5 Main memory, 6 Local memory, 7 Input/output device (T/○), 8 MPU
I built-in DMA controller 1~roller, 9-MPU 1 internal address bus, 10MPtJ] internal data bus,
1.2 DMA information data latch register, 13. Interrupt factor register, 14. Address direction control driver with latch function, 153 stage 1 to bidirectional driver,
Address direction control driver with 16 launch function, 173
Stay 1 to bidirectional driver, 18 multiplex bus, 19 system address bus, 20 system data bus, 21/MPU2 address bus, 22-M P
U 2 data bus, 23 Hass release request signal (REQ signal), 24 Bus release signal (ACK signal), 25 Micro steal request signal, 26 Interrupt request signal, 27 Read/write signal, 28... Read/write signal, 29. Bus release request signal, 30... Bus release signal, 31... I10 read/write signal, 32.
DMA request signal (DREQ signal), 33. DMA permitter number (DACK signal), 34. DMA activation signal, 101
- DMA address register, 1.02a. 102b...DMA information register, 103 - Adder.

Claims (1)

[Claims] 1. A multiprocessor comprising a first processor with built-in peripheral functions and a second processor, where the second processor can share and use the peripheral functions built into the first processor. In the system, a first register that stores information to be set in a control register of the peripheral function in a location that can be accessed from each of the first and second processors, and an interrupt factor that indicates a request to use the peripheral function. a second register for setting the peripheral function; the second processor sets predetermined contents in the first and second registers in order to use the peripheral function;
The first processor refers to the contents of the second register, sets the contents of the first register to a control register of the peripheral function according to the contents, and operates the peripheral function. multiprocessor system. 2. As a result of the first processor referring to the second register, if the interrupt factor is a request to use the peripheral function and the peripheral function is ready to respond immediately, the first processor reading the contents of the first register and writing them to the control register; when the interrupt factor is a request to use the peripheral function and the first processor is in a state where it cannot respond immediately;
The first processor reads out the contents of the first register and stacks it on the main memory, and stacks it on the main memory when it becomes ready to respond to a request to use the peripheral function. A multiprocessor system characterized in that information is read and written to the control register. 3. The multiprocessor system according to claim 1 or 2, wherein the peripheral function is a DMA (direct memory access) controller. 4. The case where the peripheral function is ready to respond immediately corresponds to the case where the first processor and the second processor do not share an input/output device, and the peripheral function is ready to respond immediately. 3. The multiprocessor system according to claim 2, wherein the case where the first processor and the second processor share an input/output device is a case where the first processor and the second processor share an input/output device. 5. A multiprocessor system, wherein the first processor receives an interrupt for each section of the microprogram, and performs the series of processing according to claim 2 as interrupt processing for each section of the microprogram. 6. The system is a loosely coupled multiprocessor system that does not share the main memory, and the peripheral functions are D
The DMA controller is an MA controller, in which the main memory of the second processor is allocated to a different address in an address space when viewed from the first processor, and the DMA controller is a DMA controller with respect to the main memory of the second processor.
Claim 1, characterized in that the processor further comprises an adding means for adding a fixed value to a DMA address so that when attempting to perform A, DMA can be performed simply by setting a physical address seen from the second processor. The multiprocessor system described. 7. A system address bus, a system data bus, and a bus arbiter that arbitrates between the first and second processors to obtain the right to use the system address bus and the system data bus; 2. The multiprocessor system according to claim 1, further comprising a second register.