JP3206013B2 - Direct memory access transfer controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a direct memory
The present invention relates to a DMA transfer control device that performs high-speed data transfer between memories in different areas and between a memory and a peripheral device by an access (hereinafter, referred to as DMA) method.

[0002]

2. Description of the Related Art The DMA system is one of widely used high-speed data transfer systems, and a control device for performing the DMA transfer is indispensable for an information processing device. This DMA transfer method includes a case where data in a specified area in a memory is read and transferred to another area (hereinafter referred to as a DMA transfer between memories), a case where data is transferred between a peripheral device and a memory, and the like. Here, DMA transfer between memories will be described.

The DMA transfer mode includes a mode in which data in a designated area is all transferred by one DMA request, and a mode in which data is transferred only while a DMA request signal is active. In a DMA transfer between memories, a form in which the execution of DMA is controlled by a DMA request signal is not suitable, and almost all data is transferred continuously by one DAM request.

FIG. 5 is a block diagram showing an example of an information processing device including a conventional DMA transfer control device. Upon receiving the DMA request signal 100, the DMA transfer control device 303 activates the bus control request signal 310 from the transfer control unit 314 to the bus control circuit 301 of the central processing unit 300 (hereinafter, referred to as CPU), thereby granting the right to use the bus. Request. The bus control circuit 301 arbitrates bus control requests from the arithmetic processing circuit 302, the refresh control device 306, and the like, and activates the bus control permission signal 311 when there is no request with a higher priority due to a DMA bus control request. The address bus 32 to the DMA transfer control device 303.
0, permit use with the data input / output bus 321.

When the right to use the bus is obtained, the DMA transfer control device 303 performs DMA transfer by repeating the following operations (1) to (3) by the transfer control unit 314. (1) An address of a transfer source (hereinafter referred to as a source) area in the memory 304 or in the memory 305 is assigned to the address bus 3
20 and read data via the data input / output bus 321. Also, the address is updated. (2) Subsequently, the address of the transfer destination (hereinafter referred to as destination) area in the memory 304 or the memory 305 is output to the address bus 320, and the data read from the source area via the data input / output bus 321 is written. . Also, the address is updated. (3) In order to count the number of transfers, the contents of the counter are updated (incremented) each time the data is transferred once.
I do.

Here, when the number of transfers reaches a value specified in advance, that is, when all data transfers in the specified area are completed, the bus control request signal 310 is made inactive, the bus use request is canceled, and the right to use the bus is released. Return to CPU 300. Further, the DMA end signal 110 corresponding to the DMA request signal 100 is activated to notify the DMA request source of the transfer end. After performing data processing of memory 304 and memory 305, CPU 300 again executes DM processing.
In order to perform the A transfer, the control information is reset for the DMA transfer control device 303 and the like.

In addition, the DMA transfer control device 303 has a plurality of transfer paths (hereinafter referred to as channels), and selects and executes a channel according to a request source. Each channel is assigned a priority for DMA processing.
When DMA requests for a plurality of channels occur at the same time, the priority control unit 315 determines the priority,
First, DMA transfer is performed from the channel with the highest priority.

[0008]

As described above, the conventional DM
In the DMA transfer between memories in the A transfer control device, there has been only a method of continuously transferring all data in a predetermined area by one DMA request. Therefore, the size of the source area and the destination area must be the same, and there is no one that is optimal for applications such as when the destination side does not have a very large area such as a buffer memory.

Therefore, a method of subdividing the designation of the source area according to the destination area can be considered.
Since the area that can be transferred at one time is narrowed, a transfer end state frequently occurs. Each time, processing such as resetting the DMA start address and the number of transfer data is required, and the software processing load on the CPU is large. Further, the DMA transfer efficiency is deteriorated because the next DMA request cannot be accepted until the CPU finishes these processes.

A DMA channel is allocated to each data unit of the destination area. For example, the source area is 1024 bytes, and the destination area is 2 bytes.
In the case of 56 bytes, a method was used in which four channels were used and each channel transferred 256 bytes. However, in this method, secondary problems have occurred such as an increase in software processing load and a decrease in memory use efficiency, such as occupying a plurality of DMA channels and making DMA transfer unavailable for other purposes. .

An object of the present invention is to realize, with simple hardware, a function capable of performing data transfer by DMA in accordance with a destination area for each DMA request, thereby greatly reducing the processing load on the CPU and peripheral devices. An object of the present invention is to provide a DMA transfer control device which can reduce the number of times and which can be optimally designed according to the application.

[0012]

According to the present invention, a transfer source
In direct memory access (DMA) transfer control device for transferring by direct memory access method of the data of the specified address in the memory to the transfer destination memory from the memory, the rolling to be the DMA transfer
It generates an address of Okusaki in memory, and an address generation circuit for updating, the transfer Ru source memory and to control the termination state before Symbol DMA transfer to determine the size of the memory area of the transfer destination memory <br/> Transfer An end control circuit, a storage circuit for storing various parameters related to the DMA transfer control, a bus control means for detecting occurrence of a valid DMA transfer request and controlling a bus use request, and responding to the bus use request. a transfer control circuit for executing DMA transfer by using the address and various parameters sequentially generating a transfer cycle in accordance with the use permission state of the bus, said that the predetermined address transfer is executed by one DMA transfer request Match with transfer destination address value
And an address detection means by detecting a
The output of the address detector is <br/> pause the DMA transfer is characterized in that to be able to split DMA transfer control.

In the present invention, the address detecting means may include one
An address register for setting a transfer end address in the memory to reach the times of the DMA transfer request, by comparing the content and DMA address of the address register can be made to have a comparison circuit for detecting the coincidence state in addition, the transfer end control circuit, and performs a transfer end control based on the number of detected coincidence state of the address detecting means
It can be.

[0014]

FIG. 1 is a block diagram showing one embodiment of a direct memory access (DMA) transfer control device according to the present invention. This DMA transfer control device receives a DMA request signal 100 from a peripheral device and controls a DMA request, and a DMA response control circuit 2 that outputs a DMA end signal 110 to a CPU, a peripheral device and the like.
01, a DMA access arbitration circuit 202, a source address 204 for storing a source address of a memory to be subjected to DMA transfer (hereinafter referred to as a DMA source address), and a destination address of the memory (hereinafter referred to as a DMA destination address). A destination address register 205, a source for each DMA transfer, and an address addition / subtraction circuit 206 for updating the contents of the destination address register. A DMA address generation circuit 203 for generating and updating DMA addresses, and a total number of transfer data Terminal count register 208 to be stored and subtraction circuit 2 for reducing the contents of terminal count register 208 each time one DMA transfer is executed
09, a terminal count control circuit 207 for controlling the total number of data in the memory to be DMA-transferred, that is, the size of the source area, and one DMA transfer.
It comprises an address detection circuit 210 for detecting an address of the destination area memory reached by the request, and a DMA address line 120 for supplying a DMA source address and a DMA destination address.

The source address register 204, destination address register 205, terminal count register 208, and address detection circuit 210
U address bus 320 (FIG. 5), data input / output bus 3
21 (FIG. 5), and is connected to the CPU 300 (FIG. 5).
Via these lines, the transfer start address of the source area memory is stored in the source address register 204, the transfer start address of the destination area memory is stored in the destination address register 205, the total number of transfer data is stored in the terminal count register 208, The transfer end address of the destination area memory is set in the address detecting means 210, respectively.

The DMA request control circuit 200 monitors the DMA request signal 100, and upon receiving a valid DMA transfer request, activates the DMA request flag signal 130 to notify the DMA access arbitration circuit 202 of the occurrence of the DMA request. . The DMA access arbitration circuit 202 activates the bus control request signal 310 to the bus control circuit 301 (FIG. 5) of the CPU at a predetermined timing,
Instead of U300, it requests that the DMA transfer control device control an address bus and a data input / output bus (hereinafter, these are collectively referred to as a bus).

The bus control circuit 301 arbitrates the right to use the bus, and responds by activating the bus control permission signal 311 when there is no request having a higher priority than the bus use request by the DMA transfer. Bus control permission signal 31
When 1 becomes active, the DMA access arbitration circuit 202
Activates one of the DMA execution permission signals 140
Start the execution cycle of A.

In the execution cycle of the DMA, the following (1) to (1)
(6) is repeated to sequentially transfer data from the source area to the destination area. (1) Source address register 20 of channel being executed
4 is read, and a DMA address is generated. DM
The data is output via the A address line 120, and data is read from this address. (2) The operation is performed by the address addition / subtraction circuit 206 and written back to the source address
Update the source address. (3) Read the contents of the destination address register 205 of the channel being executed, and generate a DMA address. Output via DMA address line 120;
The data read from the source area is written to the address. (4) The operation is performed by the address addition / subtraction circuit 206, and the DMA destination address is updated by writing back to the destination address register 205 again. (5) The address detection circuit 210 determines whether the destination address has reached a predetermined value (address). (6) The contents of the terminal count register 208 are read out, reduced by the subtraction circuit 209, and written back again to control the total number of transfer data. (7) Here, when the address detection circuit 210 detects that the destination address has reached the preset transfer end address, the match detection signal 160 is activated. This match detection signal 160
The DMA request control circuit 200 resets the DMA request flag signal 130 when the coincidence detection signal 160 becomes active, and stops the DMA transfer. Further, the destination address register 205 is reset to the transfer start address of the destination area memory.

When a DMA request occurs again, the above (1) to (7) are repeated to execute DMA transfer. Further, the terminal count register 208, the subtraction circuit 2
When the preset total number of transfer data is counted by 09, the DMA end detection signal 150 is activated.

When the DMA response control circuit 201 detects that the DMA end detection signal 150 has become active, it notifies the CPU and peripheral devices of the end of a series of data transfer by DMA.

FIG. 2 is a block diagram of the address detection circuit 210 of FIG. This address detection circuit performs one D
It comprises a transfer end address register 10 for setting a transfer end address of the destination area memory reached by the MA request, a comparison circuit 20, and an AND gate 30.

The transfer end address register 10 has a CPU
Are connected to the CPU 300 via an address bus 320 and a data input / output bus 321 of the CPU.
Prior to performing the MA transfer, 1
The transfer end address of the destination area memory to be reached by the DMA request is set. Comparison circuit 20
Compares the value set in the transfer end address register 10 with the address output on the DMA address line 120, and activates the coincidence signal 40 when both are equal. The AND gate 30 receives the DMA execution permission signal 140, the coincidence signal 40, and the destination cycle period signal 41, and generates a coincidence detection signal 160.

Next, the operation of the address detection circuit 210 will be described. FIG. 3 is an operation timing chart of the address detection circuit. In this embodiment, the transfer start address of the destination area memory is "256", and the transfer end address is "511". That is, a case where the size of the destination area memory is 256 bytes will be described as an example.

In the bus cycle (A), a DMA request occurs, and the DMA request flag signal 130 becomes active "1". At this time, if there is no bus use request higher than the DMA and the bus use by the DMA is permitted, the DMA execution permission signal 14 starts from the bus cycle (B).
0 becomes active, and DMA transfer is started. The destination address register 205 is incremented during a period when both the DMA execution permission signal 140 and the destination cycle period signal 41 are at the high level, and the destination address becomes “257” in the bus cycle (C).

Similarly, the DMA transfer is repeated and incremented in the bus cycles (X) and (Y), so that the destination addresses are "510" and "5", respectively.
11 ”. Since“ 511 ”is set in the transfer end address register 10,
In the bus cycle (Y), the transfer end address register matches the destination address, and the match detection signal 160 becomes active. When the match detection signal 160 becomes active, the DMA request flag signal 130 is reset, and the DMA transfer stops. When a DMA request occurs again, in the bus cycle (Z), the destination address becomes “256” and the source address becomes
Resume transfer from the next address.

As described above, in this embodiment, the stop control of the DMA transfer is performed by detecting that the destination address has reached the predetermined value (transfer end address) and resetting the DMA request flag signal. . Therefore, the data in the source area can be divided and transferred according to the destination area for each DMA request.

In this embodiment, the number and types of the DMA request signals are not particularly mentioned, but the number and types of the request signals are not restricted, and the capacity to be transferred by one DMA request is increased or decreased. In this case, it can be easily realized.

FIG. 4 is a block diagram showing a DMA transfer control device according to a second embodiment of the present invention, where the same parts as those in the first embodiment are denoted by the same reference numerals. In this embodiment, the terminal count control circuit 217 receives the coincidence detection signal 160 and subtracts the content of the terminal count register 208 every time a coincidence detection state occurs.
Decrease by 9 That is, it is decremented each time transfer to the destination area by one DMA request is completed.

The DMA end detection signal 150 output from the terminal count control circuit 217 is supplied to the DMA response control circuit 201 as in the first embodiment. Therefore, the total number of data in the source area can be controlled depending on how many times the division transfer to the destination area is performed.

As described above, in the present embodiment, the terminal count control circuit 217 only needs to control how many times the divided transfer to the destination area has been performed. Hardware is simplified.

[0031]

As described above, according to the present invention, the destination address has a predetermined value (transfer end address).
Has been reached, and the DMA transfer stop signal is reset by resetting the DMA request flag signal. This has the following effects. (1) The number of data according to the capacity of the designated area in the memory is 1
Since the function of dividing and controlling the transfer for each DMA request can be realized with simple hardware, it can be used for applications such as applications such as DAM transfer between memories with a relatively small capacity area such as a buffer memory. An optimal design according to the requirement can be achieved. (2) As in the case where the designation of the source area is subdivided in accordance with the destination area, the transfer end state frequently occurs because the area that can be transferred at one time is narrowed.
Each time, processing such as resetting of the DMA start address and the number of transfer data is not required, and the load of software processing on the CPU can be greatly reduced. Further, since the next DMA request is not accepted until the processing is completed, the DMA transfer efficiency can be improved. (3) A plurality of D channels are allocated, as in the case where a DMA channel is assigned to each data unit in the destination area.
Since it can be realized with only one DMA channel without occupying the MA channel, the use efficiency of the memory and the DMA channel is significantly improved. (4) Since the number of times of division transfer can be used for the total area determination control of the memory, hardware such as a terminal count register and a subtraction circuit is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a DMA transfer control device of the present invention.

FIG. 2 is a block diagram illustrating an example of an address detection circuit in FIG. 1;

FIG. 3 is an operation timing chart of the DMA area control of FIG. 1;

FIG. 4 is a block diagram of a DMA transfer control device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of an information processing device including a conventional DMA transfer control device.

[Explanation of symbols]

 Reference Signs List 10 Transfer end address register 20 Comparison circuit 30 AND gate 40 Match signal 41 Destination cycle period signal 100 DMA end signal 110 DMA response signal 120 DMA address line 130 DMA request flag signal 140 DMA execution enable signal 150 DMA end detection signal 160 Match detection Signal 200 DMA request control circuit 201 DMA response control circuit 202 DMA access arbitration circuit 203 DMA address generation circuit 204 Source address register 205 Destination address register 206 Address addition / subtraction circuit 207, 217 Terminal count control circuit 208 Terminal count register 209 Count subtraction Circuit 210 Address detection circuit 300 CPU 301 Bus control circuit 302 Arithmetic processing circuit 30 3 DMA transfer control device 304 First memory 305 Second memory 306 Refresh control device 310,313 Bus control request signal 311 Bus control permission signal 314 Transfer control unit 315 Priority control unit 320 Address bus 321 Data input / output bus

Claims (3)

(57) [Claims] A direct memory access (DMA) transfer control device for transferring data at a specified address in a memory from a transfer source memory to a transfer destination memory by a direct memory access method. An address generation circuit for generating and updating an address in the transfer destination memory to be subjected to the DMA transfer ;
Before SL DMA determines the size of the memory area of the transfer destination memory
A transfer end control circuit for controlling a transfer end state;
A storage circuit for storing various parameters related to MA transfer control, a bus control means for detecting the occurrence of a valid DMA transfer request and controlling a bus use request, and a bus use permission state in response to the bus use request A transfer cycle is sequentially generated according to the address and the DM using the address and various parameters.
The rolling and transfer control circuit for executing A transfer that by one DMA transfer request in a predetermined address transfer is executed
And a address <br/> less detection means by detecting a coincidence between Okusaki address value, a split controls DMA transfer is paused DMA transfer from <br/> the output of the address detector
Direct memory, characterized in that it has been cut way
Access transfer control device. 2. An address detecting means for comparing an address register for setting a transfer end address of a memory reached by one DMA transfer request with a content of the address register and a DMA address, 2. The direct memory access transfer control device according to claim 1, further comprising a comparison circuit for detecting a state. 3. The direct memory access transfer control device according to claim 1, wherein the transfer end control circuit controls the transfer end based on the number of times the address detecting means detects the coincidence state.