JP2972557B2 - Data transfer control device and control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device, and more particularly, to a data transfer control device for directly transferring data between memories.
The present invention relates to a data transfer control device performed by a memory access method.

[0002]

2. Description of the Related Art Generally, in an information processing system using a microcomputer, a central processing unit (hereinafter, referred to as a central processing unit) is used.
In many cases, data processed and processed by a CPU is stored in a corresponding memory, and a large amount of the stored data is transferred to another memory. For example, in a display control processing system, a CPU
In the above, the processed and processed display data is written in a memory, and every time a transfer request is generated from a display control device included in the display control processing system, display data for one screen is read out from the memory in a predetermined manner. An operation of transferring the data to the display memory is performed. At this time, if the peripheral device such as the display control device interrupts the CPU when it is defeated, and the above-described data transfer is performed in the interrupt routine, the overhead due to the interrupt process in the CPU increases. However, in order to reduce the data transfer efficiency of the display control processing system, as a countermeasure, a data transfer control device (direct memory access device) dedicated to DMA data transfer is used.
Controller: DMAC) is used. In the following, this data transfer by the DMAC is referred to as DMA transfer.

As described above, when performing the DMA transfer,
First, a memory address at which data is to be transferred, a DMA
Various control information such as the number of transfers is set in the DMAC in advance by executing a command from the CPU. Next, DM from a peripheral device (for example, a display control device or a print control device) is performed.
When the A transfer request is detected in the DMAC, the DMAC
From then on, it is required to give the CPU the right to use the bus. When this request is detected in the CPU, the right to use the bus including the address bus and the data bus is changed to the DMA bus.
The DMAC transfers the data stored in the memory to another memory area by generating address information and a read / write control signal using an empty bus. Done. By repeatedly performing such a DMA transfer operation, when the data transfer for the number of transfers (for example, the number of display data of one screen) is completed, the DMAC sends a DMA to the CPU.
A notification of the transfer end is transmitted. In response, the CPU detects the end of the DMA transfer, and executes the interrupt processing and the interrupt processing program routine. In this interrupt processing program routine, the CPU resets various control information of the DMAC in preparation for execution of the next DMA transfer, and starts the DMA transfer again.

The above-described embodiment of the conventional DMAC will be described by taking as an example a case where it is applied to data transfer on the memory side in an information processing system. The configuration of the information processing system is the same as that of an information processing system applied in an embodiment of the present invention described later, and as shown in FIG.
A microcomputer 11 including a DMAC 1, a peripheral device 13, and a CPU 14, and DMA transfer source areas A15, D
The memory 12 includes an MA transfer destination area A16, a DMA transfer source area B17, and a DMA transfer destination area B18. In FIG. 2, a CPU 146 included in the microcomputer 11 has a program
It has a counter (hereinafter, referred to as PC), a program status word (hereinafter, referred to as PSW), various registers, etc., controls execution of various instructions, and has an address bus and a data bus with the DMAC1. In addition, operation control relating to the entire information processing system is performed, including control over the right to use the bus 101 composed of read signals, write signals, and the like.

[0005] In the microcomputer 11, data generation and processing are performed, and the data output is written to the DMA transfer source area A 15 or the DMA transfer source area B 17 included in the memory 12. When a DMA transfer request from the peripheral device 13 occurs, the
The control operation of the information processing system as a whole, that is, data transfer to the corresponding DMA transfer destination area A16 or DMA transfer destination area B18 is executed by AC1. In this case, the memory 12 has a program area and a data area of the CPU 14, a DMA transfer source area A15 and a DMA transfer source area B17 included in the DMA transfer source area, and a DMA transfer destination area A16 included in the DMA transfer destination area. And a DMA transfer destination area B18. Various data in the information processing system are input and stored via the bus 101 under the control of either the CPU 14 or the DMAC1. The CPU 14 of the microcomputer 11 includes therein a PC, a PSW, various control registers, and the like. The CPU 14 controls execution of various instructions and performs an address bus, a data bus, a read signal, a write signal, etc. with the DMAC 1. And the operation control including the control of the right to use the bus 101.

FIG. 6 is a block diagram showing a configuration of a conventional DMAC 1 according to an embodiment. As shown in FIG.
The MAC 1 has a memory address source register (hereinafter, referred to as MASR) 7 for storing DMA transfer source address information, and a MASR 8 for storing head address information of the next DMA transfer source area, corresponding to the bus 101. , MAS
An address updating unit 6 for updating the storage content of R7,
Memory destination address register (hereinafter referred to as MDAR) for storing transfer destination address information
31, an MDAR 32 for storing the start address information of the next DMA transfer destination area, an address updating unit 10 for updating the stored contents of the MDAR 31, a terminal counter (hereinafter referred to as TC) 4 for storing the number of transfer data. And the next D
TC5 for storing the number of transfer data for the MA transfer area
A decrementer 3 for decrementing the contents stored in the TC 4, a data latch 9 for temporarily storing DMA transfer data, a control on the right to use the bus 101 between the CPU 14, and a transfer timing during the DMA transfer operation DM including control and update control of each internal register
And a DMA execution control unit 2 for controlling the entire A transfer. The DMAC 1 receives a DMA transfer request signal 102 from the peripheral device 13 and
4 through the transfer of the bus use right release request signal 103 and the bus use right permission signal 104 between the CPU 14
, The bus use right is secured, and the DMA
From the transfer source area A15 or the DMA transfer source area B17,
DMA transfer to the corresponding DMA transfer destination area A16 and DMA transfer destination area B18 is executed. The storage area of the memory 12 includes a program area, a data area, a DMA transfer source area A15, a DMA transfer source area B17, a DMA transfer destination area A16, and a DMA area in the CPU 14.
A transfer destination area B18 and the like are included, and CPU 14 and D
Various data of the information processing system is stored in the memory 12 via the bus 101 including the address bus, the data bus, the read signal, the write signal, and the like by one of the control operations of the MAC 1.

Here, a description will be given of the processing performed by the CPU 14 in the information processing system to which the conventional embodiment is applied. In the CPU 14, DM
Prior to the A transfer, the DMA transfer source area A shown in FIG.
The transfer data is written in advance up to the last data included in the data. Thereafter, initialization for the DMA transfer shown in the flowchart of FIG. 7A is performed. That is, the DMA transfer source start address (the head address of the DMA transfer source area A15) is set in the MASR 7 (step 71), and the DMA transfer destination start address (the head address of the DMA transfer destination area A16) is set in the MDAR31. (Step 72). Also, the following DM is included in MASR8.
The start address of the area to be the A transfer source (DMA transfer source area B17) is set (step 73), and the area to be the next DMA transfer destination (DMA transfer destination area B) is set in the MDAR 32.
18) The start address is set (step 74).
The number of DMA transfer data is set for TC4 (step 75), and the number of transfer data of the area for performing the next DMA transfer is set for TC5 (step 76).
A transfer is permitted (step 77), and the processing by the CPU 14 ends.

As described above, when the DMA transfer is enabled, the data written in the DMA transfer source area A15 by the DMAC 1 is transferred to the DMA transfer destination area A16. During a period other than the time when the above-described DMA transfer is executed, the CPU 14 controls the DMA transfer source area B17.
, DMA transfer data is written. When the DMA transfer is completed up to the last data in the DMA transfer source area A15, the DMAC1 outputs an activated DMA interrupt request signal 105 to the CPU 14, and the completion of the DMA transfer is transmitted to the CPU 14, and subsequently,
Transfer the data in the DMA transfer source area B17 to the DMA transfer destination area B
DMA transfer for transfer to the CPU 18 is started. When the CPU 14 detects the occurrence of the DMA interrupt request,
C and PCW are saved on the stack, and the interrupt processing program routine is started, as shown in FIG. In this program routine, in order to prepare for the next DMA transfer, the CPU 14
The start address of the area to be the next DMA transfer source (DMA transfer source area A15) is set in R8 (step 8).
1) The start address of the area to be the next DMA transfer destination (DMA transfer destination area A16) is set in the MDAR 32 (step 82). Next, the number of data in the DMA transfer area A is set for TC5 (step 83). After that, in the CPU 14, PC and P
CW is returned from the stack. During a period other than the time when the DMA transfer is performed on the data in the DMA transfer source area A15, the CPU 14 causes the DMA transfer source area A1 to execute.
5 is written.

Similarly to the above, when the DMA transfer up to the last data of the DMA transfer source area A15 is completed, the DMAC 1
As a result, the activated DMA interrupt request signal 105 becomes C
This is output to the PU 14 to notify the CPU 14 of the completion of the DMA transfer, and to continuously transfer the data in the DMA transfer source area A15 to the DMA transfer destination area A16.
MA transfer is started. As described above, the DMA transfer source area A15 and the DMA transfer source area B17 are alternately set as the targets of the DMA transfer source or the targets of the data writing by the CPU.

Next, in this conventional embodiment, the DM
An operation when data in the A transfer source area is transferred to the DMA transfer destination area will be described. In the information processing system of FIG. 2, when it becomes necessary for the peripheral device 13 to DMA-transfer data for the number of times set in the TC4 of the DMAC 1, the peripheral device 13 sends the DMA transfer request signal 1
02 is activated and supplied to DMAC1. DMAC
In 1, in response to the input of the DMA transfer request signal 102, the bus use release request signal 103 is activated and output and input to the CPU 14, requesting the CPU 14 to use the bus 101. In the CPU 14, the data generation processing and the generated data
Predetermined program processing including processing for storing in the MA transfer source area A15 or the DMA transfer source area B17 is being executed, and at the same time, the state of the bus use right transfer request signal 103 output from the DMAC 1 is constantly monitored. . Therefore, the above bus use right transfer request signal 103
Is activated and input from DMAC1, CPU 1
4, the contents of the PC, PCW and various registers are held as they were when the program was executed, and the bus use permission signal 104 is activated and output to the DMAC 1. It is reported that the right to use has been granted. In the DMAC 1, since the right to use the bus is given, the MAC is connected via the signal line 108.
When the DMA transfer source address stored in SR7 is bus 1
01, and at the same time, the memory read signal is activated, and the transfer data is transferred from the memory 12 to the data latch 9.
Is taken in. Subsequently, the signal line 10 is provided by the DMAC1.
7, the DMA transfer destination address stored in the MDAR 31 is output onto the bus 101, and the transfer data captured by the data latch 9 is output onto the bus 101, and at the same time, the memory write signal is output. When activated, the transfer data is written into the memory 12.

Thus, every time one DMA transfer is executed, the contents of MARS 7 and MDAR 31 are
The address is updated by the corresponding address updating unit 6 and address updating unit 10, respectively. The contents of the TC 4 storing the number of transfer data are set to “1” by the decrementer 3.
Is decremented. Here, after the execution of one DMA transfer, the DMA transfer request signal 10
If the DMAC 2 is still detected in the active state in the DMAC 1, the above-described DMA transfer is repeatedly executed. When the DMA transfer request signal 102 is not activated, the DMAC 1 makes the bus use right transfer request signal 103 inactive,
The release of the right to use the bus 101 is transmitted to the PU 14. When the right to use the bus is regained, the CPU 14, PC, PCW, and various registers immediately retain the values before the interruption of the program processing.
Execution of the suspended program processing is resumed.

When the above-described DMA transfer is repeatedly executed and the data transfer for the designated number of times is completed, the DMAC 1 decrements the value of the number of data transfers stored in the TC 4 to 0 and outputs the value from the decrementer 3. According to the TC zero detection signal 106, the contents of MARS8 are loaded into MARS7, and the contents of MDAR32 are stored in MRS7.
Loaded to DAR31. Thus, when the next DMA transfer occurs, the data stored in the next DMA transfer source area is transferred to the next DMA transfer destination area.
The transfer is performed. At the same time, by activating the DMA interrupt request signal 105, the CPU 14
The completion of the MA transfer is transmitted. In this way, by repeatedly executing the above processing, the DMA transfer source area A1
5 to the DMA transfer destination area A16,
The DMA transfer is performed in an operation state in which the DMA transfer from the DMA transfer source area B17 to the DMA transfer destination area B18 is performed alternately and repeatedly.

[0013]

In recent years, as the cost of memories and the memory capacity have increased, various types of information processing systems can handle large-scale data. In a data transfer control device for DMA transfer, large-scale data transfer control is also required. However, in the above-described conventional data transfer control device, in order to perform such large-scale data transfer control, it is necessary to increase the bit configuration of each register included in the DMAC, MASR, MDAR, TC, and the like. And for this,
There is a drawback that the circuit scale of the DMAC is remarkably enlarged, and the required area of the entire semiconductor chip is increased.

Each of the above registers, MASR, MD
Initial setting processing in AR and TC, resetting processing by an interrupt processing program, and the like are executed by the CPU. In these processings, the setting for one register is processed by one instruction as the bit configuration increases. And it becomes necessary to process by two or three instructions. For this reason, there is a disadvantage that the program capacity is increased, and further, the program processing time is inevitably increased, and the processing time related to the setting process at the time of the DMA transfer is increased, so that the original processing speed of the CPU is reduced. There is a disadvantage that.

[0015]

A data transfer apparatus according to the present invention.
The feature of the present invention is that, in a data transfer control device for controlling DMA data transfer between memories by a direct memory access (DMA) method, a transfer count storage means for storing a value of a DMA data transfer count for a predetermined DMA transfer area. Transfer number updating means for updating the value of the number of times of execution stored in the number-of-transfers storage means every time a DMA data transfer is executed, and an address for storing an address of a predetermined DMA transfer source area as address information Storage means, address update means for updating the value of address information stored in the address storage means each time DMA data transfer is executed, and bit modification of the address information stored in the address storage means and address modification means for and outputting, is bit modified by the address modification means DMA transfer source stored DMA transfer destination address information that is a force with the address storing means
Address information switching means for inputting the address information and alternately switching the data in time series and outputting the data.
And the address modifying means performs a predetermined bit
An address modification register for storing a number of modification bits;
The DMA transfer stored in the address storage means
The value of each bit of the address of the original area and each of these bits
Output from the address modification register corresponding to
Input the value of the decoration bit and take the logical sum of each and output
And a plurality of OR gates
Logic level “1” in the
Modification target address of the DMA transfer source address corresponding to the fixed value
Set "0" to the address of the DMA transfer destination address.
Ru near possible to generate motion.

Further, prior Symbol address modification means inverts the first and second address modification register for storing the modified bit of Jo Tokoro number of bits, the value of each bit of the first address modification register Multiple inverters to output,
A plurality of first AND gate groups for performing an AND operation on inverted output values of the plurality of inverters and values of corresponding bits of the second address modification register;
And a plurality of second AND gate groups for outputting a logical product of the value of each bit of the address modification register and the value of the corresponding bit of the second address modification register; The value of each bit of the address of the DMA transfer source area and the output values of the plurality of first and second AND gate groups corresponding to each bit are input, and the logical sum is calculated respectively. And a plurality of OR gates for outputting.

[0017]BookData transfer control device of the inventionOther features of
Is based on the direct memory access (DMA) method.
Data for controlling DMA data transfer between memories.
In the data transfer control device, a predetermined DMA transfer area is
First transfer count that stores the value of DMA data transfer count
Each time a DMA transfer is performed,
The execution count stored in the first transfer count storage means.
Transfer number updating means for updating the value of the number;
DMA transfer count value for the DMA transfer area next to the area
Second transfer number storing means for storing
A first method for storing the address of the source area as address information
Address storage means and each time DMA data transfer is executed
Are stored in the first address storage means for each
Address updating means for updating the value of the address information;
The address of the DMA transfer source area next to the DMA transfer source area
Second address storage means for storing as address information
And the data stored in the first address storage means.
Address modification method that outputs address information with bit modification
Step and,thisBit modified by the address modification means
Address information andIn the first address storage means
StoredEnter the address informationTimeExchange in series
Address information switching means direct to switch and output each other
・ Between memories by the memory access (DMA) method
Transfer control device for controlling DMA data transfer in a computer
, DMA data for a predetermined DMA transfer area
First transfer count storage means for storing a transfer count value;
Each time the MA data transfer is executed, the first transfer
Update the value of the number of executions stored in the number storage means
Transfer number updating means, and a next DM in the DMA transfer area.
Second for storing the value of the number of DMA transfers for the A transfer area
Transfer number storage means and an address of a predetermined DMA transfer source area.
Address storage for storing addresses as address information
Means, and each time a DMA data transfer is performed,
1 of the address information stored in the address storage means.
Address updating means for updating a value;
The address of the DMA transfer source area next to the area is
Second address storage means for storing the first address and the first address.
The address information stored in the dress storage means.
Address modification means to output by modifying the address and this address
Output with bit modification byDMA conversion
DestinationAddress information and stored in the first address storage means
Has beenDMA transfer sourceEnter the address information and time system
Address information switching means for switching and outputting alternately in columns
And perform a DMA data transfer, and
The decoration means stores an predetermined number of bits for decoration.
Address modification register and the first address storage means.
Each bit of the stored DMA transfer source area address
And the address modifier corresponding to each of these bits
Enter the value of the modifier bit output from the register and
It is composed of a plurality of OR gates, each of which outputs a logical sum.
And a logical level is stored in the address modification register.
Is set to "1" and the DMA conversion corresponding to this set value is performed.
Set “0” to the modification target bit of the source address and
DMA transfer destination address can be automatically generated.

Further, prior Symbol address modification means, and the first and second address modification register for storing the modified bit of a predetermined bit number, by inverting the value of each bit of the first address modification register output Multiple inverters to
A plurality of first AND gate groups for performing an AND operation on inverted output values of the plurality of inverters and values of corresponding bits of the second address modification register;
A plurality of second AND gate groups for outputting a logical product of the value of each bit of the address modification register and the value of the corresponding bit of the second address modification register, and the first address storage means , And the output values of the plurality of first and second AND gate groups corresponding to these bits are input to the respective logical sums. And at least a plurality of OR gates for outputting the signals.

The control method of the data transfer control device of the present invention
Is based on the direct memory access (DMA) method.
Data for controlling DMA data transfer between memories.
In the control method of the data transfer control device, a predetermined DMA transfer
Transfer that stores the value of the number of DMA data transfers to the area
A number-of-times storage means, each time the DMA data transfer is executed;
And the execution stored in the transfer number storage means.
Transfer number updating means for updating the number of times;
Stores the address of the MA transfer source area as address information
Address storage means for executing the DMA data transfer.
Every time the address stored in the address storage means is
Address updating means for updating the value of the address information;
The address information stored in the dress storage means.
Address modification means to output by modifying the address and this address
Address that is bit-qualified and output by
Information and the address stored in the address storage means
Information that is input and switched alternately in chronological order and output.
The DMA data transfer by
At the time of execution and as the address modification means, a predetermined bit
Address modification register that stores the number of bits for modifying
And the DMA stored in the address storage means.
The value of each bit of the address of the transfer source area and each of these bits
Output from the address modification register corresponding to the
The values of the modifier bits, and OR each one.
And a plurality of OR gates for outputting
Initialization for the DMA data transfer and
Then, the DMA data is stored in the first address storage means.
The first address in which the start address of the area to be the data transfer source is set
Processing and the second address storage means store the following D
Second address in which the head address of the MA transfer source area is set
Processing, and the address modification register
The value to which the bit to decorate is set to the logical level "1" is set.
The third process and the first transfer count storage unit include
A fourth process in which the number of DMA transfer data is set;
In the transfer number storage means, the next DMA data transfer
A fifth process in which the number of transfer data in an area for performing
A sixth state in which the CPU enables the DMA transfer;
And the occurrence of a DMA interrupt request is detected.
Then, the CPU executes the DMA termination interrupt processing program routine.
And start the next DMA transfer.
The DMA transfer to said second address SL 憶means to obtain
Seventh processing in which the start address of the source area is set, and
Bit to modify the address in the address modification register.
Eighth processing in which the value set to “1” is set, and
The second transfer count storage means stores the next DMA transfer area.
A ninth process for setting the number of transfer data items is performed.
It is characterized by the following.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
I will explain. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. The first embodiment is an example of a data transfer control device (DMAC) when applied to data transfer in an information processing system formed using a microcomputer, and as shown in FIG. In one embodiment, a DMA execution control unit 2, a decrementer 3, terminal counters (hereinafter referred to as TC) 4 and 5, an address modification unit 6, a memory address source Register (hereinafter referred to as MA
SR, 7 and 8, a data latch 9, and an address updating unit 10. As is clear from the comparison with FIG. 6, the difference between the present embodiment and the conventional embodiment is that one combination circuit of the address updating unit and the MARD in FIG. 6 is deleted and the address modification unit is newly added. Is provided. FIG. 2 is a block diagram showing the configuration of the information processing system to which the present embodiment is applied, as in the case of the conventional embodiment.
The microcomputer 11 includes a microcomputer 11 including a PU 14 and a memory 12 including a DMA transfer source area A15, a DMA transfer destination area A16, a DMA transfer source area B17, and a DMA transfer destination area B18.

First, in connection with the description of the operation of this embodiment,
An information processing system to which the present embodiment is applied will be described with reference to FIG. In FIG. 2, a microcomputer 11 performs data generation and processing, and outputs the data to a DMA included in a memory 12.
The data is written to the transfer source area A15 or the DMA transfer source area B17. When a DMA transfer request is generated from the peripheral device 13, the DMAC 1
The control operation of the information processing system as a whole, that is, data transfer to the transfer destination area A16 or the DMA transfer destination area B18 is executed. In this case, the memory 1
2 includes a program area and a data area of the CPU 14 and a DMA transfer source area A1 included in the DMA transfer source area.
5 and a DMA transfer source area B17, and a DMA transfer destination area A16 and a DMA transfer destination area B18 included in the DMA transfer destination area.
Various data in the information processing system are input and stored via the bus 101 by the control action of any one of the above. The CPU 14 of the microcomputer 11 includes:
A PC, a PSW, various control registers, and the like are included therein to control execution of various instructions and to use the bus 101 including an address bus, a data bus, a read signal, a write signal, and the like with the DMAC 1. Operation control including control is performed.

DM included in the microcomputer 11
The configuration of AC1 is as summarized above,
A memory source address register (hereinafter, MASR) 7 for storing transfer source address information, a MASR 8 for storing head address information of a next DMA transfer source area,
An address updating unit 10 for updating the storage content of the SR 7;
An address modification unit 6 for modifying address information stored in the ASR 7;
In the transfer source area B17, a terminal counter (hereinafter referred to as TC) 4 for storing the number of data not yet subjected to the DMA transfer, a decrementer 3 for decrementing the stored content of the TC 4, and a next DMA transfer area , A data latch 9 for temporarily storing DMA transfer data, a control on the right to use the bus 101 with the CPU 14, a transfer timing control during a DMA transfer operation, and And a DMA execution control unit 2 for controlling the entire DMAC including the update control of each register.

FIG. 3 is a conceptual diagram showing the configuration of the address modification unit 6, which is a feature of the present invention. FIG.
In FIG. 2, only the part of the address modification unit 6 directly related to the operation function of the present invention is extracted and conceptually shown, and not all of the constituent elements are shown. For example, in FIG. 3, an address modification register (hereinafter referred to as AMD) 19 consisting of 3 bits is provided in the address modification unit 6.
And OR gates 20, 21 and 22 are provided. As an example, DM of MASR7 consisting of 24 bits is provided.
A case where the A transfer source address 109 is modified by the address modification unit 6 to generate a 24-bit DMA transfer destination address 110 is conceptually shown. The operation of the address modification unit 6 in the case where the 24-bit DMA transfer source address 109 is modified to generate the 24-bit DMA transfer destination address 110 will be described below with reference to FIG.

As shown in FIG. 3, it is assumed that “001” is set in the AMD 19. The value “0” of the bit 2 in the AMD 19 and the value “0” of the bit 20 of the DMA transfer source address 109 of the MASR 7 are input to the OR gate 20, and the OR output value “0” of the OR gate 20 is transferred to the DMA transfer. It is output as the value of bit 20 of the destination address 110. Similarly, the value “0” of the bit 1 in the AMD 19 and the value “1” of the bit 16 of the DMA transfer source address 109 of the MASR 7 correspond to the OR gate 21.
And the OR output value “1” of the OR gate 21 is
The value of bit 16 of the DMA transfer destination address 110 and the value “1” of bit 0 of the AMD 19 and the value “0” of bit 8 of the DMA transfer source address 109 of the MASR 7 are input to the OR gate 22. , O
The logical sum output value “1” of the R gate 22 is output as the value of bit 8 of the DMA transfer destination address 110.

As described above, when "0" is set in the AMD 19, the corresponding bit of the DMA transfer source address 109 of the MASR 7 becomes the value of the corresponding bit in the DMA transfer destination address 110 as it is.
9 is set to “1”, the D
The corresponding bit of the MA transfer source address 109 is set and becomes the value of the corresponding bit in the DMA transfer destination address 110. For bits other than bit 20, bit 16, and bit 8, the value set in the DMA transfer source address 109 of MASR 7 is used as it is in the DMA transfer.
It becomes the value of the corresponding bit in the transfer destination address 110.
As described above, if “1” is set in the AMD 19 and “0” is set in the corresponding bit of the DMA transfer source address 109, the DMA transfer destination address 110 is automatically generated by the address modification unit 6. You.

Next, the DMA transfer source area A15 or DM
A transfer source area B17 to corresponding DMA transfer destination area A
16 or the software processing on the CPU 14 side when data is transferred to the DMA transfer destination area A18,
FIG. 5A is a flowchart of a DMA start process, and FIG.
This will be described with reference to the flowchart of the DMA end interrupt processing of FIG. In FIGS. 5A and 5B, the address modification register 19 is abbreviated as AMD. Prior to the DMA transfer, transfer data up to the last data in the DMA transfer source area A is written in the CPU 14. In FIG. 5A, in the DMA start processing, first, initial settings for DMA transfer are performed. That is, the start address of the DMA transfer source area (DMA transfer source area A15) is set in MASR7 (step 51), and the start address of the next DMA transfer source area (DMA transfer source area B17) is set in MASR8. An address is set (step 52). In the address modification register 19,
A value in which the bit for address modification is set to "1" is set (step 53), the number of DMA transfer data is set in TC4 (step 54), and the next DMA is set in TC5.
The number of data to be transferred in the transfer area is set (step 55). Next, the CPU 14 converts the DMAC1 into a DM.
The A transfer is permitted (step 56), and the DMA start process ends.

When the CPU 14 enters the DMA transfer permission state, the data written in the DMA transfer source area A15 is transferred to the DMA transfer destination area A16 by the DMAC1. Also, the CPU 14 controls the DMA transfer source area B17 to store the D
MA transfer data is written. When the DMA transfer up to the last data in the DMA transfer source area A16 is completed,
In the DMAC1, by activating the DMA interrupt request signal 105, the completion of the DMA transfer is transmitted to the CPU 14, and the DMA transfer source area B1 is continued.
7 for transferring the data No. 7 to the DMA transfer destination area B16.
A transfer is started. When the CPU 14 detects the occurrence of the DMA interrupt request, the PC and PCW are evacuated to the stack, and the DMA end interrupt processing program routine shown in FIG. 5B is started.

In FIG. 5B, the program
In the routine, the CPU 14 stores the DMA transfer source area A1 in the MASR 8 in preparation for the next DMA transfer.
5 is set (step 61), and a value in which the bit for modifying the address is set to "1" is set in the address modification register 19 (step 62). Next, a process of setting the number of data to be transferred to the next DMA transfer area in TC5 is performed (step 63).
, The PC and PCW are returned from the stack. During periods other than the time when DMA transfer is performed on the data in the DMA transfer source area B17, the CPU 14
Thus, a process of writing data to the DMA transfer source area A15 is performed. As in the above case, the DMA transfer source area B1
When the DMA transfer up to the final data of No. 7 is completed,
C1 sends a DMA interrupt request signal 1 to the CPU 14
03 is output, and the DMA transfer for transferring the data in the DMA transfer area A15 is started. Thus, the DMA transfer source area A15 and the DMA transfer source area B17
Are alternately DMA transfer source targets or write targets by the CPU 14.

Next, the DMAC 1 transfers the corresponding DMA transfer destination area A16 or DMA transfer destination area B18 from the DMA transfer source area A15 or DMA transfer source area B17.
The operation of the DMA transfer with respect to is described specifically. In the peripheral device 13 shown in FIG. 2, when it becomes necessary to transfer data for the number of times set in TC4 to the DMA, the peripheral device 13 sends a DMA transfer request signal 102 to the DMA execution control unit 2 in the DMAC1. Is received, and upon receiving the DMA transfer request signal 102, D
In the MA execution control unit 2, via the bus use right release request signal 103 and the bus use right permission signal 104,
The right to use the bus 101 is given from the CPU 14. The DMAC 1 given the right to use the bus outputs the DMA transfer source address information stored in the MASR 7 via the signal line 107 onto the bus 101 and at the same time activates the memory read signal, Transfer data is taken into the data latch 9 from the memory. Then, D
According to MAC1, MASR 7
DMA transfer address information generated from the
8 on the bus 101 and the data latch 9
Is transferred onto the bus 101, and at the same time, the transfer data is written into the memory 12 by a memory write signal. Thus, one D
Every time the MA transfer is executed, the contents of the MASR 7 are read out to the address updating unit 10, and are written back after being updated to the next DMA transfer source address. The contents of the TC 4 storing the number of transfer data are decremented by “1” by the decrementer 3. When the DMA transfer request signal 102 is not continuously output from the peripheral device 13, the bus use right transfer request signal 103 output from the DMAC 1 to the CPU 14 becomes inactive. The release of the right to use the bus 101 is transmitted, and the DMA transfer operation ends.

When the above-described DMA transfer is repeatedly executed, when the transfer of the DMA data for the predetermined number of transfers is completed, the content of TC4 is decremented to zero. In the DMAC 1, the contents of the MASR 8 are loaded into the MASR 7 by the TC zero detection signal output from the TC 4 via the signal line 106, and at the same time, the TC
5 is loaded into TC4. As a result, the next D
When an MA transfer request occurs, a DMA transfer is performed in which data stored in the DMA transfer source area B17 is transferred to the DMA transfer destination area B18. At the same time, the DMA interrupt request signal 105 input from the DMAC 1 to the CPU 14 is activated, and the CPU 1
4 is notified of the completion of the DMA transfer.

By repeatedly executing the above processing, the DMA transfer source area A15 is shifted from the DMA transfer destination area A1.
6 and the DMA transfer from the DMA transfer source area B17 to the DMA transfer destination area B18 are performed alternately and repeatedly. In the address modification unit 6 described above, the logical transfer of the value of the bit set in the MASR 7 and the value set in the address modification register 19 included in the address modification unit 6 is performed to obtain the DMA transfer destination address. The DMA transfer is performed by taking the logical product or exclusive OR of the value of the bit set in the MASR 7 and the value set in the address modification register 19 included in the address modification unit 6. Even if the destination address is generated, it goes without saying that the same DMA transfer is performed.

Next, a second embodiment of the present invention will be described. As in the first embodiment, this embodiment is an example of a data transfer control device (DMAC) when applied to data transfer in an information processing system formed by using a microcomputer. The configuration of the processing system is exactly the same as that of the first embodiment shown in FIG. This embodiment is different from the first embodiment in the difference in the internal configuration of the address modification unit 6 in FIG. 1. A conceptual diagram of the internal configuration is shown in FIG. Therefore, in order to avoid duplication of the description of the operation with the first embodiment, the operation of the present embodiment will be described below mainly on the operation due to the difference in the internal configuration of the address modification unit 6. .

FIG. 4 is a conceptual diagram of the configuration of the address modification unit 6 in the present embodiment, as described above. In FIG. 4, as in the case of FIG. 3 described above, only the part directly related to the operation function of the address modification unit 6 in the present embodiment is extracted and conceptually shown. Not shown. For example, in FIG. 4, the address modification unit 6 includes an address bit consisting of two bits.
A select register (hereinafter referred to as ASL) 23 and A
MD 24, inverters 25 and 26, AND gates 27, 28, 29 and 30, and OR gates 31, 3
2, 33 and 34 are provided, and as an example,
The case where a 24-bit DMA transfer destination address 112 is generated by modifying the 24-bit DMA transfer source address 111 of the MASR 7 by the address modification unit 6 is conceptually shown. Hereinafter, referring to FIG. 4, the DMA transfer source address 111 is modified so that the DMA transfer destination address 1
The operation of the address modification unit 6 when generating the address 12 will be described.

As shown in FIG. 4, it is assumed that "01" is set in the ASL 23 and "11" is set in the AMD 24. The value “0” of bit 1 in the ASL 23 is inverted by the inverter 25, and the output value “1” is input to the AND gate 27 and also directly input to the AND gate 28. The value “1” of the bit 1 in the AMD 24 is also input to the AND gate 27, and an output value “1” based on a logical product with the output value “1” of the inverter 25 is output.
Input to the R gate 31. The value “0” of the bit 20 of the DMA transfer source address 111 is also input to the OR gate 31, and is ORed with the output value “1” of the AND gate 27, and the output value “1” is obtained. "Is DM
It is output as a 20-bit value in the A transfer destination address 112. As described above, the value of bit 1 in the ASL 23 and the value of bit 1 in the AMD 24 are also input to the AND gate 28, as described above. Is output and input to the OR gate 32. The value “0” of bit 16 of the DMA transfer source address 111 is also input to the OR gate 32, and the logical sum of the value and the output value “0” of the AND gate 28 is calculated, and the output value “0” is obtained. "Is DM
It is output as a 16-bit value in the A transfer destination address 112.

Similarly, the value “1” of bit 0 in the ASL 23 is inverted by the inverter 26, and the output value “0” is input to the AND gate 29 and also directly to the AND gate 30. AND gate 29
, The value “1” of bit 0 in the AMD 24 is also input, and an output value “0” is obtained by ANDing the output value “0” of the inverter 26 with the OR gate 33.
Is input to The value “0” of the bit 12 of the DMA transfer source address 111 is also input to the OR gate 33, and is ORed with the output value “0” of the AND gate 29, and the output value “0” is obtained. "Is the DMA transfer destination address 11
2 is output as a 12-bit value. Also, A
For the ND gate 30, as described above, the ASL 23
, The value “1” of bit 0 in the AMD 24 is also input, and the output value “1” of the logical product of these is output, and the OR gate 34
Is input to The value “0” of the bit 8 of the DMA transfer source address 111 is also input to the OR gate 34, and is ORed with the output value “1” of the AND gate 30 to obtain the output value “1”. "Is the DMA transfer destination address 112
Is output as an 8-bit value.

Thus, bit 1 in ASL 23
The values bi <br/> Tsu the value of bets, DMA transfer source address 111 of MASR7 modifying the value of bit 1 in AMD24
Bit 20 and selects the value or these bits 16 in, also, the value of bit 0 in ASL23, the value of the bit to be modified by the value of bit 0 in AMD24, MASR
In 7 of the DMA transfer source address 111 value or al-selected bit 12 and bit 8. The value of the bit selected by the ASL 23 is modified by the value of the bit of the AMD 24 to generate the value of the corresponding bit of the DMA transfer destination address 112. For bits 20 and 16, unselected bits out of bits 12 and 8, and bits other than bits 20, 16, 12 and 8, the value of MASR 7 is used as is for the DMA transfer destination address 112 as it is. Generated as a bit value. In the first embodiment, at the start of the DMA transfer and at the
As the processing in the CPU 14 at the time of the A end interrupt, the setting for the AMD 24 is performed (FIG. 5).
(See step 53 in FIG. 5A and step 62 in FIG. 5B.) In the present embodiment, the CPU
14, the processing contents of AMD 24 and AS
The setting in L23 is performed.

As described above, if “1” is set in the AMD 24 and the bit of the DMA transfer source address 111 selected in the ASL 23 is set to “0”, the DM
The A transfer destination address 112 is automatically generated by the address modification unit. Further, in the present embodiment, the AMD
Since the bit modified by 24 can be selected by the ASL 23, there is an advantage that the area to be DMA-transferred can be allocated to a more free memory area.

[0038]

As described above, according to the present invention, in an information processing system including a microcomputer, a DM
A DMA transfer destination address can be automatically generated by providing a simple address modification means for generating a DMA transfer destination address from a DMA transfer source address, which is applied for A data transfer. The circuit size can be reduced by eliminating a register for storing a DMA transfer destination address conventionally required and a register for storing a next DMA transfer destination address. is there. In particular, in a single-chip microcomputer provided with another peripheral device, the area occupied by the DMA transfer control means is suppressed to a minimum, so that the required area of the semiconductor chip can be reduced.

Further, conventionally, in the initial setting process in the CPU and the interrupt process generated at the end of the DMA transfer, the setting of the DMA transfer destination address and the next DMA
In contrast to the case where two or three instructions have to be executed in accordance with the setting of the transfer destination address, respectively, a register for modifying the DMA transfer source address and, as seen in the second embodiment, Since only one instruction for setting a register for selecting a qualified bit of a transfer source address needs to be executed, there is an effect that the program capacity can be reduced.
Since the setting processing time of the PU is shortened, there is an effect that the original processing of the CPU can be efficiently executed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an information processing system to which the embodiment is applied.

FIG. 3 is a conceptual diagram illustrating a configuration of an address modification unit according to the first embodiment.

FIG. 4 is a conceptual diagram illustrating a configuration of an address modification unit according to a second embodiment.

FIG. 5 is a diagram illustrating a processing flow of a CPU according to the embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional embodiment.

FIG. 7 is a diagram showing a processing flow of a CPU in a conventional embodiment.

[Explanation of symbols]

 Reference Signs List 1 DMAC 2 DMA execution control unit 3 Decrementer 4, 5 TC 6 Address modification unit 7, 8 MASR 9 Data latch 10 Address update unit 11 Microcomputer 12 Memory 13 Peripheral device 14 CPU 15 DMA transfer source area A 16 DMA transfer destination area A 17 DMA transfer source area B 18 DMA transfer destination area B 19, 24 AMD 20 to 22, 31 to 34 OR gate 23 ASL 25, 26 Inverter 27 to 30 AND gate 31, 32 MDAR

Claims (5)

(57) [Claims] 1. A direct memory access (DM)
A) In a data transfer control device for controlling DMA data transfer between memories according to a method, a transfer number storage means for storing a value of the number of DMA data transfers with respect to a predetermined DMA transfer area, and each time a DMA data transfer is executed, A number-of-transfers updating means for updating the value of the number of executions stored in the number-of-transfers storage means, an address storage means for storing an address of a predetermined DMA transfer source area as address information, and a DMA data transfer. Address updating means for updating the value of the address information stored in the address storage means every time; address modification means for bit-modifying and outputting the address information stored in the address storage means ; wherein the DMA transfer destination address <br/> less information output is bit modified by address modification means DM, which is stored in the dress storage means
DMA has an address information switching means for outputting switching to chronologically alternating inputs an A transfer source address information
Performing data transfer, and the address modification means
An address modification register that stores a fixed number of modification bits
And the D stored in the address storage means.
The value of each bit of the address of the MA transfer source area and these
Output from the address modification register corresponding to each bit
And the values of the modifier bits to be
And a plurality of OR gates that output
Set logic level "1" to the address modification register
And the DMA transfer source address corresponding to the set value.
Set the bit to be modified to “0” and set the DMA transfer destination address.
A data transfer control device for automatically generating a dress . 2. The address modification means according to claim 1, wherein said first and second address modification registers each store a predetermined number of modification bits, and inverts and outputs a value of each bit of said first address modification register. A plurality of inverters; a plurality of first AND gate groups that output a logical product of inverted output values of the plurality of inverters and corresponding bit values of the second address modification register; And a plurality of second AND gate groups for outputting a logical product of the value of each bit of the address modification register and the value of the corresponding bit of the second address modification register; The value of each bit of the address of the DMA transfer source area and the output values of the plurality of first and second AND gate groups corresponding to these bits are input, respectively. Plural ORs that take logical OR and output
The data transfer control device according to claim 1, wherein the data transfer control device includes at least a gate. 3. A direct memory access (DM)
A) In a data transfer control device that controls DMA data transfer between memories according to a method, a first transfer count storage unit that stores a value of a DMA data transfer count for a predetermined DMA transfer area, and executes DMA data transfer. Transfer count updating means for updating the value of the number of executions stored in the first transfer count storage means every time, a DMA for a DMA transfer area next to the DMA transfer area
A second transfer number storage unit for storing a value of the number of transfer times, a first address storage unit for storing an address of a predetermined DMA transfer source area as address information, and each time the DMA data transfer is performed, Address updating means for updating the value of the address information stored in the first address storage means, second address storage means for storing, as address information, an address of a DMA transfer source area next to the DMA transfer source area, Address modification means for bit-modifying the address information stored in the first address storage means and outputting the same; DMA transfer destination address information which is bit-modified by the address modification means and output; and the first address Address information output by inputting the DMA transfer source address information stored in the storage means and alternately switching in time series And DMA address transfer, and the address modification means is stored in the first address storage means and an address modification register for storing a predetermined number of modification bits. DM
A plurality of OR gates for inputting the value of each bit of the address of the A transfer source area and the value of the qualifying bit output from the address qualifying register corresponding to each of these bits, and performing a logical sum on each of the OR gates And a logic level “1” is set in the address modification register,
A data transfer control device which automatically generates the DMA transfer destination address by setting "0" to a modification target bit of the DMA transfer source address corresponding to the set value. 4. The address modification means includes first and second address modification registers for storing a predetermined number of modification bits, and inverts and outputs the value of each bit of the first address modification register. A plurality of inverters; a plurality of first AND gate groups that output a logical product of inverted output values of the plurality of inverters and corresponding bit values of the second address modification register; A plurality of second AND gate groups for performing a logical AND operation on the value of each bit of the address modification register and the value of the corresponding bit of the second address modification register;
The value of each bit of the address of the DMA transfer source area stored in the address storage means and the output values of the plurality of first and second AND gate groups corresponding to these bits are inputted. And a plurality of OR gates each of which performs a logical sum operation and outputs a logical level "1" in the first address modification register, and the DMA transfer source address corresponding to the set value is modified. Bit is set to “0”, and the modification target bit is selected by the set value of the second address modification register,
4. The data transfer control device according to claim 3, wherein the MA transfer destination address is automatically generated. 5. A direct memory access (DM)
A) In a control method of a data transfer control device for controlling DMA data transfer between memories according to a method, a transfer count storing means for storing a value of a DMA data transfer count for a predetermined DMA transfer area, and executing the DMA data transfer. Transfer count updating means for updating the value of the execution count stored in the transfer count storage means,
Address storage means for storing an address of the predetermined DMA transfer source area as address information, and address update means for updating the value of the address information stored in the address storage means each time the DMA data transfer is performed Address modification means for bit-modifying and outputting the address information stored in the address storage means, and address information outputted by being bit-modified by the address modification means and stored in the address storage means Address information switching means for inputting the address information and alternately switching the time information in a time series and outputting the same.
A: When performing data transfer, and as the address modification means, an address modification register storing a predetermined number of modification bits, and a bit of each bit of the address of the DMA transfer source area stored in the address storage means. Value and
The DMA data transfer is performed by using a configuration comprising a plurality of OR gates which receive the value of the modification bit output from the address modification register in correspondence with each of these bits, and take a logical sum and output the result. As an initial setting, a first process in which the first address storage means is set with a start address of the area to be the DMA data transfer source, and the second address storage means has the following D
Second address in which the head address of the MA transfer source area is set
A third process in which a value obtained by setting a bit to be subjected to address modification to a logical level “1” is set in the address modification register; and the first transfer count storage unit stores the DMA transfer data count. A fourth process in which the number of transfer data in the area where the next DMA data transfer is performed is set in the second transfer count storage means;
A sixth state in which the CPU enables the DMA transfer;
When the occurrence of a DMA interrupt request is detected, the CPU activates a DMA end interrupt processing program routine, and stores the DMA in the second address storage means in preparation for the next DMA transfer. A seventh process in which a start address of a transfer source area is set, an eighth process in which a value in which a bit for modifying an address is set to "1" is set in the address modification register, and a second process in which the second transfer is performed. Ninth processing for setting the number of data to be transferred to the next DMA transfer area in the number-of-times storage means, and performing a ninth process.