JPH0424733B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control system for transferring command information based on input/output commands executed by a central processing unit of a computer system to a channel control device.

The peripheral devices of many computer systems are connected to the central processing unit and main storage of the main body of the computer system via a channel control device that controls one or more subchannels.

The channel control device receives control information constituted by input/output instructions executed by the central processing unit, and executes control such as data input/output of the subchannel specified by the control information.

[Conventional technology]

Figure 2 is a configuration diagram of an example of a computer system, in which two central processing units (hereinafter referred to as CPUs) 1, two channel control units (hereinafter referred to as CHP) 2, and a main storage device 3 control the system. It is connected to device 4.

The CHP 2 holds information necessary for controlling each subchannel, and this information is stored using, for example, a part of the storage area of the main storage device.

Such an area is called, for example, an I/O system area, and is fixedly allocated to the CHP 2 as a so-called hardware area that cannot be accessed directly from a program executed by the CPU 1.

The system control device 4 controls access to the main storage device 3 from the CPU 1 and CHP 2, and
Controls information exchange between each other, between CPU1 and CHP2, between CHP2, etc.

When a program executed by the CPU 1 requires data transfer or other control regarding peripheral devices, an input/output command is issued to send the required command information to the CHP 2.

There are various types of commands that belong to input/output commands, with the typical example being the start I/O (SIO and SIOF) command, which instructs the CHP2 to start the operation of peripheral devices. Conventionally, this has been performed as described below.

That is, for example, when issuing a SIOF command, the program prepares a command control word (hereinafter referred to as CCW) that specifies the operation of a peripheral device in the main memory 3, and stores its memory address in the main memory. After storing the command address word (hereinafter referred to as CAW) at a specific storage address, the SIOF command is issued.

In the CPU 1, when executing the SIOF instruction, as shown in the timing diagram of Fig. 4, the I/O request signal 1
0, and sends command information including the operation code of the command and the subchannel address (peripheral device address) specified by the operand to the system control device 4.

The system control device 4 selects the CHP and relays the input/output control information together with the control signal and the source CPU number to the CHP 2 at the timing shown as information 11.

CHP2 reads the CAW of a specific memory address determined by the CPU number and I/Os the CCW address etc.
It is stored in the system area and a series of other processes are executed during time 12. After that, the end signal 13 is returned together with the resulting condition code (hereinafter referred to as CC), so the system control device 4
, and relays it as information 14.

The CPU 1 sets CC in a predetermined register and completes the execution of the instruction.

[Problems to be Solved by the Invention] As is clear from the above explanation, the CPU 1 is occupied for the period from time 15 to time 16 in FIG. 4 to execute input/output instructions.

This period includes information transfer between devices, so there is a problem that it takes a relatively long time.
As the speed of 1.1 increases, this problem tends to become more widespread.

[Means for solving the problem] The above problem has a central processing unit, a channel control unit, and a main storage device, and the channel control unit has an input/output function executed by the central processing unit. Receive command information based on the command,
A specified process is executed for the subchannel specified by the command information, and the main storage device is connected to be accessed by the central processing unit and the channel control device, and the main storage device is connected to the central processing unit and the channel control device, and stores the information of the subchannel in a predetermined I/O system area. In a computer system that retains control information, the channel control device has one or more buffers, and the command information transferred from the central processing unit is stored in an empty buffer independently of the processing state within the channel control device. means for receiving data on a buffer, and means for notifying a central processing unit that all of the buffers are full, and the central processing unit refers to the notifying means when executing the input/output command. When it is determined that there is no space in the buffer, the execution of the instruction is stopped or placed in a waiting state, and when it is determined that there is space in the buffer, the I/O of the subchannel specified by the input/output instruction is executed. The state of the subchannel is identified from the control information held in the system area, and if the subchannel is in a state where it is impossible to execute the command, the central processing unit stops executing the input/output command, and the subchannel executes the command. If the state is executable, the central processing unit stores predetermined information for controlling the subchannel in the I/O system area, and then transfers the command information to the buffer of the channel control device; If the input/output command is an instruction in which the execution of input/output processing by the channel control device and the execution of the command by the central processing unit are performed asynchronously, the input/output command is executed upon completion of the transfer of the command information. This problem is solved by the input/output control method of the present invention, which is characterized by recognizing that the execution of the problem has been completed.

[Effect]

During the period of time 12 in Figure 4, which occupies most of the time when CPU 1 is held on hold for the execution of input/output instructions, the processing performed by CHP 2 generally differs depending on the type of input/output instruction, but can be roughly divided into There are two types.

The first type of instructions, like the SIOF instruction and others, are
At this point, the control information based on the command is CHP2
The execution may be performed asynchronously with the execution of instructions by the CPU 1.

The second type is a so-called synchronous type, such as an SIO instruction, in which information such as command transfer is exchanged with a peripheral device during a period of time 12, and the instruction is completed when the result is obtained. be.

Therefore, a buffer is provided in the CHP 2 for the purpose of holding the command information received from the CPU 1, and in the case of the first type of command, execution of the input/output command is completed when the command information is transferred to the buffer. In other words, even if CHP2 is executing other processing,
CPU1 can finish executing the input/output instruction.

In this case, for example, before transferring command information,
CPU1 refers to the information of the required subchannel in the I/O system area, determines whether the subchannel is in a state where the command can be executed, and if possible, CAW
The CCW storage address and other control information located in the subchannel are stored in the area of the subchannel.

CC based on the result and the command information transfer result.
can also be generated by the CPU 1 itself.

Note that the CPU 1 stores the above control information in the subchannel area by CHP as in the conventional technology.
If CPU 2 executes the process, CPU1
When CHP2 recognizes that the input/output command has been completed by transferring the specified command information and moves on to the next process, CHP2
This is to prevent this from happening, since there is a risk that the control information will be updated before the process.

Since these processes of the CPU 1 can be performed in parallel while the CHP 2 is executing other processes, the time of the CPU 1, which was essentially idle in the past, can be used efficiently.

As described above, when executing an input/output command such as a SIOF command, there is no need to wait even during channel control device processing as long as the buffer is free, and I/O Processing in the system area is performed by the central processing unit, and there is no need for the channel control unit to perform the processing after receiving the command, resulting in a reduction in command execution time and an improvement in the overall performance of the system.

〔Example〕

FIG. 1a is a detailed block diagram of the configuration of an embodiment of the present invention, and FIG. 1b is a timing diagram of input/output command execution in this embodiment.

When executing an input/output command, the CPU 1 looks at a buffer full signal sent from the CHP 2 as described later, and if it determines that there is space in the command information receiving buffer of the CHP 2, it proceeds with the process.

In that case, first, the I/O
Access the area of the subchannel in the O system area, check the status of the subchannel, and if the subchannel is not in a state where the command can be executed, for example, at this stage, set a predetermined CC and finish the command execution. Branch to processing.

If the command is executable, read the CAW at a fixed storage address and read its contents,
After performing preprocessing (50 in FIG. 1b) of writing the CCW storage address, storage protection key value, etc. to the I/O system area, the transfer of command information is started.

The CPU 1 loads the command information and request type onto the address bus 20 and sends it to the register 2 of the system control device 4.
1, 22 (51 in Figure 1b).

The request type in the register 22 is different from read/write to the main memory 3, I/O request, etc., and in this case, the I/O request is displayed.

The command information in the register 21 has, for example, the configuration shown in FIG.
The operation code of input/output commands such as
is placed when other control information is required.

Note that the numbers at the bottom of the figure are bit position numbers showing an example of the structure of command information. In this example, the command information is composed of 32 bits from bit positions 0 to 31.

In the system control device 4, the selection circuit 23 selects one of the requests occurring simultaneously according to a predetermined priority order, and receives the request information,
input to address pipeline 24;

The three types of command information mentioned above are stored in the address pipeline 24 along with the request type and source CPU number.
The information is input in the order in which it is received, and the information is used to shift registers that make up a so-called pipeline and is used for control according to each request type.

In the case of an I/O request, the request type is detected and the command information and the source CPU are sent to the channel selection circuit 25 at an appropriate stage in the pipeline.
The number will be copied.

The channel selection circuit 25 is configured by a part of the subchannel address part (61 in FIG. 3) of the command information.
The CHP2 is determined, and the command information is transferred to the register 26 of the CHP2, and the CPU number is transferred to the register 27 (52 in FIG. 1b).

The command information in the register 26 is stored in a buffer register 35-1 or 35- provided corresponding to each CPU.
2.

When the command information and the like are set in the buffer registers 26 and 27, the control section 29 immediately sets the CPU number in the register 30 of the system control device 4 and sets the reception confirmation signal in the latch 31.

In the system control device 4, the selection circuit 32 selects the CPU with the CPU number set in the register 30,
By setting the reception confirmation signal in the latch 33 for the CPU, the reception confirmation signal is transferred to the CPU (53 in FIG. 1b).

At the same time, the controller 29 of the CHP 2 also sets the buffer full signal latch 34-1 or 34-2 of the system controller 4.

This buffer full signal latch 34-1 or 3
4-2 is provided corresponding to each CHP to indicate that the buffer registers 35-1 and 35-2 for each CPU are in use, and the control unit 29 receives the buffer registers from the processing unit 28. Register 35-1 or 35
-2 is held until it is reset.

Buffer full signal latch 34-1, 34-2
The signal for each CPU transfers the buffer full signal to that CPU by setting latch 36 by ORing the signals for that CPU. Therefore, each
The CPU 1 detects the OFF state of the buffer full signal when all of the buffer registers 35-1 or 35-2 for its own CPU in all CHPs 2 are empty.

When the CPU 1 receives the reception confirmation signal transferred by the register 33, if the input/output instruction being executed is the above-mentioned asynchronous type, it immediately sets a CC with a predetermined content in a predetermined register and completes the execution of the instruction.

Therefore, in the execution of an asynchronous type input/output instruction, CHP1 and
A connection with the CHP 2 is required, and when the CPU 1 receives a buffer full signal from the system control device 4, it can start processing the next instruction.

If the input/output command being executed is the synchronous type described above, it receives a buffer full signal and waits for a processing end signal from the CHP2.

In addition, buffer register 35-1 in CHP2,
When 35-2 is in use, the buffer full signal is on, so if the subsequent instruction that CPU 1 attempts to execute is an input/output instruction as described above, the buffer full signal will not be executed until it detects that the buffer full signal is off. cannot be executed.

When processing becomes possible, the processing unit 28 of the CHP 2 reads the command information from the buffer register 35-1 or 35-2 and performs input/output control processing according to the conventional method. However, in this case,
CAW information has already been transferred to the I/O system area by CPU1, so
CHP2 never reads CAW.

In that case, the processing section 28 first notifies the control section 29 that the buffer register 35-1 or 35-2 that has been read out has become empty.
resets the appropriate buffer full signal latch 34-1 or 34-2.

If the operation determined by the operation code section (60 in Figure 3) of the command information is an asynchronous type, the instruction execution in the CPU 1 is completed as described above, and no further response to the instruction is required from the CHP 2. Not issued.

If the processing unit 28 determines that the operation is synchronous, when control based on command information (for example, peripheral device startup control in the case of an SIO command) is completed, a CC indicating the result of the control is sent. It is created and transferred to the register 37 of the system control device 4. At the same time, the source CPU number of the input/output command is transferred to the register 30, and the processing end signal is transferred to the latch 38 (57 in FIG. 1b).

The CC and processing end signals pass through the selection circuit 32, are set in the register 39 and latch 40 for the target CPU, and are transferred to the CPU 1 (5 in Figure 1b).
5).

The CPU 1 receives them and sets CC in a predetermined register, thereby completing execution of the synchronous input/output instruction. Therefore, in the case of synchronous input/output instructions, the CPU and
CHP is combined.

In the above explanation, it is assumed that each CHP has one buffer register 35-1, 35-2 for each CPU, but it is assumed that two or more buffer registers are provided for each CPU, or for multiple CPUs. A plurality of buffer register pools may be provided in common, and these can be easily configured as a modification of this embodiment.

〔Effect of the invention〕

As is clear from the above description, the present invention has a significant industrial effect of reducing the CPU hold time due to the execution of input/output instructions and improving the processing capacity of the computer system.

[Brief explanation of drawings]

FIG. 1a is a block diagram of an embodiment of the present invention;
FIG. 1b is a timing diagram of one embodiment of the present invention;
3 is a configuration diagram of a computer system, FIG. 3 is a configuration diagram of command information, and FIG. 4 is a conventional input/output command execution timing diagram. In the figure, 1 is the central processing unit (CPU), 2 is the channel control unit (CHP), 3 is the main memory, and 4
21, 22, 26, 27 are registers, 23 is a selection circuit, 24 is an address pipeline, 25 is a channel selection circuit, 28 is a processing section, 29 is a control section, 32 is a selection circuit, 34-1 ，
34-2 is a buffer full signal latch, 35-
1, 35-2 indicates a buffer register.

Claims (1)

[Claims] 1. A central processing unit, a channel control device, and a main storage device, the channel control device receiving command information based on input/output commands executed by the central processing unit. ,
A specified process is executed for the subchannel specified by the command information, and the main storage device is connected to be accessed by the central processing unit and the channel control device, and the main storage device is connected to the central processing unit and the channel control device, and stores the information of the subchannel in a predetermined I/O system area. In a computer system that retains control information, the channel control device has one or more buffers, and the command information transferred from the central processing unit is stored in an empty buffer independently of the processing state within the channel control device. means for receiving data on a buffer, and means for notifying a central processing unit that all of the buffers are full, and the central processing unit refers to the notifying means when executing the input/output command. When it is determined that there is no space in the buffer, the execution of the instruction is stopped or placed in a waiting state, and when it is determined that there is space in the buffer, the I/O of the subchannel specified by the input/output instruction is executed. The state of the subchannel is identified from the control information held in the system area, and if the subchannel is in a state where it is impossible to execute the command, the central processing unit stops executing the input/output command, and the subchannel executes the command. If the state is executable, the central processing unit stores predetermined information for controlling the subchannel in the I/O system area, and then transfers the command information to the buffer of the channel control device; If the input/output command is an instruction in which the execution of input/output processing by the channel control device and the execution of the command by the central processing unit are performed asynchronously, the input/output command is executed upon completion of the transfer of the command information. An input/output command control method characterized by recognizing that execution of the input/output command has been completed.