JPS6215903B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus control system, and more particularly to a bus control system that can eliminate hang-ups and collisions of transferred data between two sets of systems.

Many small computer systems use a single bus system in which the input/output interface circuit, like the processor and memory, is connected to a bus, and the memory can be directly accessed from the input/output interface circuit in the same way as the processor. in this case,
A method for controlling data transfer between a processor and an input/output interface circuit by a program;
DMA control unit (Direct Memory Access
There is a method of controlling high-speed data transfer between a memory and a high-speed input/output interface circuit using a high-speed input/output interface circuit (controller). For high-speed data transfer, for example, when display data of a display device is read from memory and transferred for refreshing,
This will be given priority.

FIG. 1 is a block diagram of two sets of bus-coupled control schemes.

In the B system 2 in which the B processor 9, the B memory 12, and the B adapter 11 group are connected to one bus 4, the transfer between the adapter 11 and the memory 12 is performed under the control of the DMA control unit 10. Data transfer between the processor 9 and the memory 12, or between the processor 9 and the adapter group 11, and between the adapter group 11 and the memory 12 are performed on the bus 4 without collision. In addition, adapter group 11
is connected to various input/output devices as an input/output interface circuit.

Further, the A system 1 connected to the bus 4 of the B system 2 by the bus control unit 8 functions as an adapter for the B system 2. The processor 5 of the A system 1 can access the B memory 12 in the B system 2 via the DMA controller 10, while the processor 9 of the B system 2 can access the B memory 12 of the A system 1 via the bus controller 8. The memory 6 or the adapter group 7 can be accessed.

FIG. 2 is a detailed block diagram of the conventional bus control section shown in FIG.

The bus control unit 8 in FIG. 2 includes a bus time division control unit 50, a DMA sequence control unit 51, and an address
Buffer 23, 24, 26 and data buffer 2
2 and 25 are provided. Bus time division control unit 5
0, when there is a request from the B processor 9 and the A processor 5 to transfer data to the A memory 6 or the A adapter group 7 using the A address bus 27 and the A data bus 28, these processors This is to accept and execute it in a time-sharing manner.
Further, when there is a data transfer request from the A processor 5 to the B memory 12, the DMA sequence control unit 51 issues a B bus use request signal 17 to the DMA control unit 10 of the B system 2, and the DMA control unit 10
Data transfer between the A processor 5 and the B memory 12 is executed by allowing the B bus to be used.

Therefore, A processor 5, A memory 6, A
Adapter group 7, B memory 12 or B adapter 1
Data transfer between group 1 and B processor 9
When controlling the bus so that data transfer can be performed between the A memory 6, the A adapter group 7, the B memory 12, or the B adapter group 11, the bus time division control unit 50 controls the A processor 5 and the B processor 9. Even if two processors issue requests to use the A bus at the same time, when one processor's request to use the A bus is sampled, that processor's instruction execution ends. Bus control is performed so that both processors can execute instructions without the data of both processors colliding on the buses 27 and 28 by not sampling the other processor's A bus use request until the bus 27, 28.

Further, the DMA sequence control unit 51 is configured such that the A bus use request from the A processor 5 is sampled by the time division control unit 50 to enable the instruction execution of the A processor 5, and the B memory access request signal 13 from the A processor 5 is sampled by the time division control unit 50. is issued,
B bus use request signal 1 to the DMA control unit 10
Issue 7. At this time, data from the A processor 5 is loaded onto the A data bus 28 via the data buffer 22. Thereafter, the DMA control section 10 issues the B bus use permission signal 18, thereby enabling the address buffer 26 and the data buffer 25, and when the B memory 12 is accessed, the DMA sequence control section 51 is the bus time division control unit 50 that has B memory
The B memory access signal 52 is sent to notify that the access has been completed. Bus time division control unit 5
0 learns that the instruction of A processor 5 has been executed and begins sampling the next A bus usage request.

However, in such a system configuration, DMA
A B bus use request from the sequence control unit 51,
When requests to use the A bus from the B processor 9 occur simultaneously, the DMA control unit 10
is in the middle of executing an instruction, and in order to prevent data collision on the B buses 29 and 30, the B bus use permission signal 18 is not returned to the DMA sequence control unit 51. Further, the bus time division control unit 50 also does not accept a request to use the A bus from the B processor 9 because the A processor 5 is in the middle of executing an instruction. Therefore, there is a possibility that both processors 5 and 9 may hang up as they are.

Therefore, in order to improve this situation, conventionally, when the A processor 5 attempts to access the B memory 12, it notifies the DMA control unit 10 and the B processor 9 of the request, and the A processor 5 receives permission from both. The B memory 12 is accessed from. However, such a control system has the problem that data transfer from both processors to the adapter groups 7 and 11 and memory access programming become difficult, and data transfer efficiency decreases.

Furthermore, if the DMA sequence control section 51 in FIG. 2 is separated from the bus time division control section 50 and an attempt is made to access the B memory 12 regardless of the operations of both processors, the DMA control section adapted to the bus interface of the B system 10, B memory 1
2, a register for setting the data to be transferred and the address of that data, and a DMA sequence control adapter equipped with a data buffer, address buffer, etc., which increases the number of ICs. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and to enable two processors in a bus-coupled system to connect memory and adapter groups connected to other buses without being aware of the operating status of the other processor. We developed a bus control method that allows the command to be executed without causing a system hang-up due to contention between data transfer requests of two processors, or data collision on the bus, even when a data transfer command is issued to the processor. It is about providing.

The bus control method according to the present invention is applicable to a multi-processor system consisting of a first system that transfers data between a memory and an adapter using DMA control, and a second system that is an adapter for the first system. A bus control circuit that executes data transfer to the system memory and adapter group in a time-sharing manner, and in the case of simultaneous requests, executes the data transfer of the first processor preferentially without using time-sharing control. Provide the first system DMA
This system is characterized in that the second processor accesses the memory of the first system only after receiving permission to use the bus from the control unit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing the bus control method of the present invention.

As in the past, the B system has a B processor 9, a B adapter group 11, and a B memory 12 on the B address bus 30 and the B data bus 29.
are combined, and the A processor 5 of the A system,
The A memory 6 and the A adapter group 7 are connected to the B address bus 30 and the B data bus 2 via the bus control unit 8'.
It is connected to 9.

Further, an A memory 6 and an A adapter group 7 are coupled on an A address bus 27 and an A data bus 28, and an A processor 5 is connected via a bus controller 8'.
are combined.

The bus control section 8' in FIG. 3 includes the data line of the A processor 5 and the A
Data buffer 22 for connecting the data bus 28, Address buffer 2 for connecting the address line of the A processor 5 and the A address bus 27
3. A processor 5 address line and B address line.
address buffer 26 for connecting bus 30;
An address buffer 24 for connecting B address bus 30 and A address bus 27, and a data buffer 25 for connecting B data bus 29 and A data bus 28 are provided.

In addition, in FIG. 3, the bus time division use control unit 50
A bus control circuit 21 is provided in place of the DMA control section 51 and the DMA sequence control section 51, and this bus control circuit 21 controls all signal exchange between the DMA control section 10 of the B system and the A system. The data buffer 25 and address buffer 24 are maintained in a three-state state and an active state under the control of the bus control circuit 21 to prevent data collisions on the bus.

Next, the bus control circuit 21, the A processor 5, the B processor
The processor 9, DMA control unit 10, and interface signals will be explained.

First, the signals inputted to the bus control circuit 21 from the A processor 5 or the B processor 9 are an A processor A bus use request signal (hereinafter referred to as the AMREQ signal) 13 and an A processor B memory access request signal (hereinafter referred to as the AMREQ signal). ACS signal) 19 and B
Processor A bus use request signal (hereinafter referred to as BMREQ signal) 15, while bus control circuit 21
The signals outputted from the processor are an A processor A bus use permission signal (hereinafter referred to as the AENBL signal) 14 and a B processor A bus use permission signal (hereinafter referred to as the BENBL signal) 16.

Second, the DMA control unit 10 from the bus control unit 21
For the B bus use request signal (hereinafter
A B bus use permission signal (hereinafter referred to as a BUSENBL signal) 18 is input from the DMA control section 10 to the bus control section 21.

FIG. 4 is a detailed configuration diagram of the bus control circuit of FIG. 3.

The operation of the bus control section 8' can be considered in the following five cases.

First of all, the A processor 5 and the B processor 9
This also applies to the case where a data transfer request to the A memory 6 and the A adapter group 7 is not issued to the bus control unit 8'. At this time, AMREQ signal 1 in Figure 4
3, BMREQ signal 15 and ACS signal 19,
Since both are logic "0", the BENBL signal 16 which is the output of the flip-flop circuit 32 and the AENBL signal 1 which is the output of the AND circuit 37
4 becomes "0".

Further, since the ACS signal 19 is "0", the BUSREQ signal 17 which is the output of the AND circuit 39 becomes "0", and the DMA control unit 10 sends the BUSENBL
Since the signal 18 is never returned, the data buffer enable signal (hereinafter referred to as BDEN signal) 20, which is the output of the NOR circuit 40, also becomes "0".

Therefore, as shown in FIG. 3, address buffers 23, 24, 26 and data buffers 22, 25 controlled by AENBL signal 14, BENBL signal 16, and BDEN signal 20 are all 3-
The A address bus 27 and the A data bus 28 are not loaded with data.

Second, the A processor 5 fetches programs stored in the A memory 6, exchanges operational information with the A adapter group 7, and exchanges data with other systems sent and received by the adapter group 7. This is a case where a data transfer request is issued to the bus control unit 8' in order to perform the following.

In this case, in FIG. 4, the AMREQ signal 13 becomes "1", and the BMREQ signal 15 and ACS signal 19 remain "0". BMREQ signal 15
is “0”, the flip-flop circuit 32
The BENBL signal 16 which is the output of is "0".

Since the AMREQ signal 13 is input to the flip-flop circuit 34, the reset state is released and the D
The input signal becomes "1" and the output signal 42 becomes "1".

Also, since the ACS signal is "0", the output of the NAND circuit 36 is "1" and the flip-flop 3
4 is input to the AND circuit 37, and the output signal AENBL signal 14 is set to "1".

Further, since the BUSENBL signal 18 is also "0", the BDEN signal 20, which is the output of the OR circuit 40, is also "0".

Therefore, the address buffer 23 and data buffer 22 in FIG.
4 and controlled by the BDEN signal 20 and the BENBL signal 16.
4, 26 and the data buffer 25 are in a 3-state state, the address of the A processor 5 is transferred on the A address bus 27, and the data line is transferred through the data buffer 22 to the A data bus 2.
8, thereby A processor 5 and A
Data transfer with the memory 6 or the A adapter group 7 becomes possible.

Third, the B processor 9 reads the operation status information of the A system 1 stored in the A memory 6, writes operation instruction information to the A system 1,
In order to initialize the A adapter group 7, etc.
This is a case where a data transfer request is issued to the bus control unit 8'.

In this case, the BMREQ signal 1 in FIG.
5 becomes "1", and the AMREQ signal 13 and ACS signal 19 remain "0".

If the AMREQ signal 13 is "0", the flip-flop circuit 34 has been reset, so the output signal 42 is "0". Therefore,
Since the AENBL signal 14, which is the output of the AND circuit 37, is "0" and the BMREQ signal 15 is "1", the output of the AND circuit 31 is "1". As a result, the reset of the flip-flop circuit 32 is released and the D input signal becomes "1", so that the output BENBL signal 16 becomes "1".

Also, the BDEN signal 2 which is the output of the OR circuit 40
0 also becomes "1".

Therefore, in FIG. 3, BENBL signal 1
6 causes address buffer 24 and BDEN
The data buffers 25 are each activated by the signal 20.

At this time, the address buffer 23 controlled by the BUSENBL signal 18 and the AENBL signal 14,
26, and data buffer 22 remain in the 3-state condition. As a result, the address of the B processor 9 is transferred via the A address bus 27, the B data bus 29 and the A data bus 28 are coupled through the data buffer 25, and the address of the B processor 9 and the A adapter group 7 or A memory 6
It becomes possible to transfer data between

The fourth case is a conflicting state between the second and third cases. For example, the A processor 5's program fetch and the B processor 9's reading of the operating status of the A system 1 occur simultaneously, and both This is a case where a data transfer request to the A memory 6 is issued to the bus control unit 8'.

At this time, in FIG. 4, the AMREQ signal 13
and BMREQ signal 15 both become “1”, and ACS
Signal 19 remains at "0". As a result, both flip-flop circuits 32 and 34 are released from reset, and the D input signal becomes "1".

However, since the flip-flop circuits 32 and 34 are inputted with a clock 41 for sampling the AMREQ signal 13 and BMREQ signal 15 in a time-division manner with opposite phases, if the BMREQ signal 15 is sampled first, When the BENBL signal 16 becomes "1", the D input of the flip-flop circuit 34 becomes "0", the output signal 42 remains "0", and the AENBL signal 14 also remains "0". As a result, the output of the NAND circuit 31 also
The BMREQ signal remains at "1" until it becomes "0", and the BENBL signal 16, which is the output of the flip-flop circuit 32, also remains at "1". At this time, the BDEN signal 20 becomes "1", so as explained in the third case, the B processor 9 and the A
Data transfer between the memory 6 and the A adapter group 7 becomes possible.

Thereafter, when the data transfer of the B processor 9 is completed and the BMREQ signal 15 becomes "0", the flip-flop circuit 32 is reset.
The BENBL signal 16 becomes "0". This results in
The D input signal of the flip-flop circuit 34 becomes "1", and since the AMREQ signal 13 remains "1", the output signal 42 becomes "1", and at the same time, since the ACS signal is "0", the AND The AENBL signal 14, which is the output of the circuit 37, becomes "1".

Since the AENBL signal 14 is "1", the output of the AND circuit 31 remains "0", the flip-flop circuit 32 remains reset, and the BENBL signal 16 never becomes "1". . Since the ACS signal is "0", the BUSREQ signal 17 becomes "0", the BUSENBL signal 18 also becomes "0", and the BDEN signal 20 continues to be "0". This results in, as explained in the second case,
Data transfer between the A processor 5 and the A memory 6 or the A adapter group 7 becomes possible.

Next, in the fifth case, for example, in order for the A processor 5 to process data transmitted and received by the A adapter group 7, it becomes necessary to perform data transfer with the B memory 12, and therefore the bus controller 8' This is a case where a request to access the B memory 12 is issued. At the same time, since the B processor 9 reads the operational status of the A system 1,
When attempting to access memory 6, bus control unit 8'
It will also be explained that both processors can normally execute the above operations even when a data transfer request is issued.

In this case, both the AMREQ signal 13 and the ACS signal 19 become "1" in FIG.

If the BMREQ signal 16 is "0", the output signal 42 of the flip-flop circuit 34 is "1", and since the ACS signal 19 is "1", the BUSREQ signal 17, which is the output of the AND circuit 39, is "1". ”, and the bus control unit 8' issues a request to the DMA control unit 10 to use the B address bus 30 and the B data bus 29.

However, it is a use permission signal for the B address bus 30 and B data bus 29 of the DMA control unit 10.
The AENBL signal 14, which is the output of the AND circuit 37, remains at "0" until the BUSENBL signal 18 becomes "1".

Therefore, if the B processor 9 issues a data transfer request to the A memory 6 and the A adapter group 7 at this time, the bus control unit 8' accepts it, so the B processor 9 can As explained above, by setting the BMREQ signal 15 to "1", the flip-flop circuit 32 is set to the BENBL signal 16 to "1", and the BDEN signal 20 is set to "1" to initiate data transfer. can be executed.

In response, the DMA control unit 10
When the signal 18 is set to "1", in FIG.
If the data transfer of the B processor 9 is completed and the BENBL signal 16 becomes "0", the AENBL signal 1
4 becomes "1", and thereby the BDEN signal 20 also becomes "1". Therefore, address buffers 23, 26 and data buffers 22, 25 in FIG. 3 are activated. At this time, BENBL
Address buffer 24 controlled by signal 16
is in three states. The address of A processor 5 is transferred to B address bus 30 through address buffer 26, and the data lines are coupled to B data bus 29 through data buffers 22, 25, so that A processor 5 is transferred to B memory 12. becomes possible to access.

In the embodiment, the bus control section 8' is
Although the bus control section 8' is provided in the system 1, there is no problem in providing the bus control section 8' in the B system 2.

As explained above, according to the present invention, there is provided a means for time-sharingly executing data transfer from two sets of processors to a second memory and an adapter group, and a means for simultaneously executing data transfer from two sets of processors to a second memory and an adapter group. A bus control circuit is provided which includes a means for causing a data transfer of a first processor to be executed first when a data transfer request is issued, and then executing a data transfer of a second processor after receiving permission from a DMA control unit. Therefore, even if two processors execute instructions without being aware of the operating state of the other processor, the system will not hang up due to conflicting data transfer requests between the two processors, and and data without colliding on the address and data buses of the two systems.
It can be transferred smoothly.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a two-set bus coupling control system, Fig. 2 is a detailed block diagram of the conventional bus control section in Fig. 1, and Fig. 3 is a block diagram of a bus control system showing an embodiment of the present invention. , FIG. 4 is a detailed configuration diagram of the bus control circuit in FIG. 3. 1...A system, 2...B system, 3...A bus, 4...B bus, 5...A processor, 6...A memory, 7...A adapter group, 8, 8'... bus control unit,
9...B processor, 10...DMA control unit, 11...
B adapter group, 12...B memory, 13...A processor A bus use request signal, 14...A processor A
Bus use permission signal, 15...B processor A bus use request signal, 16...B processor A bus use permission signal, 17...B bus use request signal, 18...B bus use permission signal, 19...A processor B memory use request signal , 20...Data buffer enable signal, 21...Bus control circuit, 22...Data buffer, 23...Address buffer, 24...Address buffer, 25...Data buffer, 26...
Address bus, 27...A address bus,
28...A data bus, 29...B data bus,
30...B address bus, 31...AND circuit, 3
2... Flip-flop circuit, 33... Inverter circuit, 34... Flip-flop circuit, 35... AND circuit, 36... NAND circuit, 37... NAND circuit, 38... Inverter circuit, 39... AND circuit,
40...NOR circuit, 41...Bus use request sampling clock signal, 42...Flip-flop output signal.

Claims (1)

[Claims] 1 a first system that performs data transfer between the memory and the adapter under the control of a DMA control unit;
In a multi-processor system consisting of a second system which is an adapter for the second system, means for time-sharingly executing data transfer from the processors of both systems to the second system's memory and adapter group; When a data transfer request is issued to the memory and adapter group of the first system, the data transfer of the processor of the first system is executed first, and then the
A bus control system comprising: a bus control unit including means for executing data transfer by a processor of a second system after receiving permission from a DMA control unit.