JPS6127790B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device.
Conventional data processing devices, especially central processing units (hereinafter referred to as CPUs), input/output devices (hereinafter referred to as I/O ports), and memories, have a large number of connections between these devices (for example, between CPUs, between CPUs and /O between ports,
Data transfer between devices (or between CPU and memory, etc.) is performed while each device communicates with each other. A so-called handshake method is used.
A conventional data transfer method using handshake between these data processing devices will be described below with reference to the drawings.

FIG. 1 shows a system configuration block diagram of each data processing device.

As shown in FIG. 1, a system configured with conventional data processing devices includes a first CPU, a second CPU 3, each having a dedicated memory 2 and 4, a shared memory 5, an I/O port 6, 7 and one common bus 8, data information of each device is output to the one common bus 8, and this common bus 8,
It is configured to transfer data between each device.

Here, the common bus 8 is a bus having an address bus, a data bus, a control bus, etc., and data transfer between conventional data processing devices using the common bus 8 is shown in FIGS. 2 and 3. This will be explained with reference to the data transfer timing diagram shown in FIG. Here, FIG. 2 shows a timing diagram when data is transferred from the first CPU 1 to the input/output port 6, and FIG. 3 is a timing diagram when data is transferred from the input/output port 6 to the first CPU 1. .

First, in Figure 2, the first
When transferring data from the CPU 1 to the input/output port 6, the first CPU 1 outputs a data signal, a control signal, and a device address signal A indicating the data destination to the common bus 8.
After the time, synchronization signal (SYN signal) B is output to input/output port 6. When the input/output port 6 selected by the device address signal receives this synchronization signal B, it inputs data from the common bus 8. Thereafter, a synchronization signal C is output to the first CPU 1 to notify the first CPU 1 that data has been received. When the first CPU 1 receives the synchronization signal C from the input/output port 6, it turns off the data, address, control signal A, and synchronization signal B. On the other hand, when the synchronization signal B from the first CPU 1 is cut off, the input/output port 6 cuts off the synchronization signal C output from the input/output port 6, and the data transfer ends.

Conversely, when transferring data from the input/output port 6 to the first CPU 1, the first
The CPU 1 outputs the device address signal and the control signal D to the common bus 8 to the data processing device that has the data it wants to receive (in this case, the input/output port 6), and inputs the synchronization signal E after the setup time. Output to output port 6. On the other hand, the input/output port 6 selected by the device address signal
outputs the data signal G to be sent to the first CPU 1 to the common bus 8, and in order to notify the first CPU 1 that the data has been output to the common bus 8, it outputs the synchronization signal F to the first CPU 1 after the setup time. Send to CPU1. When the first CPU 1 receives this basic signal F, it inputs the data from the common bus 8, and sends a synchronization signal E and an address control signal D to notify the input/output port 6 that it has received the data. Cut. Input/output port 6 sees that the synchronization signal E from CPU 1 is cut off, and connects it to the first CPU.
The synchronization signal F to 1 is cut off, and the data transfer ends.

The data transfer method described above is called a so-called handshake method, in which devices communicate with each other, and this is intended to ensure data transfer and improve reliability.

However, on the other hand, when this method is used for data transfer between conventional data processing devices, the next process cannot be performed until the data transfer is completed, so the time spent on one process increases, and during that time, each Data processing devices, particularly CPUs, have had the disadvantage that the execution time of input/output commands increases due to data transfer, resulting in poor processing efficiency. In particular, if the common bus 8 is long and the response speed of the input/output ports is slow, the input/output instructions of the CPU will be long, and the processing efficiency will be significantly reduced.

An object of the present invention is to eliminate such drawbacks and provide a data processing device that is highly reliable and has good processing efficiency.

The present invention includes a processing mechanism having a predetermined processing ability;
In order to transfer data to this processing mechanism, it is composed of a data processing device having a data transfer mechanism that temporarily holds data, and after the processing mechanism transfers its output to the data transfer mechanism, the next data processing is executed. It is characterized by what it can do.

According to the present invention, a data processing device that is to perform data transfer outputs data and data transfer information to a data transfer device provided in the data processing device. A data transfer can occur at the device and other instructions can be executed during the data transfer. For this reason, the processing efficiency of the data processing device during the period conventionally spent on data transfer is significantly increased, and reliability is not reduced by using the handshake method for data transfer in the data transfer device.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 4 shows an embodiment in which the data processing device according to the present invention is applied to a microcomputer.

The data processing device of this embodiment includes a general-purpose register section 9 that can be used as a stack pointer, a program counter, and an index register, an accumulator 12, an arithmetic logic unit (ALU) 10,
An arithmetic unit 30 having a temporary register 11 for temporarily storing data, an instruction register unit 14, a decoder unit 13, an address buffer unit 15, a data buffer unit 16, a timing control unit 17, an interrupt control unit 18, A CPU unit 31 has an internal data bus a that transmits data from each of these units, and when this CPU unit 31 transfers data, other data processing devices (for example, I/O ports, shared memory, other CPUs, etc.) ) address register 21 that outputs the device address signal of
and an address buffer 23 connected thereto, and
A data buffer 20 to which the CPU unit 31 transfers data, a transmit register 24 used to gate the data and used when transmitting the data of the CPU unit 31 connected to this to another data processing device, and a data buffer 26 connected to this. Furthermore, a receive register 25 connected between the data buffers 20 and 26 and used when the CPU section 31 receives data from another data processing device and gates the data, and an interrupt control section 18 of each of these sections and the CPU section 31. A data transfer control section 27 is connected to the CPU section 31 by an interrupt request signal i, and controls each section. A transmit control unit 28 and a CPU unit 31 are connected to the read/write control unit 22 and the data transfer control unit 27 and are used when the CPU unit 31 sends data to other data processing devices. The CPU section 31 and the data transfer device 32 are connected to a local control signal line b, a local data bus c, and a local address bus d. Mutual data transfer is possible by connecting the address buffer 15 of the CPU section 31 and the address register 21 of the data transfer device 32 via the I'm used to it. Further, the address buffer 23, data buffer 26, transmit control section 28, and receive control section 29 of the data transfer device 32 are connected to each other data processing device, and a single line consisting of a control bus e, a data bus f, and an address bus g is connected. It is connected to the common bus 33 of. Here, a box 19 connected to the local data bus c and the local address bus d indicates a dedicated memory provided in the CPU section 31.

According to the data processing device having the CPU section 31 and the data transfer device 32 of this embodiment, for example, the handshake method is used to transfer data from the CPU section 31 to other I/Os.
When transferring O port, shared memory, or CPU data, the CPU section 31 first transfers the device address signal of the data destination from the address buffer 15 to the address register 21 of the data transfer device 32 via the local address bus d. output,
The desired data is transferred to the data buffer 1 of the CPU section 31.
6 to the data buffer 20 of the data transfer device 32 via the local data bus C, and from the timing control of the CPU section 31 to the read/write control section 22 of the data transfer device 32 via the local control signal line b. Output. The CPU section 31, which has output the data transfer information to the data transfer device, starts executing the next instruction. On the other hand, the data transfer device 32 that has received the data transfer information from the CPU section 31 sends a control signal from the read/write control section 22 to the data transfer control section 27, and the data transfer control section 27 that has received the control signal
sends a control signal to the transmit control section 28 used when transmitting data. At this time, data buffer 20 sends a data signal to data buffer 26 via transmit register 24, while address register 21 sends an address signal to address buffer 23. The address buffer 23, data buffer 26, and transmit control unit 28 that have received these signals output the respective signals to the address bus g, data bus f, and control bus 6 of the common bus 33, and perform the conventional handshake method. data transfer with other data processing devices or data transfer devices attached thereto. Next, when the data transfer is completed in the data transfer device, the data transfer end signal is sent to the transmit control unit 2.
8 to the data transfer control unit 27, and the data transfer control unit 27 receives the notification.
is sent to the timing control section 1 of the CPU section 31 through the read/write control section 22.
7 and waits for the next data transfer command.

On the other hand, conversely, from another data processing device to the CPU section 3
1 receives data, data signals from other data processing devices that have entered through the common bus 33 are stored in the receive register 25 that is input to the data buffer 26 of the data transfer device 32 via the data bus f. The control signal is input to the receive control section 29 via the control bus e. The receive control unit 29 that received the control signal outputs a control signal to the data transfer control unit 27, and the data transfer control unit 27 that received this outputs an interrupt request signal line to notify the CPU unit 31 that the data has been received. CPU section 31 through i
An interrupt request signal is output to the interrupt control unit 18 of.

Here, the interrupt control section 18 outputs a signal indicating whether or not the CPU section 31 may input data from the data transfer device to the data transfer control section 27 via the timing control section 17 in the form of a ready signal h. When the CPU section 31 is in a data input permission state, the data stored in the receive register 25 is transferred via the data buffer 20.
is input to the data buffer 16 of the CPU section 31,
In the data input permission state, data is stored in the receive register 25 until a permission signal is input to the data transfer control section 27 through the ready signal line h.

Furthermore, when the CPU section 31 transfers data to another data processing device, if the transfer of the previously transferred data has not been completed, that is, the address register 2
1 When the previous data is stored in the transmit register 24, a data transfer disabling signal is output from the read/write control section 22 to the timing control section 17 through the ready signal line h, and at this time, the data transfer is disabled. The CPU section 31 is in a waiting state (a state in which other instructions cannot be executed) until the device 32 issues a data transfer permission signal.

In order to make clearer the advantages of the processing procedure performed by the data processing device having the CPU section 31 and the data transfer device 32 in this embodiment, we will explain the conventional CPU
A comparison will be made with reference to FIG. 5, in comparison with a processing procedure of a data processing apparatus having only the following.

FIG. 5a shows a data transfer and a CPU processing procedure in a conventional data processing device (CPU), and FIG. 5b shows a data transfer and a CPU processing procedure in this embodiment.

However, FIGS. 5a and 5b are examples of data transfer from the CPU to another data processing device.

Here, ○A indicates the data transfer period, ○B indicates the CPU processing period, HIJK is the CPU instruction processing period, and H′.I′.J′ is the data transfer period of HIJ processed by the CPU. Yes, and XYX′.Y′.Z′ indicates the period during which the CPU issues a data transfer command.

As is clear from FIG. 5a, in the conventional data transfer method using the handshake method, when the CPU executes one instruction in period H, the data is transferred in period H' after data transfer instruction period X, and then The next instruction is executed in period I, and after the data transfer instruction period Y, data is transferred in period I', and the next instruction is executed in period J after waiting for its completion.

However, looking at FIG. 5b, in this embodiment, the CPU executes one instruction in period H,
The data is sent to the data transfer device, and after the data transfer command period X', the data is transferred from the data transfer device to another data processing device in the period H'.
During H', the CPU can execute the next instruction I. When the execution of the instruction is completed, the data is similarly sent to the data transfer device and the data is transferred in the period I' after the data transfer instruction period Y', while the next instruction J is executed. Here, when the execution of instruction J is finished, if the data transfer I' of the previous instruction I is not finished,
The CPU enters the waiting state until the data transfer I′ is completed, and after the data transfer I′ is completed, the CPU waits for the data transfer command period.
After Z', data transfer J' of instruction J is performed and the next instruction K is executed.

In this way, in this embodiment, the following instructions can be executed while data is being transferred, and therefore
The processing efficiency of the CPU can be improved without reducing the reliability of data transfer.

Furthermore, the data transfer device in the data processing device of the present invention can be provided in each part of the data processing device as necessary. For example, in data transfer,
It is also possible to transfer data between a data transfer device attached to the CPU section and a data transfer device attached to an input/output port, or by adding a data transfer device to the CPU and attaching this data transfer device to the I/O port. Data transfer device and I/O added to these CPUs without adding
Data can also be transferred directly between ports.

In addition, those skilled in the art may freely incorporate the data transfer device into a semiconductor chip such as a CPU, an I/O port, or a shared memory, or attach it externally to the semiconductor chip as necessary. It is something that can be done.

Furthermore, the local control signal line b, roll data bus c, and roll address bus d used in this example are not necessary in a simple circuit with only one CPU, and can be directly connected without going through these buses. The CPU section and the data transfer device may be connected.

[Brief explanation of the drawing]

Figure 1 is a system configuration diagram using a conventional data processing device, Figure 2 is a timing diagram for transferring data from a conventional CPU to an I/O port, and Figure 3 is a diagram of a system using a conventional data processing device.
Timing diagrams for transferring data from the I/O port to the CPU are shown. FIG. 4 shows a configuration diagram of a data processing device according to an embodiment of the present invention in which the present invention is applied to a data processing device having a CPU, and FIG. 5a shows the timing of data transfer time and instruction execution time of a conventional CPU. FIG. 5b shows a timing chart of data transfer time and instruction execution time of the CPU in the embodiment. 1... First CPU, 2... Dedicated memory for the first CPU, 3... Second CPU, 4... Dedicated memory for the second CPU, 5... Shared memory, 6, 7... Input/output ports,
8... Common bus, 9... General purpose register, 10... Arithmetic processing unit (ALU), 11... Temporary register, 12... Accumulator, 13... Decoder section,
14... Instruction register section, 15... Address buffer section, 16... Data buffer section, 1
7... Timing control unit, 18... Interrupt control unit, 19... CPU dedicated memory unit, 20, 26...
Data buffer section, 21...address register section,
22...Read/write control section, 23...
Address buffer section, 24... Transmit register section, 25... Receive register section, 27... Data transfer control section, 28... Transmit control section, 29... Receive control section,
30... Arithmetic unit, 31... CPU, 32... Data transfer device, 33... Common bus, a... Internal data bus, b
...Local control signal line, c...Local data bus, d...Local address bus, e...Control, f...Data bus, g...Address bus,
h...ready signal line, i...interrupt request signal line,
○B…Data transfer period, ○B CPU processing period, HIJ
K...CPU execution instruction, H′.I′.J′...data transfer period, XYX′.YZ′...data transfer instruction period.

Claims (1)

[Claims] 1 A common bus to which memory and input/output devices are connected in parallel, and a CPU connected to the common bus via a data transfer device, the data transfer device being connected to the common bus and the CPU, respectively. a buffer that temporarily holds data, a circuit that transfers data to the memory or input/output device in a handshake manner through the common bus, and a circuit that transfers data to the CPU when inputting data on the common bus to the CPU. A circuit that generates an interrupt signal, and a circuit that outputs data from the CPU to the common bus when the buffer is full.
and a circuit that puts the CPU in a wait state.
A data processing device characterized in that a CPU is coupled to the common bus only via the data transfer device.