JPH0784971A - Computer system - Google Patents

Abstract

PURPOSE:To provide a computer system which can be improved by the improvement of the hit rate of a cache and the effective utilization of common elements whichever address of a common memory control data to be executed by each processor is present in. CONSTITUTION:A CPU 12 starts access and if a cache miss is caused, a cache controller 14 outputs a request to retrieve all control data having added block tags which are stored in a block tag memory 8 and a main memory 9 to a memory controller 7. The memory controller 7 performs retrieval at the retrieval request and detects the contents of the block tags in order; when the contents are control data to be processed by the CPU 12 with high possibility, a request to write the control data in the cache memory 13 is outputted to the cache controller 14 and the control data is written at the request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing computer system having a plurality of processors and a shared element such as a memory shared by the processors.

[0002]

2. Description of the Related Art Conventionally, processing functions, control functions, etc., which have been concentrated in a single processor, are divided into a plurality of processors,
A computer system called a parallel processing system that performs control processing by distributed / cooperative processing is known.
For example, this conventional parallel processing system is configured such that a plurality of processors share a main storage device via a shared bus, and a plurality of processors access the shared memory to perform control processing. There is.

In this conventional parallel processing system, access of a plurality of processors to a shared memory may compete with each other, and it is essential to reduce the contention of this access as much as possible in order to improve system performance. . As a means for solving this problem, each of a plurality of processors is provided with a cache memory, each processor holds control data of a shared memory once accessed, and when each processor accesses the same data again, the shared data is shared. A method has been proposed in which the number of accesses to the shared memory is reduced by reading the data from the cache memory instead of the memory.

Further, in order to improve the hit rate of the cache memory, the block size of the control data fetched from the main storage device to the cache memory at the time of a cache miss is set to be larger than the data size required by the processor for one processing. Methods have also been proposed. According to this method, when the control data to be processed next to the control data causing the cache miss is present in the vicinity of the control data causing the cache miss, that is, in the fetched block, consecutive cache misses occur. Occurrence is avoided, the processor can reduce the number of accesses to the shared memory, and the system can be improved.

[0005]

However, in the above conventional computer system, in the method in which each of the plurality of processors is simply provided with the cache memory, when each processor accesses the same control data a plurality of times, Although it is possible to enjoy the effect of reducing the number of times of access to the shared memory, there is a problem in that access competition due to only one access has no effect.

Further, in the method of increasing the block size of the control data fetched in the cache memory, in general,
The block size of the control data fetched in the cache memory by one cache miss process is about 16 times the data amount required for one process of the processor,
After the transfer of this block is completed, no data transfer is requested until the next cache miss processing even if the bus usage rate remains low, resulting in wasted time during which data transfer is not performed. It was

Further, in the method of increasing the block size, for example, the control data processed by the processor next to the control data causing the cache miss is the control data existing at an address other than the block acquired by the cache miss. In other words, when the processor access is to control data existing at discrete addresses, the control method using the normal cache memory may have better system performance than the block transfer method. There was a problem.

The present invention has been made in view of the above problems, and improves the hit rate of the cache and effectively uses the shared element regardless of the address of the shared memory where the control data executed by each processor exists. An object is to provide a computer system capable of improving the system.

[0009]

In order to achieve the above object, the present invention provides a plurality of processors, a cache memory provided in association with each processor, and a plurality of processors shared by each processor and executed by each processor. In a parallel processing system including a main storage device for storing control information composed of the control data, and a control in which the additional information is added by the additional information adding means for adding the additional information to the control data. Writing means for writing data to the main memory, detecting means for detecting the additional information added by the additional information adding means, and searching means for searching all the additional information stored in the main memory,
Cache memory writing means for detecting the predetermined additional information by the detecting means from all the additional information searched by the searching means, and writing the control data to which the predetermined additional information is added to the cache memory corresponding to the processor. It is characterized by having.

Specifically, the additional information adding means is a block tag adding means for adding a block tag as the additional information, and each processor includes a block tag register for storing a block tag and the block. A write command for writing an arbitrary value to the tag register, and a reference command for referring to a block tag added to the control data, wherein the block tag adding means is the write command, and the searching means is the It is a reference instruction.

[0011]

According to the present invention, with the above-mentioned configuration, the additional information is added to the control data by the additional information adding means, the control data to which the additional information is added by the writing means is stored in the main storage device, and the processor stores the control. When the processing is started according to the data, the search means searches all the additional information, and the detecting means detects the predetermined additional information.
The control data to which the predetermined additional information is added by the cache memory writing means is written in a predetermined position in the cache memory.

Specifically, each processor writes an arbitrary value to the block tag register by a write command,
The result is stored in the main memory together with the control information, and when each processor starts processing in accordance with the stored control information, a predetermined block tag is searched from all the block tags by the reference instruction, and the cache memory writing means The control data to which a predetermined block tag is added is written to a predetermined address in the cache memory.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the schematic arrangement of an embodiment of a computer system according to the present invention. In the figure, the computer system of the present embodiment is a CPU
And processor elements 1 to 4 including a cache memory and the like, a bus arbiter 6 that arbitrates the use of the bus when the processor elements 1 to 4 simultaneously access the system bus 5, a memory controller 7 described in detail later, and the present invention. Block tag memory 8 for storing the block tags that characterize the above, and main memory 9 for storing the control programs and data of processor elements 1 to 4
And an external disk device 10 and an input / output controller (hereinafter referred to as “I / O controller”) 11 that transfers data between the external disk device 10 and the system bus 5.

Processor elements 1 to 4, bus arbiter 5, memory controller 7, block tag memory 8,
The main memory 9 and the I / O controller 11 are connected to each other via the system bus 5.

Here, the processor element 1 is a CP
U12 and cache memory 13 attached to CPU12
A cache memory controller 14 that controls the cache memory 13, a bus controller 16 that controls the internal bus 15 of the processor element 1, and an internal bus 1
5 and a bus interface 17 for interfacing with the system bus 5. Here, the bus controller 16 constantly decodes and monitors the address accessed by the CPU 12, and if access to the system bus 5 is required as a result, requests the bus arbiter 6 to acquire the bus, and the bus When acquired, the data is output to the system bus 5, and access to external elements such as the main memory 9 is started. This is a function of a general bus controller and is known.

The cache memory 13 is composed of a tag address section for storing a tag address, a block tag section for storing a block tag, and a data section for storing control data, and is composed of, for example, SRAM.

The processor elements 2 to 4 also have the same configuration as that of the processor element 1, and the computer system of this embodiment adopts a multiprocessor system having a four-processor configuration consisting of four processor elements 1 to 4. did. However, the present invention is not limited to the case where the number of processors is four.

FIG. 2 is a memory map showing an example of the contents stored in the block tag memory 8 and the main memory 9 of FIG. 1, and the physical address, the contents of the block tag memory 8 and the main memory 9 are arranged in order from the left. Shows the contents of. In this embodiment, C of the processor elements 1 to 4 is used.
When the address is accessed by the PU, the contents of the block tag memory 8 and the main memory 9 at the specified address are both output. That is, the data structure of the data handled in the present embodiment has a data structure in which one block tag data is added to each of the data (contents) stored in the main memory 9.

Further, in this embodiment, the block tag memory 8 and the main memory 9 both have a physical address of 0h.
Addresses from the address to 000FFFFCh are allocated, the physical address is every 4 bytes, the block tag memory 8 has 2 bytes of data (block tag), and the main memory 9 has 4 bytes of data (program, table data, etc.). have. Here, h indicates that it is a hexadecimal number.

For example, when the physical address is address 0h,
The memory content of the block tag memory 8 is "0000h", and the memory content of the main memory 9 is also "0000000".
When the physical address is 4h, the memory contents of the block tag memory 8 and the main memory 9 are "0000h" and "00FF0F, respectively.
When the physical address is 0Ah, the memory contents of the block tag memory 8 and the main memory 9 are "0001h" and "9ABCDEF0h", respectively.
Is. That is, as described above, each 4 of the main memory 9
A 2-byte block tag is added to the byte data.

Hereinafter, the description will be continued assuming that the data shown in the memory map of FIG. 2 is stored in advance in the block tag memory 8 and the main memory 9.

FIG. 3 is a block diagram showing a detailed configuration of the processor element 1 of FIG.

As mentioned above, the processor element 1
Is a CPU 12, a cache memory 13, a cache memory controller 14, and a bus controller 16
And a bus interface 17, and the respective elements are mutually connected by an internal bus 15.

The internal bus 15 includes a data bus B1 for transmitting control data executed by the CPU 12, a block tag bus B2 for transmitting a block tag, and an address bus B.
3, a control bus B4, and a bus B5 including control signals used for arbitration of other internal buses. Here, the control bus B4 is
The address strobe signal (/ AS) indicating that a valid address is output to the address bus B3, and the CPU
12 read / write signals (R) indicating whether the access is a memory read cycle or a memory write cycle.
// W), a retry signal (/ RETRY) requesting access to the same address as the address accessed immediately before to the CPU 12, a termination signal (/ TERM) indicating that the access is completed, and reading of the cache memory Confirmation signal (/ AC
K) and. The bus B5 has an internal bus use right request signal / BR and an internal bus use right permission signal / B.
G and an internal bus permission confirmation signal / BGACK.

The CPU 12 and the bus interface 17 are mutually connected via a data bus B1, a block tag bus B2, an address bus B3, and a control bus B4. Similarly, the bus interface 17 and the system bus 5 are connected.
And are connected to each other via these four types of buses.

The cache memory 13 is a direct mapping type write-through cache having a capacity of 32 Kbytes, the address of which is supplied with the addresses A2 to A14 of the address bus B3, and the data input of the address tag portion thereof. , The upper 2 bytes (A15 to A31) of the address bus B3 are supplied. Further, the data inputs of the block tag section and the data section of the cache memory 13 are connected to the block tag bus B2 and the data bus B1, respectively. That is, the contents of the address tag portion, the block tag portion, and the data portion are read from and written to the cache memory 13 in accordance with the address designated by the A2 to A14 bits of the address bus B3.

The data output of the address tag portion of the cache memory 13 is supplied to one input terminal of the comparator 18, and the other input terminal of the comparator 18 is supplied with the upper 2 bytes of the address bus B3. The comparator 18 supplies the output signal / HIT to the cache memory controller 14, compares the input data output of the address tag unit with the upper 2 bytes of the address bus B3, and when they match, that is, when a cache hit occurs. When signal / HIT is set to low level and they do not match,
That is, when a cache miss occurs, the signal / HIT is set to a high level to notify the cache memory controller 14 of whether or not there is a cache hit.

The cache memory controller 14 transmits / receives various control information to / from the CPU 12 and the bus interface 17 via the control bus B4, and based on the signal / HIT and various control information, the cache memory controller 14 stores the memory information. Write request signal / CR
Outputs AMW.

The bus controller 16 uses the address bus B
3 and is connected to the CPU 12 via the bus B5.
It is connected to the. Further, the bus controller 16 outputs the cache write signal / CWR1 for outputting a write request to the cache memory 13 by the memory controller 7 of FIG. 1 and the system bus arbiter 6 of FIG. Three types of signals R, G, BB for requesting / confirming that the system bus 5 is released
Is connected to the system bus 5 via a signal line for transmitting a control signal BCNT for releasing the buses B1 to B4, and a write request to the cache memory 13 is transmitted. It is connected to the cache memory controller 14 via a signal line that transmits a signal to be performed / MEMWR.

Here, the bus B5 is used for the above-mentioned three types of signals /
BR, / BG, / BGACK consists of
The signals R, G, and BB represent a bus use right request signal, a bus use right permission signal, and a bus permission confirmation signal for the system bus 5, respectively. These three types of signals / BR, / BG,
/ BGACK and signals R, G, BB, and CP
The U12 and the bus controller 16 perform data transmission by the well-known 3-wire handshake control.

The bus controller 16 constantly decodes and monitors the access address output by the CPU 12, and as a result, when access to the system bus 5 is required,
A signal R outputs a bus use right request to the system bus arbiter 6. After that, when the acquisition of the system bus 5 is reported by the signal G, the bus controller 16 outputs the signal BB to the system bus 5 and the signal BCNT to the bus interface 17, and the internal buses B1 to B1 of the processor element 1 are output. Connect B4 to the system bus 5. This allows access to external elements. Further, the bus controller 16 requests the CPU 12 to release the internal buses B1 to B4 of the processor element 1 based on the cache write request signal / CWR1 output from the memory controller 7, and when the bus is acquired, the cache memory controller A function for making a write request to the cache memory 13 is added to the cache memory 14.

FIG. 4 is a block diagram showing a detailed structure of the CPU 12 of FIG.

Although FIG. 1 shows the detailed structure of the CPU 12 of the processor element 1, the CPUs of the other processor elements 2 to 4 also have the same structure.

The CPU 12 includes an instruction executing unit 21, a multiplexer (MUX) 22, a built-in memory management unit (MMU) 23, a block tag register 24 for reading and writing a block tag, and the processor element 1.
It is mainly configured by a bus interface 25 for interfacing with the internal buses B1 to B5 of FIG.

Here, the instruction execution unit 21 is composed of, for example, an instruction fetch unit (IF), a decode unit (DECODE), an operand fetch unit (OF), an execution unit (EXEC), and a writeback unit (WB). The control is performed by the control method executed by the CPU. It should be noted that, of the elements constituting the CPU 12, the elements other than the block tag register 24 are included in a general CPU, and the elements are mutually connected by an internal bus.

The CPU 12 can write an arbitrary block tag to the block tag register 24 by the BLKL instruction. When writing the block tag to the block tag memory 8 of FIG. 1, the block tag is transferred to the block tag bus B2. Output to. Also, the CPU 12 sets the BL
By the KR instruction, the block tag of an arbitrary address stored in the block tag memory 8 can be read into a general-purpose register (not shown) inside the CPU 12. In this reading method, first, a desired address is designated and the content of the block tag memory 8 is read. At this time, actually, the stored content is read from the main memory 9, and the block tag of the block tag memory 8 stored at the same address is read along with the stored content. The block tag is output to the block tag bus in the system bus 5 and then transmitted to the block tag bus B2 in the processor element 1. Next, the CPU 12
Reads the contents of the block tag bus B2 into the block tag register 24 and then transfers the contents to the general purpose register by internal data transfer.

As will be described later, in this embodiment, the function of the block tag register 24 is not used, and when a block tag is generated, an external CPU (not shown) is used, and the block The memory controller 7 is used to detect or search for a tag. Needless to say, the CPU performs the generation or detection / search of a block tag.
12 can also be used.

FIG. 5 is a block diagram showing a detailed structure of the cache memory controller of FIG.

The cache memory controller 14 has four types of input control signals (/ MEMWR, /
AS, / HIT, R // W), control signal / RET
RY, READHIT (/ STERM), WRITEH
OR gates 31 to 34 for generating IT and MEMWRITE (/ ACK) and output signal of OR gate 31 /
The signal RE is obtained by taking the logical sum of the D flip-prop 35 for outputting RETRY in synchronization with the signal / AS and the D flip-prop 35 and the signal / AS.
OR gate 36 for generating PLACE, the signal REPLACE, the signals WRITEHIT, MEMW
AND gate 37 for generating a signal / CRAMW by taking the logical product of RITE.

The operation of the processor element 1 configured as described above will be described with reference to FIGS.

In FIG. 3, when the CPU 12 accesses an arbitrary address, for example, the address at address 000FFFF4h in FIG. 2, the address of bits A2 to A14, that is, the address tag of the cache memory 13 designated by "3FFDh". Content of the part is comparator 1
8 and is the other input of the comparator 18, the upper bits (A15 to A31), that is, “000F”.
h ". As a result, if there is a match, the signal /
HIT goes low, and the contents of the block tag portion and the data portion stored in the cache memory 13 are output to the buses B2 and B3, respectively.

On the other hand, if they do not match, the signal / HIT goes high and the cache memory controller 14
Requesting re-access of the CPU 12, and then the CPU
12 again executes access to the same address. By this access, the signal / CRAMW becomes low level, the results read from the block tag memory 8 and the main memory 9 are written in the block tag section and the data section of the cache memory 13, and the high-order bit "000Fh" of the address is written. Is written in the address tag portion of the cache memory 13. The above operation is
This is a general operation of a cache memory and is well known.

Further, a memory write request signal / MEMWR is input from the bus controller 16 to the cache memory controller 14 in the present invention, and as will be described later, a write request (signal to the cache memory 13 of the processor element 1 is sent from the memory controller 7). / CWR1) is performed, the bus controller 16
Processes the request. That is, the bus controller 16 requests the CPU 12 to acquire the internal buses B1 to B4, and when the bus acquisition is completed, the signal BCN is acquired.
The bus interface 17 is opened via T to reflect the data, address, block tag, and control signals in the system bus 5 to the internal bus, and the signal / MEMWR is set to low level. The cache memory controller 14 is
When the signal / MEMWR becomes the low level and the signal / AS becomes the low level, the signal / CRAMW is set to the low level, the block tag and the data on the bus are written in the cache memory 13, and at the same time, the signal / ACK is returned and the write request to the memory controller 7 is completed. Let me know.

With the above operation, the memory controller 7
When a write request is issued from the device, the data existing on the system bus 5 is written to the desired cache memory.

FIG. 6 is a block diagram showing a detailed structure of the memory controller 7 of FIG.

The memory controller 7 monitors the read request made by each CPU of the processor elements 1 to 4 to the main memory 9, and when the read request is made, the address, the block tag, the CPU number of the request, etc. Is controlled by the dynamic allocation controller 42, a dynamic allocation controller 42 which will be described later in detail, a bus controller 43 which acquires the system bus 5 acquisition request by the dynamic allocation controller 42, and a dynamic allocation controller 42. Bus interfaces 44 and 45 for connecting the buses of the block tag memory 8 and the main memory 9 to one or both of the dynamic allocation controller 42 and the system bus 5.
And a DRAM controller 46 for generating and refreshing dynamic RAM (DRAM) addresses. Further, the DRAM controller 46 includes a dynamic allocation controller 4
When the signal / READ is output by 2, the function of forcibly setting the block tag memory 8 and the main memory 9 to the read state is added.

FIG. 7 is a block diagram showing a detailed structure of the snooper latch circuit 41 shown in FIG.

The snooper latch circuit 41 is connected to the address bus in the system bus 5 to decode the address content, and the address latch circuit 5 which is also connected to the address bus to latch the address content.
2, a block tag latch circuit 53 that is connected to the block tag data bus in the system bus 5 and latches a block tag, and a CPUID latch circuit 54 that latches the CPU number that issued the read request. .

The decode circuit 51 constantly monitors the address of the address bus and outputs a low level when the address is output to the bus. The output of the decoding circuit 51 is connected to one input terminal of a 4-input OR gate 55, and the signal R // W transmitted by the control bus in the system bus 5 is supplied to the inverter 56 at the other 3 input terminals.
The inverted signal inverted by the signal / AS and R
The output Q of the S flip-flop 57 is supplied with the inverted signal inverted by the inverter 58, the output of the OR gate 55 is supplied to the input R of the RS flip-flop 57, and the input S of the RS flip-flop 57 is 5 output of dynamic allocation controller 42 / R
ESET is supplied.

The output Q of the RS flip-flop 57 is used as a clock input of the address latch circuit 52 and the CPUID latch circuit 54, and an acknowledge signal for detecting the signal / ACK of the control bus in the system bus 5. Via the detection circuit 59,
It is used as a clock input of the block tag latch circuit 53, and is further supplied to the dynamic allocation controller 42 as a signal / START for changing the state of a sequencer constituting the dynamic allocation controller 42 described later.

The address latch circuit 52 outputs the latch address to the dynamic allocation controller 42, and similarly, the block tag latch circuit 53 and the CPU.
The ID latch circuit 54 outputs the latch block tag and the latch CPUID to the dynamic allocation controller 42, respectively.

Thus, the processor elements 1 to
When any one of the four CPUs issues a read request to the main memory 9, the signal R // W goes high, so the output of the OR gate 55 goes low, and the output Q of the RS flip-flop 57. Goes high. As a result, the address requested by the CPU for reading is latched in the address latch circuit 52, and the CPU number CPUID is latched in the CPUID latch circuit 54. Further, when the content of the main memory 9 is read by a read request and the block tag of the block tag memory 8 of the same address is read at the same time, the block tag is synchronized with the output of the acknowledge signal (ACK) detection circuit 58. And is latched by the block tag latch circuit 53. The data once latched by each latch circuit is held unchanged until the signal / RESET is input.

FIG. 8 is a block diagram showing a detailed structure of the dynamic allocation controller 42 shown in FIG.

The dynamic allocation controller 42 includes, for example, a sequencer 61 composed of a sequencer-configuring PAL, an address counter 62 for loading a latch address output from the snooper latch circuit 41, and counting up the address, and two address counters. It is mainly configured by the comparators 63 and 64.

The signal / START is input to the sequencer 61 from the snooper latch circuit 41, and the bus use right grant signal GRANT is input from the bus controller 43.
Is input and, via the bus interface 44, signals / ACK, / of the control bus in the system bus 5 are input.
AS is input. Further, the sequencer 61 outputs the signal / RESET to the snooper latch circuit 41, and outputs the bus use right request signal REQUEST to the bus controller 43.
Control signal BUSCON that outputs to and controls the connection of the bus
T1 and BUSCONT2 are output to the bus interfaces 44 and 45, respectively, and the signal / READ is output to the DRAM controller 46. Furthermore, the sequencer 61
Is a signal LOA for loading the latch address
The address counter 6 outputs the count clock (COUNT CLOCK) for performing D and the count up.
2 and outputs the signal / WRITE for controlling the write request signals / CWR1 to 4 to one input terminal of the OR gates 65 to 68.

The other input terminals of the OR gates 65 to 68 are respectively connected to the latched CPU number CPUID.
(/ CPU1 to 4) are input, and OR gates 65 to 68
Is for writing the contents read from the block tag memory 8 and the main memory 9 to the associated cache memory in any of the CPUs of the processor elements 1 to 4 according to the input signal / WRITE, CPUID. The write request signal (/ CWR1 to 4) is output.

The address counter 62 outputs the counted address to the bus interface 45 and also to one input terminal of the comparator 64. The comparator 64 outputs the address value and the END address output to the other input terminal. The output value of the circuit 69 is compared, and the comparison result is output to the sequencer 61 as a signal / END. In this embodiment, the END address circuit 69 is the last address of the main memory 9, that is, "000FFFFC.
It is set to h ".

Further, the comparator 63 receives the latch block tag from the snooper latch circuit 41 inputted to its two input terminals and the signal B of the block tag bus in the system bus 5 supplied by the bus interface 44.
LOCKTAG is compared, and the comparison result is signal / MA
It is output to the sequencer 61 as TBLK.

Next, the processing operation of the computer system configured as described above will be described.

The computer system according to the present invention is assumed to be, for example, a parallel processing system in which an operating system capable of multitask processing such as UNIX is mounted, and processing is shared by a plurality of processors in each process unit or each module unit. However, of course, the present invention is not limited to this system configuration.

First, a method of creating a program that operates on the computer system of this embodiment will be described.

The programmer makes a declaration to the assembler so as to set the same block tag for a series of programs that are likely to be executed by the same processor (processor elements 1 to 4 in this embodiment). In the case of a high-level language compiler, the block tag number can be declared automatically. The assembler used in this embodiment is, for example, a machine language generated by a CPU as described in FIG. 4, and when a declaration for adding a block tag is detected during the operation, the assembler declares the machine language. The block tag is written into the block tag register, the written block tag is added to the generated machine language code which is the execution module, and the block tag is written into a working memory or a file (not shown).

Also, the programmer is already in the main memory 9
When rewriting the control data stored in the
It is also possible to read the block tag added to the control data by the KR instruction and program it to add the block tag to the newly generated control data.

As described above, the program to which the block tag is added, the table data and the like (control data) are generated, and the control data is the I / O controller 1 of FIG.
1 is stored in the external disk device 10. At this time, the I / O controller 11 stores the block tag in the external disk device 10 by handling the block tag as a part of the control data (program, table data, etc.), while controlling the block tag added from the external disk device 10. When reading data, the block tag is output to the block tag bus of the system bus 5, and the control data is output to the data bus of the system bus 5. As a result, the block tag and control data are stored in the block tag memory 8 and the main memory 9, respectively.

In the present embodiment, the above processing is carried out by using a processor (not shown) independent of the I / O controller 11, but the present invention is not limited to this, and it may be carried out by using the CPU 12, for example. Good.

Next, the processing operation when the computer system of this embodiment actually executes the program (control data) generated as described above will be described with reference to FIG.

FIG. 9 is a state transition diagram showing state transitions of the sequencer 61 of FIG.

First, one of the CPUs in the processor elements 1 to 4 requests the I / O controller 11 to load a file (program) stored in the external disk device 10. In response to this request, as described above, the I / O controller 11 searches the external disk device 10 for a desired file, separates the block tag and the data from the file, and establishes the block tag bus and the data bus. Write to designated addresses in the block tag memory 8 and the main memory 9, respectively. When the writing of all the data of the file is completed, the I / O controller 11 causes an interrupt to all the CPUs of the processor elements 1 to 4. By this write completion interrupt, each CPU initializes all the contents of the cache memory in each processor element 1 to 4.

Next, one of the CPUs of the processor elements 1 to 4 starts the processing operation according to the program stored in the main memory 9. For example, the description will be continued assuming that the CPU 12 of the processor element 1 has started the processing operation.

The CPU 12 starts fetching the instruction code from the start address of the program stored in the main memory 9. For convenience of explanation, the start address is the address 0 of the physical address, and the CPU 12 first sets 0.
The instruction code at the address is fetched.

Since a series of processing until the CPU 12 starts the processing as described above is generally performed by the operating system, detailed description thereof will be omitted.
Hereinafter, a description will be given from the state where the processing of the operating system has progressed to some extent, the user program has been loaded, and the cache memories in the processor elements 1 to 4 have been initialized.

Needless to say, the present invention can also be applied to a system program of an operating system.

The CPU 12 performs a read operation on the address 0. Since the cache memory 13 has already been initialized, the hit signal / HIT is not output (low level) by the comparator 18 for this access (read operation), and the cache memory controller 14 of FIG. Signal / RET
RY goes low and the CPU 12 is requested to re-execute the access. When the access is terminated by the signal / RETRY, the CPU 12 again accesses the same address as the previous access. That is,
The address 0 is accessed again.

At the second access, the signal REPLAC
E becomes low level and signal / CRAMW for writing to cache memory is output (low level)
To be done. At this time, the cache memory controller 14
Since no termination signal of signals / RETRY and / STERM is output from CPU to CPU 12, access is continued. The bus controller 15 is the CPU 12
The output address is decoded and a bus use request R is output to the bus arbiter 6 when access to the external bus (system bus 5) is required.

As described above, the bus arbiter 6 arbitrates bus use requests. As a result, when the use permission is given, the bus controller 6 outputs the bus use signal BB to start using the bus. As a result, a read request for address 0 in the main memory is output to the system bus 5. At this point, the sequencer 61 of the dynamic allocation controller 42 of FIG. 8 has the state 0 of the state transition diagram of FIG.
Is in the state of.

At this time, the bus interface 4 of FIG.
4 becomes a memory accessible state by the signal BUSCONT1. At this time, the bus interface 4
5 is the cutoff. Therefore, a read request for address 0 on the system bus 5 is issued by the DRAM controller 4
It is transmitted to the main memory 9 via 6. As a result, the block tag "0000h" stored at address 0 is output from the block tag memory 8 onto the system bus 5,
Data “00000000h” is output from the main memory 9 onto the system bus 5.

The CPU 12 fetches the contents of the system bus 5 into the CPU and stores the contents in the cache memory 13 at the same time as the processing is continued. At the same time, the read process is detected by the snooper latch circuit 41. This detection is performed as follows. First, FIG.
The decoding circuit 51 detects that the main memory 9 is accessed, and the signal R // in the control bus is detected.
It is judged from W and the signal / AS that it is a legitimate read process. As a result, the output of the OR gate 55 becomes low level, the output of the RS flip-flop 57 becomes low level, and the detection of the read operation ends.

When the read operation is detected, the address at that time is stored in the address latch circuit 52, and the CPUID making the request is stored in the CPUID latch circuit 54. At present, the address 0 and the number of the CPU 12 are stored respectively. Further, when the data is output from the main memory 9 and the block tag is output from the block tag memory 8, the acknowledge signal detection circuit 59 detects the acknowledge signal / ACK, and the content "0000h" of the block tag at this time is the block tag. It is stored in the latch circuit 53.

The outputs of these latch circuits 54, 52 and 53 are output to the dynamic allocation controller 42 as signals / CPU1 to CPU4, latch address and latch block tag, respectively. Further, the output of the RS flip-flop 57 is output to the sequencer 61 as a signal / START.

The sequencer 61 advances to state 1 by this signal / START. Sequencer 61 in state 1
Loads the latch address input from the snooper latch circuit 41 into the address counter 62 and monitors the signal / AS.

When the signal / AS becomes high level (transfer is completed), the state 2 is entered.

In the state 2, the bus interface 44 is cut off by the signal BUSCONT1. Then, it proceeds to state 3.

In state 3, the address counter 62 is counted up by 4, the bus interface 45 is opened, and the output of the address counter 62 is used as an address to read the contents of the block tag of the block tag memory 8. Then proceed to state 4.

In state 4, as described above, END
If the final address has been reached by referring to the output of the comparator 64 that compares the END address value “000FFFFCh” preset in the address output circuit 69 with the current count value of the address counter 62, state 10
Then, the signal / RESET is set to low level. As a result, the RS flip-flop 57 of the snooper latch circuit 41.
Is set and the bus is in the snoop state again. After that, the process returns to the state 0 and the process is completed. Since it has not reached the final address at this time, it proceeds to state 5. At this time, since the output of the counter is "4h", the content of the block tag read with this as an address is "0h".

In state 5, the sequencer 61 refers to the comparison result of the comparator 63 which compares the content of the block tag input from the block tag memory 8 with the content of the latch block tag previously latched by the block tag circuit 53. , If there is no match as a result, signal / MAT
Since BLK is at high level, it returns to state 3. After that, the same process is continued until the final address while incrementing the address counter by 4. Now, the content of the block tag and the content of the latch block tag are both "0".
Since they match in h ″, the process proceeds to state 6.

In state 6, the bus arbiter 6 is requested to use the system bus 5. After that, when the bus arbiter 6 permits the use, the process proceeds to state 7.

In the state 7, the write operation to the cache memory 13 is performed with respect to the processor element 1 which has issued the read request currently latched. This write operation is processed as follows. Sequencer 61
When the signal / WRITE is output (low level), C
CPUID latched in PUID latch circuit 54
(Signal / CPU1, / CPU2, / CPU3, / CPU
4) OR any of the OR gates 65 to 68
The output of the circuit goes low. In this embodiment, the signal / CWR1 which is the output of the OR gate 65 becomes low level. At the same time, the signal R // W is set to high level to open the bus interfaces 44 and 45. As a result, system bus 5
The output from the address counter 62 is output as an address, and the contents of the block tag memory 8 and the main memory 9 are output as a block tag and data. Then proceed to State 8.

In the state 8, after the signal / AS is set to the low level, the acknowledge signal / ACK from the cache memory 13 for writing is waited.

At this point, the processor element 1 has
The signal / CWR1 is input to the bus controller 15, and as a result, the bus controller 15 requests the CPU 12 to release the internal bus. When the CPU 12 notifies that the internal bus has been released, the bus controller 15
Opens the bus interface 17 and the external system bus 5
The above signal is reflected on the internal bus. Further, the signal / MEMWR is set to low level and output to the cache memory controller 14. As a result, in the cache memory controller 14 of FIG. 5, the signal MEMWRITE goes low and the signal / CRAMW goes low.
Therefore, the high-order bits (A15 to A3) of the block tag, the data, and the address read from the block tag memory 8 and the main memory 9 are stored in the cache memory 13.
1) is written, and at the same time, the signal / ACK is output on the system bus 5. If the signal / ACK is detected, the state goes to 9.

In the state 9, the signal / AS is returned to the high level and the state 2 is returned.

Hereinafter, the same operation as described above is performed up to the end address.

The control is performed as described above, and the instruction code and the data having the same block tag in the main memory 9 are sequentially written in the same cache memory. This control operation is similarly performed for an access from a CPU other than the CPU 12, and as a result, the instruction code and data having a high probability of a cache hit in the subsequent processing at the cache memory 4 in each processor element are effective. Written in
Efficient use of the shared bus and improved cache hit rate are obtained.

In this embodiment, the addresses "4h", "8"
The contents such as "h" and "000FFFF4h" are stored in the CPU 12
Is written to the cache memory associated with the.

Next, another embodiment of the computer system according to the present invention will be described.

The configuration of this embodiment is the same as that of the first embodiment except for the dynamic allocation controller. Therefore, the same elements as those of the first embodiment are designated by the same reference numerals, and the detailed description thereof will be omitted.

FIG. 10 is a block diagram showing the detailed structure of the dynamic allocation controller of this embodiment.

The dynamic allocation controller of this embodiment is different from the dynamic allocation controller of the first embodiment in that the block tag is written in the cache memory 13 in the dynamic allocation controller 42 of the first embodiment. A counter 71 that counts up each time you search for
The point is that a predetermined count value can be set in advance and a count value output circuit 72 that outputs the value is added. Therefore, the same elements as those of the dynamic allocation controller 42 of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The output of the counter 71 is connected to one input terminal of the comparator 64, and the output of the count value output circuit is connected to the other input terminal of the comparator 64.
The connection relationship of other elements is the same as that of the first embodiment.

FIG. 11 is a state transition diagram showing the state transition of the sequencer of this embodiment. The processing operation of the computer system of this embodiment will be described below with reference to this figure.

The operation until the access to the address 0 by the CPU 12 starts is the same as that of the embodiment. Main memory 9
When a read request for the address 0 is output from the CPU 12 to the system bus 5, the sequencer 61 of the dynamic allocation controller of FIG. 10 is in the state 0 of FIG.

When the state of the sequencer 61 advances to state 1 as in the first embodiment, the counter 71 is reset in addition to the processing described in the first embodiment. After that, the operation up to the state 3 is the same as in the seventh embodiment.

In state 3, the address counter 62 is set to 4
Then, the bus interface 45 of FIG. 6 is opened and the output of the counter 62 is used as an address to read the contents of the block tag of the block tag memory 8. Further, the count value of the counter 71 is incremented by 1. Then proceed to state 4. In the state 4, the count number preset in the count value output circuit 72 (for example, 10 in this embodiment).
The output signal / END of the comparator 64 that compares the value of the counter 71 with the value of the counter 71 is referred to. As a result, if the set number of counts has been reached, the process returns to state 0 and ends the processing. Since the end count number (setting value) has not yet been reached, the process proceeds to state 5. Further, since the output of the counter 62 is now "4h", the content of the block tag read using this as an address is "0h".

In the state 5, the comparison result of the comparator 63 which compares the contents of the block tag input from the block tag memory 8 with the contents of the latch block tag previously latched by the block tag latch circuit of FIG. 7 is referred to. As a result, when they do not match, the signal / MATBLK becomes high level, and therefore the state returns to state 3, and thereafter the same processing is continued until the final address (set value) while incrementing the address counter 62 by 4. Since both the block tag and the output latch block tag are now "0h" and coincide with each other, the process proceeds to state 6.

Since the subsequent processing is the same as that of the first embodiment, its explanation is omitted.

As described above, in this embodiment, in the case of a system having a large memory capacity, the block search will not be continued more than necessary.

[0107]

As described above, according to the present invention,
Parallel processing including a plurality of processors, a cache memory provided in association with the respective processors, and a main storage device which is shared by the respective processors and stores control information composed of a plurality of control data executed by the respective processors In the system, additional information adding means for adding additional information to the control data, writing means for writing control data to which the additional information has been added by the additional information adding means to the main storage device, and addition by the additional information adding means Detecting means for detecting the additional information retrieved, search means for retrieving all the additional information stored in the main storage device, and predetermined additional information by the detecting means from all the additional information retrieved by the retrieving means. Is detected and the control data to which the predetermined additional information is added is written to the cache memory corresponding to the processor. Since it has a cache memory writing means, the cache hit rate is improved even if the access addresses of each processor are dispersed, and it is hit by using the unused time of the bus from one cache miss to the next cache miss. Control data having a high rate can be transferred to the cache memory, and the effective use of shared resources can be achieved. In particular, a large hit rate can be obtained for data such as table data among the control data.

More specifically, the additional information adding means is block tag adding means for adding a block tag as the additional information, and each processor has a block tag register for storing the block tag. The block tag register has a write command for writing an arbitrary value and a reference command for referencing a block tag added to the control data, the block tag adding means is the write command, and the searching means is Since it is the above-mentioned reference instruction, the block tag can be generated and searched by the processor configuring this system without using a processor different from this system for the generation and search of the block tag. It can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a computer system according to the present invention.

FIG. 2 is a memory map showing an example of contents stored in a block tag memory and a main memory of FIG.

FIG. 3 is a block diagram showing a detailed configuration of each processor element in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a CPU shown in FIG.

FIG. 5 is a block diagram showing a detailed configuration of the cache memory controller of FIG.

FIG. 6 is a block diagram showing a detailed configuration of the memory controller of FIG.

FIG. 7 is a block diagram showing a detailed configuration of the snooper latch circuit of FIG.

8 is a block diagram showing a detailed configuration of the dynamic allocation controller of FIG.

9 is a state transition diagram showing state transitions of the sequencer of FIG.

FIG. 10 is a block diagram showing a detailed configuration of a dynamic allocation controller that constitutes a computer system according to another embodiment.

11 is a state transition diagram showing state transitions of the sequencer of FIG.

[Explanation of symbols]

12 CPU (block tag addition means) 14 Cache memory controller (cache memory writing means) 61 Sequencer (detection means, search means)

Claims (3)

[Claims] 1. A plurality of processors, a cache memory provided in association with each processor, and a main storage device that stores control information that is shared by each processor and that is composed of a plurality of control data executed by each processor. A parallel processing system including: additional information adding means for adding additional information to the control data; writing means for writing the control data to which the additional information is added by the additional information adding means to the main storage device;
The detecting means for detecting the additional information added by the additional information adding means, the searching means for searching all the additional information stored in the main storage device, and the all the additional information searched by the searching means A computer system comprising: a cache memory writing unit that detects predetermined additional information by the detection unit and writes the control data to which the predetermined additional information is added to a cache memory corresponding to the processor. 2. The computer system according to claim 1, wherein the additional information adding means is block tag adding means for adding a block tag as the additional information. 3. Each of the processors includes a block tag register for storing a block tag, a write command for writing an arbitrary value in the block tag register, and a reference command for referring to the block tag added to the control data. 3. The computer system according to claim 2, wherein the block tag adding unit is the write command, and the search unit is the reference command.