JP2001043204A - Cache memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce load caused by the bus snooping operation of each processor for guaranteeing the coherency of a cache in a multiprocessor system. SOLUTION: A function for guaranteeing the coherency of cache memories 120 and 220 is added to a system bus-I/O bus bridge 300. The bridge 300 singly discriminates whether cache matching processing is required for the data of an address to be accessed or not and only when cache matching processing is required, it is instructed to the relevant processor. Besides, address and tag information showing the address on a shared memory 400 and the state of the data held on the cache memories 120 and 220 inside respective processors 100 and 200 is held just by cache capacity for the unit of a cache line in processor cache tag tables 350 and 351.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control device for a multiprocessor system having a shared memory, and more particularly to a coherency control device for a multiprocessor system which guarantees cache coherency by a bus snoop method. The present invention relates to a cache memory control device that performs guarantee control at high speed and efficiently.

[0002]

2. Description of the Related Art Generally, in a multi-processor system having a cache memory and a shared memory, coherency must be guaranteed for all data stored in the cache memory and the shared memory in the system. This guarantee of coherency means that devices under the I / O bus that can access each processor and the shared memory can access the latest data corresponding to a specific address. For example, a particular processor stores a copy of the data at a particular address of the shared memory in a cache memory, and
If only the data in the cache memory is updated,
I / O that can access other processors and shared memory
This means that the device under the O bus must access the updated data existing in the cache memory as the data at the address.

In general, as a method of guaranteeing coherency of a cache in a multi-processor system,
It is known to rely on the bus snooping operation of each processor having a cache memory.
In this method, each processor having a cache memory in a multi-processor system monitors a memory access by a device under an I / O bus that can always access another processor and a shared memory, and stores data at an appropriate address. Is checked whether it exists in its own cache memory, and if necessary, a cache matching process is performed. According to this method, even if the memory access does not require the cache coherency processing, a snooping operation by each processor described above is always performed for each memory access for the determination, and the overhead of each processor increases. Therefore, there is a problem that the system performance is deteriorated, and various techniques have been proposed to solve the problem.

As an example of such a conventional technique, for example, a cache memory control device disclosed in Japanese Patent Application Laid-Open No. H10-55314 can be mentioned. In this cache memory control device, in order to avoid unnecessary bus snooping operation by each processor, state storage means for expressing the state of caching of data on the shared memory in units of cache lines, and the state storage means A determining circuit for determining whether or not snooping of another cache is necessary according to the contents of the means; a suspending signal control circuit for issuing a snoop suspending signal based on the determination result of the determining circuit; and a snooping control for each cache control unit of each processor. And a suspending circuit are provided, and a bus snooping operation is performed by each processor for memory access as in the past, but when it is determined that snooping is unnecessary by referring to the state storage means at the same time,
The interruption signal control circuit instructs the interruption circuit of the processor to suspend the snoop without waiting for the end of the snoop, thereby reducing the system performance degradation due to unnecessary bus snooping operation of each processor.

FIG. 10 is an overall configuration diagram for implementing an example of the cache memory control device described in the publication. The cache memory controller 1 (4) and the like are connected to the signal line (2
1) and the like, and to the cache 1 (7) and the like via a signal line (24) and the like. Also, each of the cache controllers 1 (4) to n
(6) and the main memory controller (10)
They are connected to each other via (27), and data transfer and snoop control are performed via the signal group (27). The signal (30) is a snoop interruption signal sent from the main memory controller (10) to each of the cache controllers 1 (4) to n (6).

The state storage means (12) is a main memory (11)
Has one table entry for each block in the memory space, and if the content of the entry is "00", it means that the data of the block is not stored in any cache; Indicates that the data of the block is stored in at least one cache and its contents match the main memory, and if "10", the data of the block is stored in at least one cache and its contents Means that it does not match the main memory.

The main memory controller (10) refers to state storage means (including a directory) (12) storing the state of the cache, and determines whether or not snooping is necessary. As a result, when the snoop is unnecessary, the snoop interruption signal (30) for notifying the snoop interruption to the cache controllers (4) to (6) is issued. In the cache controllers (4) to (6), the snoop interruption signal (3
0), the snoop is interrupted. As described above, the present apparatus reduces unnecessary cache snooping by using both the snoop method and the directory method.

[0008]

However, in the prior art described in the above-mentioned Japanese Patent Application Laid-Open No. H10-55314, even a processor which does not need the cache coherence processing needs a bus and a bus.
There is a first problem that a load of the snooping operation occurs. The reason is that each processor unconditionally performs a snooping operation every time a memory access is performed, and after the main memory controller refers to the state storage means, the snoop is interrupted if unnecessary. Because.

There is also a second problem that the memory capacity of the state storage means is increased. The reason is that it is necessary to manage the state of caching for all data in the shared memory in units of cache lines in the state storage means. For example, as described in the above publication, it is assumed that the cache state per cache line is managed by 2 bits, the shared memory size is 256 Mbytes, and the cache line size is 3 bits.
In the case of a 2-byte system, the state storage means requires a capacity of as much as 16 Mbits.

A first object of the present invention is to provide a multi-processor by concentrating a function for guaranteeing coherency of a cache which each processor has conventionally had individually on a system bus-I / O bus bridge. The object of the present invention is to provide a cache memory control device that eliminates a load due to a bus snooping operation of each processor in a system and improves the performance of the entire system.

A second object of the present invention is to provide a system bus-I /
An object of the present invention is to provide a cache memory controller which is implemented as small as possible in an O bus bridge.

[0012]

According to a first aspect of the present invention, there is provided a cache memory control device, wherein each processor constituting a multiprocessor system having a shared memory and a device capable of accessing the shared memory are provided with a specific memory address. Is guaranteed by the bus snoop method outside the processor and as a single device so that the latest data corresponding to the data can be accessed.

According to a second aspect of the present invention, there is provided a cache memory control device, wherein each processor constituting a multiprocessor system having a shared memory and a device capable of accessing the shared memory are provided with the latest data corresponding to a specific memory address. In order to perform the guarantee for accessing the shared memory by the bus snoop method, in what state the cache memory of each processor holds the data in the shared memory, corresponding to the processor, and
It is characterized in that the cache memory is held in cache line units.

According to a third aspect of the present invention, there is provided a cache memory control device in a multiprocessor system having a shared memory, wherein data of any address in the shared memory is stored in the cache memory of each processor. A processor cache tag table for holding address and tag information indicating in what state it is held in cache line units, and a memory access request when a memory access request is issued from the processor and a device under the I / O bus A cache hit detection circuit for determining from the processor cache tag table whether or not cache matching processing is required for the data of the address to be performed, and cache matching processing is required based on the result of the determination; If the relevant To instruct the cache control circuit in the processor to perform cache matching processing in units of cache lines, and to update the processor cache tag table when the internal state of the cache is changed by each processor. A cache control circuit for designating a corresponding cache line address.

More specifically, in the cache memory control device according to the present invention, the cache control circuit and the cache control circuit in the processor are connected by a cache control signal line including an address signal line of the cache line. A protocol for storing an address and data in a cache memory is the same as a protocol for storing an address in the processor cache tag table.

More specifically, in the cache memory control device according to the present invention, the cache control circuit and the cache control circuit in the processor are provided in a system bus connecting the processor, the shared memory, and the cache memory control device. Are connected by data signal lines.

More specifically, the cache memory control device of the present invention is inserted between a system bus to which each processor and the shared memory are connected and an input / output bus to which the device is connected, and has a DMA control function and It is characterized by comprising a system bus-I / O bus bridge having a memory control function.

The cache memory control device of the present invention comprises:
Specifically, multi-processors with shared memory
In the system, as a means for guaranteeing cache coherency, in a system bus-I / O bus bridge, an internal cache of each processor stores which address data in a shared memory is held in what state. A table (35 in FIG. 1) for holding the indicated address and tag information in cache line units for each processor.
0, 351), and when the memory access request from the processor and the agent under the I / O bus is made, it is determined from the above table whether or not the data of the address to be accessed requires the cache matching process. The determination means (360 in FIG. 1) and the cache control circuit of the corresponding processor are instructed to perform the cache matching process in units of cache lines only when the cache matching process is necessary, and the state of the cache internal by each processor. Is changed, the corresponding cache line
Communication means designated by the address (330 and 18 in FIG. 1)
0, 280), unnecessary snooping operation by each processor is eliminated, and the performance of the system is improved.

According to the present invention, in the system bus-I / O bus bridge, address and tag information indicating which address data on the shared memory is held in the internal cache of each processor and in what state. Is held for each processor in a cache line unit, and when a memory access request is made from the processor and an agent (device) under the I / O bus, cache matching processing is required for data at an address to be accessed. The system bus-I / O bus bridge independently determines whether or not it is, and gives an instruction to the corresponding processor only when cache matching processing is necessary. Therefore, the overhead due to the bus snooping operation of each processor. System to eliminate cache and maintain cache coherency It is a reduction of those to be alleviated.

Further, since the address and the tag indicating the data state are stored not in the shared memory but in the cache line unit of the cache memory,
The cache coherency guarantee function can be realized with a small amount of hardware.

[0021]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a multi-processor system to which a cache memory control device according to an embodiment of the present invention is applied. This multi-processor system includes processors 100-20.
0, a system bus I / O bus bridge 300, a shared memory 400, a system bus 401, an I / O bus 402, and devices 403 to 405. Referring to FIG.
0 and the shared memory 400 are connected to the system bus 401 and the devices 403 to 4 under the I / O bus 402.
The system bus-I / O bus bridge 300 that connects and controls the I / O bus 402 to which the H.05 is connected is a cache memory control device of the present invention. The system bus-I / O bus bridge 300 also performs DMA control and memory control for the shared memory 400.

The processor 100 includes a CPU core 110,
Cache memory 12 controlled by write-back method
0, a cache control circuit 130 for controlling an address signal line, a data signal line, a control signal line and the like input / output to / from the cache memory 120, and a bus interface circuit 14 for controlling an interface with the system bus 401.
0. The cache memory 120 includes an address section for storing an address of each line, a data section for storing data of each line, and a state section for storing a caching state value of each line. This state part is “Invalid”, “Shared (Share)
d) "and" Dirty "can be stored. The initial value of the state part is “invalid”.
The other processors 200 and the like have the same configuration as the processor 100, and the components of the processor 200 and the like are also the same as the corresponding components of the processor 100.

System bus-I / O bus bridge 3
00 denotes a cache in the processors 100 to 200.
In order to hold copies of the address portion and the tag portion of the memories 120 to 220, the same number of processor cache tag tables 350 to 350 as the number of processors having the cache memories constituting the multi-processor system are used.
351. FIG. 1 shows only processor cache tag tables 350 and 351 corresponding to the processors 100 and 200 in order to avoid complication of the drawing. .

The protocol for storing an address and data in a specific line of the cache memory depends on the processor or the system. In this embodiment, the processor 100 and the system bus-I / O bus
Bridge 300, processor 200 and system bus
In order to control the cache memory using the cache line address between the I / O bus bridges 300, when the processor 100, 200 stores addresses and data in the cache memories 120, 220, The protocol and the protocol for storing the corresponding address in the processor cache tag table 350 and the processor cache tag table 351 need to be the same, and correspond to the cache line of the processor having the same line address. The line of the processor cache tag table guarantees that the same address is always stored.

System bus-I / O bus bridge 3
00 is a memory controller 320 that controls the shared memory 400 connected to the system bus 401;
Devices 403 to 4 connected to I / O bus 402
Controller 310 for controlling the H.05, input / output buffers 311 and 321, and a command for storing a transaction command on the system bus 401.
A register 322, an address register 323 for storing an address, a data register 324 for storing data, a command register 312 for storing a command of a transaction on the I / O bus 402, and an address for storing Address register 313, a data register 314 storing data, a system bus arbitration circuit 370 for controlling arbitration of the system bus 401, a cache memory of the processors 100 and 200 and a system bus I / O. A cache control circuit 33 for controlling the processor cache tag tables 350 and 351 of the O bus bridge 300
0, processor 100, processor 200 and I /
Memory read / write transactions from the devices 403 to 405 under the O bus 402
A cache hit detection circuit 360 that hits the cache tag tables 350 and 351 and determines whether or not cache matching processing is necessary.

The shared memory 400 includes a system bus 401
Connected to the processor 100, the processor 200, and the devices 403 to 405 under the I / O bus 402, which are requested on the system bus 401 via the system bus-I / O bus bridge 300. A storage device that can respond to access and memory write access.

System bus 401 and I / O bus 4
Reference numeral 02 denotes a bus including control signal lines such as an address signal line, a data signal line, a command signal line, and an arbitration signal line for allowing the connected devices to access each other. Also, for the cache matching process, the cache control circuits 130, 2 of each processor 100, 200
The cache control circuit 330 of the system bus-I / O bus bridge 300 is connected to the cache control signal lines 180 and 280. Cache control signal line 1
Numerals 80 and 280 are composed of a cache line address signal line and a control signal line, and are connected point-to-point.

Next, the cache memories 120 and 220
The following describes three state values that can be stored by the state unit. One of the status values "Invalid"
Indicates that the address portion and the data portion of the cache line are invalid, that is, the line does not have a copy of the shared memory 400. Another state value "Shared" indicates that a copy of the shared memory 400 exists in the cache line, and a copy may exist in the cache memory of a plurality of processors.
This indicates that the data and the contents of the shared memory 400 match. The remaining state value "Change (Dirty)" indicates that a copy of the shared memory 400 exists only in the cache line and the content is updated.

Next, the operation of the embodiment shown in FIG.
This will be described with reference to the drawings.

First, the CPU core 1 of the processor 100
Consider a case where a memory read access is performed from 10 to a specific address of the shared memory 400. At this time, C
The PU core 110 instructs the cache control circuit 130 to check whether or not the data of the corresponding address is stored in the cache memory 120.

(Case 1) If there is data to be read in the cache memory 120 and the corresponding status part indicates "shared" or "change", that is, if a cache hit occurs, the cache memory 12
The data in 0 is passed to the CPU core 110, and the memory read access ends.

(Case 2) When the data to be read does not exist in the cache memory 120, or when it exists but the corresponding status part indicates "invalid", that is, when a cache miss occurs. The CPU core 110 drives the bus request signal line 181 to the system bus arbitration circuit 370 of the system bus-I / O bus bridge 300 via the bus interface circuit 140 to use the system bus 401. Claim rights. If no other processor is using the system bus 401, the system bus arbitration circuit 370 drives the bus enable signal line 182 to the bus interface circuit 140 of the processor 100 after appropriate arbitration, and -The use of the bus 401 is permitted.

The processor core 110 granted the right to use the system bus drives the memory read address on the address signal line of the system bus 401 and the memory read command on the command signal line to read the memory read. Start. The system bus-I / O bus bridge 300 stores addresses driven by the processor 100,
The command is fetched into the address register 323 and the command register 322, and it is determined whether or not the corresponding address is stored in the processor cache tag table 351 corresponding to the processor other than the processor 100 which has started the memory read. Detection circuit 3
Check at 60.

(Case 2-1) In one of the processor cache tag tables corresponding to other processors,
If the corresponding address is stored and the status part indicates "change", the system bus-I / O bus.
The cache hit detection circuit 360 of the bridge 300
It determines that the cache matching process is necessary, and instructs the cache control circuit of the corresponding processor to perform the cache matching process via the cache control circuit 330 (see FIG. 2).

The following description is based on the assumption that a memory read access initiated by the processor 100 hits the processor cache tag table 351 corresponding to the processor 200. The cache control circuit 330 of the system bus-I / O bus bridge 300 uses the cache control signal line 280 to send the line where the memory read address started by the processor 100 hits to the cache control circuit 230 of the processor 200. Shared memory 4
00, and instructs the status part to be “shared”.

The cache control circuit 230 of the processor 200 receiving the instruction sets the bus interface circuit 240
, The data of the line including the corresponding address is driven to the data signal line of the system bus 401, and the status part of the corresponding line is changed to “shared”.

System bus-I / O bus bridge 3
00 instructs via the memory controller 320 to fetch the data into the shared memory 400. At the same time, the processor 100 fetches the data driven on the system bus 401 into the cache memory 120 via the bus interface circuit 140 as data for the memory read, and the cache control circuit 130
Makes its status part "shared". Further, the data is passed to the CPU core 110, and the memory read access is terminated.

System bus-I / O bus bridge 3
00 updates the state part of the line including the corresponding address in the cache tag table 351 corresponding to the processor 200 from “change” to “shared”, and stores the cache of the processor 100 in the processor cache tag table 350. Using the same protocol as the cache memory 120 of the processor 100.
The address of the memory read in the address register 323 is stored at the same line address as the memory read address and the line address at which the data is stored, and "shared" is stored in the information section.

(Case 2-2) When the corresponding address is not stored in the processor cache tag table 351 corresponding to another processor, or is stored, the state part is “shared” or If it indicates “invalid”, the cache hit detection circuit 360 of the system bus-I / O bus bridge 300 determines that the cache matching process is unnecessary, and sends the cache memory to the shared memory 400 via the memory controller 320. Instruct a memory read (see FIG. 3).

Upon receiving the instruction, the shared memory 400 stores the data corresponding to the memory read address in the system bus 40.
Drive to one data signal line.

The processor 100 includes a system bus 401
The data driven above is taken into the cache memory 120 via the bus interface circuit 140 as data for the memory read, and the CPU core 11
0 to end the memory read access.

System bus-I / O bus bridge 3
00 stores the memory read address and data of the cache memory 120 of the processor 100 in the processor cache tag table 350 corresponding to the processor 100 using the same protocol as the cache storage protocol of the processor 100. Then, the address of the memory read in the address register 323 is stored in the same line address as the specified line address, and “shared” is stored in the status section.

Second, the CPU core 1 of the processor 100
Consider a case where a memory write access is performed from 10 to a specific address of the shared memory 400. At this time, C
The PU core 110 instructs the cache control circuit 130 to check whether or not the data of the corresponding address is stored in the cache memory 120.

(Case 3) If there is data to be written in the cache memory 120 and the corresponding status part indicates “change”, the CPU core 110 writes data to the data in the cache memory 120. Then, the memory write access ends.

(Case 4) If there is data to be written in the cache memory 120 and the corresponding status part indicates “shared”, the CPU core 110 writes to the data in the cache memory 120. The cache control unit 130 updates the status part to “change” and, at the same time, updates the status part of the cache line address hit by the memory write access to “change”. The signal line 180 is used to instruct the cache control circuit 330 of the system bus-I / O bus bridge 300.

The cache control circuit 330 of the system bus-I / O bus bridge 300 that has received the instruction updates the status part of the cache line address in the processor cache tag table 350 to “change”. ,
It is checked whether another processor cache tag table has the same address as the address stored in the address portion of the cache line address.

(Case 4-1) If the memory write address exists in another processor cache tag table and its status part indicates "shared", it is determined that cache matching processing is necessary. , And instructs the cache control circuit of the corresponding processor to perform the cache matching process. Hereinafter, the memory write access initiated by the processor 100 hits the cache memory 120 of the processor 100, and a copy of the data at the same address also exists in the cache memory 220 of the processor 200 in a “shared” state. It will be described as.

System bus-I / O bus bridge 3
The cache control circuit 330 of the processor 200 updates the status portion of the line where the memory write address hits in the processor cache tag table 351 to “invalid” and uses the cache control signal line 280 to execute the processor 200 Of the line where the memory write address hits is updated to "invalid". The cache control circuit 230 of the processor 200 that has received the instruction updates the control unit of the corresponding cache line address to “invalid” (see FIG. 4).

(Case 4-2) When the memory write address does not exist in another processor cache tag table, or when the memory write address exists but its status part indicates "invalid", the system bus -I / O bus
The cache hit detection circuit 360 of the bridge 300 determines that the cache matching process is unnecessary, and ends the process (see FIG. 5).

(Case 5) If the data to be written does not exist in the cache memory 120, or if it exists but the corresponding status part indicates "invalid",
That is, when a cache miss occurs, the CPU core 110 sends the bus request signal line 181 to the system bus arbitration circuit 370 of the system bus-I / O bus bridge 300 via the bus interface circuit 140. Drives and requests the right to use system bus 401. If no other processor is using the system bus 401, the system bus arbitration circuit 370 drives the bus enable signal line 182 to the bus interface circuit 140 of the processor 100 after appropriate arbitration, and The use of the bus 401 is permitted.

The processor core 110 to which the right to use the system bus has been granted the address signal line of the system bus 401 to perform a cache fill (filling the cache memory with data read from the shared memory 400). And the read command on the command signal line on the premise of writing.
Start reading on the premise of writing. Driving a read command on the premise of writing is not merely a read operation, but the processor 100 rewrites the cache memory 120 with read data. For example, the state part is set to “invalid”). The system bus-I / O bus bridge 300 captures the address and command driven by the processor 100 into the address register 323 and the command register 322, and stores the address and command in the processor cache tag table 351 corresponding to processors other than the processor 100. The cache hit detection circuit 360 checks whether or not the corresponding address is stored.

(Case 5-1) In one of the processor cache tag tables corresponding to other processors,
If the corresponding address is stored and the status part indicates "change", the system bus-I / O bus.
The cache hit detection circuit 360 of the bridge 300
It is determined that the cache matching processing is necessary, and the cache matching circuit is instructed via the cache control circuit 330 to the cache control circuit of the corresponding processor. Hereinafter, a read access on the premise of a write started by the processor 100 is performed by a processor corresponding to the processor 200.
It is assumed that a hit has occurred in the cache tag table 351.

System bus-I / O bus bridge 3
The cache control circuit 330 of 00 uses the cache control signal 280 to cause the cache control circuit 230 of the processor 200 to hit the line where the read address based on the write started by the processor 100 hits, that is, the “changed” state. The cache line written to the shared memory 400 is instructed to make its status part “invalid”.

Upon receiving the instruction, the cache control circuit 230 of the processor 200 sets the status section of the corresponding cache line to “invalid” and, at the same time, transfers the data of the line including the corresponding address to the system via the bus interface circuit 240. -Drive to the data signal line of the bus 401.

System bus-I / O bus bridge 3
00 instructs via the memory controller 320 to fetch the data into the shared memory 400. At the same time, the processor 100 captures the data driven on the system bus 401 into the cache memory 120 via the bus interface circuit 140 as data for a read on the premise of writing, and the CPU core 11
0 executes writing to data in the cache memory 120. At the same time, the cache control circuit 130 sets the status part to "change" and ends the memory write access.

System bus-I / O bus bridge 3
00 updates the state part of the line including the corresponding address in the processor cache tag table 351 corresponding to the processor 200 from “change” to “invalid”, and stores the state part in the processor cache tag table 350 corresponding to the processor 100. Using the same protocol as the cache storage protocol of the processor 100, that is, the same address as the line address where the read address and the data stored in the cache memory 120 of the processor 100 are stored, The address of the memory read in the register 323 is stored, and “change” is stored in the status section (see FIG. 6).

(Case 5-2) In one of the processor cache tag tables corresponding to other processors,
If the corresponding address is stored and the status part indicates "shared", the system bus-I / O bus.
The cache hit detection circuit 360 of the bridge 300
It is determined that the cache matching processing is necessary, and the cache matching circuit is instructed via the cache control circuit 330 to the cache control circuit of the corresponding processor. Hereinafter, the read access based on the write started by the processor 100 is performed by the processor 2 corresponding to the processor 200.
It is assumed that a hit has occurred in the 00 cache tag table 351.

System bus-I / O bus bridge 3
00 uses the cache control signal 280 via the cache control circuit 330 to cause the cache control circuit 230 of the processor 200 to include a cache address including a read address based on a write started by the processor 100.
Instructs the state part of the line to be "invalid". At the same time, the shared memory 40
0 is designated for memory read.

The cache control circuit 230 of the processor 200 that has received the instruction sets the status part of the relevant cache line to “invalid”. Also, the shared memory 40 receiving the instruction
0 drives the data corresponding to the memory read address to the data signal line of the system bus 401.

The processor 100 includes a system bus 40
The bus interface circuit 1 uses the data driven on the bus 1 as data for reading on the premise of writing.
40 into the cache memory 120 via
The CPU core 110 executes a write on data in the cache memory 120. At the same time, the cache control circuit 130 sets the status part to "change" and ends the memory write access.

System bus-I / O bus bridge 3
00 updates the status portion of the line where the corresponding address hits in the processor cache tag table 351 corresponding to the processor 200 from “shared” to “invalid”, and updates the processor cache cache corresponding to the processor 100.
The tag table 350 uses the same protocol as the cache storage protocol of the processor 100, that is, the same read address as the write address of the cache memory 120 of the processor 100 and the same line address as the line address where the data is stored. The address of the memory read in the address register 323 is stored in the address, and “change” is stored in the status section (see FIG. 7).

(Case 5-3) If the corresponding address is not stored in any of the processor cache tag tables 351 corresponding to other processors, the cache of the system bus-I / O bus bridge 300 is used. The hit detection circuit 360 determines that the cache matching process is unnecessary, and instructs the shared memory 400 via the memory controller 320 to perform a memory read.

Upon receiving the instruction, shared memory 400 transfers the data corresponding to the memory read address to system bus 40.
Drive to one data signal line.

The processor 100 is connected to the system bus 40
The bus interface circuit 1 uses the data driven on the bus 1 as data for reading on the premise of writing.
40 into the cache memory 120 via
The CPU core 110 executes a write on data in the cache memory 120. At the same time, the cache control circuit 130 sets the status part to "change" and ends the memory write access.

System bus-I / O bus bridge 3
00 is the processor cache tag table 35
0, using the same protocol as the cache storage protocol of processor 100, ie, processor 100
The address register 32 is stored in the same line address as the read address and the line address where the data is stored on the assumption that the data is stored in the cache memory 120 of FIG.
3 is stored, and "change" is stored in the status section (see FIG. 8).

Third, a case where the cache memory of the processor is cast out (sweep from the cache memory to the shared memory 400) will be described.
Hereinafter, description will be made assuming that a specific line of the cache memory 120 of the processor 100 is cast out.

The CPU core 110 drives the bus request signal line 181 to the system bus arbitration circuit 370 of the system bus-I / O bus bridge 300 via the bus interface circuit 140 to drive the system bus. Request the right to use the bus 401. If no other processor is using the system bus 401, the system bus arbitration circuit 370, after making the appropriate arbitrations, returns the bus interface circuit 14 of the processor 100.
For 0, the bus permission signal line 182 is driven and the use of the system bus 401 is permitted. The processor 100 permitted to use the system bus starts the castout by driving the castout address to the address signal line of the system bus 401 and the castout command to the command signal line.

System bus-I / O bus bridge 3
00 fetches the address and command driven by the processor 100 into the address register 323 and the command register 322, and sets the status part of the line of the processor 100 cache tag table 351 where the corresponding address is stored to "shared". I do.

Table 1 briefly summarizes all the operations described above.

As described above, in this embodiment, the management of the cache memory, which was conventionally performed individually by each processor, is collectively performed by the system bus-I / O bus bridge 300, and when necessary, In this configuration, the processor other than the one that started the memory read or memory write interrupts the currently executing process and performs a bus snooping operation to match the caches as in the past. There is no need to uselessly determine whether or not the conversion process is necessary.

Next, a second embodiment of the present invention will be described.

In the above-described first embodiment, the processor 100 and the system bus-I / O bus bridge 30
0, and processor 200 and system bus-I / O
Since the cache memory is controlled using the cache line address between the bus bridges 300, a protocol for storing addresses and data in the cache memory in the processor and a system bus I / O bus bridge It is necessary that the protocol used to store the relevant address in the processor cache tag table 350 and the processor cache tag table 351 be the same, and the same line
Address cache line and corresponding processor
It was necessary to ensure that the cache tag table line always stored the same address.

In the present embodiment, the cache memory address is used as the cache line address in the first embodiment, but this is not used, and the address signal of the system bus 401 is not used. It is indicated by the memory address on the line. In this case, at the time of cache control, each of the processors 100 and 200 and the shared memory 400
Arbitration of the system bus 401 shared by
Although there is a problem that the data transfer performance of the system bus 401 is slightly lowered, the protocol for storing addresses and data in the cache memory must be the same between the processor and the system bus-I / O bus bridge 300. In addition, since the address signal line of the system bus 401 is used, the address signal is transmitted from the cache control signal line connecting the processor and the system bus-I / O bus bridge 300 in a point-to-point manner. Since lines can be deleted, the number of lines can be significantly reduced.

[0075]

A first effect of the present invention is that the load due to the bus snooping operation of each processor in a multiprocessor system can be reduced, and the performance of the entire system can be improved.
The reason for this is that each processor has a function that guarantees the coherency of the cache that each processor had individually,
By concentrating on the bus-I / O bus bridge, the system bus-I / O bus bridge alone determines whether or not cache matching processing is necessary for the data of the address to be accessed. This is because the determination is made and an instruction is given to the corresponding processor only when cache matching processing is necessary.

The second effect is that the function of ensuring the coherency of the cache is provided by the system bus-I / O.
This means that the bus bridge can be implemented with a small hardware configuration. The reason is,
The address and tag information indicating which address data in the shared memory is held in what state in the internal cache of each processor is not stored in the shared memory, but in units of a cache memory and a cache line for each processor. This is because they are held by

For example, assuming that the address signal line of the system bus 401 is 32 bits and the caching state is managed by 2 bits, the shared memory size is 25 bits.
For a system having 6 Mbytes and a processor cache line size of 32 bytes, Japanese Patent Application Laid-Open No. H10-553
While the state storage means disclosed in Japanese Patent Application Publication No. 14 requires a capacity of as much as 16 Mbits, according to the present invention, it can be realized with a small storage capacity of only 30 Kbits / processor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of case 2-1 of the embodiment shown in FIG. 1;

FIG. 3 is an operation explanatory diagram of case 2-2 of the embodiment shown in FIG. 1;

FIG. 4 is an operation explanatory diagram of case 4-1 of the embodiment shown in FIG. 1;

FIG. 5 is an operation explanatory diagram of case 4-2 of the embodiment shown in FIG. 1;

FIG. 6 is an operation explanatory diagram of case 5-1 of the embodiment shown in FIG. 1;

FIG. 7 is an operation explanatory diagram of case 5-2 of the embodiment shown in FIG. 1;

FIG. 8 is an operation explanatory diagram of case 5-3 of the embodiment shown in FIG. 1;

FIG. 9 is a view showing an operation list of each case of the embodiment shown in FIG. 1;

FIG. 10 is a block diagram showing a conventional example.

[Explanation of symbols]

100, 200 Processor 110, 210 CPU core 120, 220 Cache memory 130, 230 Cache control circuit 140, 240 Bus interface circuit 300 System bus-I / O bus bridge 310 DMA controller 311 I / O buffer 312 DMA command Register 313 DMA address register 314 DMA data register 320 Memory controller 321 I / O buffer 322 Command register 323 Address register 324 Data register 330 Cache control circuit 350, 351 Processor cache tag
Table 360 Cache hit detection circuit 370 System bus arbitration circuit 400 Shared memory 401 System bus 402 I / O bus 403-405 Device

Claims (6)

[Claims] An assurance is provided outside the processor that each processor constituting a multiprocessor system having a shared memory and a device capable of accessing the shared memory can access latest data corresponding to a specific memory address. A cache memory control device according to the bus snoop method, wherein the control is performed as a single device. 2. A bus snoop method that guarantees that each processor constituting a multiprocessor system having a shared memory and a device that can access the shared memory can access the latest data corresponding to a specific memory address. In order to perform the above, it is required that the state of the cache memory of each processor holding the data in the shared memory be held for each of the processors and in units of cache lines of the cache memory. Characteristic cache memory control device. 3. A cache memory control device in a multiprocessor system provided with a shared memory, wherein the cache memory of each processor indicates which address data in the shared memory is held in what state. A processor cache tag table for holding address and tag information on a cache line basis, and a cache for data of an address to be accessed when a memory access request is made from the processor and a device under the I / O bus A cache hit detection circuit for judging from the processor cache tag table whether or not the coincidence processing is necessary; and a cache control circuit in the corresponding processor only when the cache coincidence processing is required based on the result of the judgment. Against The cache matching process is instructed on a cache line basis, and when the internal state of the cache is changed by each processor, the processor cache tag
A cache control circuit for instructing a corresponding cache line address to update a table. 4. The cache control circuit and a cache control circuit in the processor are connected by a cache control signal line including an address signal line of the cache line, and store addresses and data in the cache memory. 4. The cache memory control device according to claim 3, wherein a protocol for storing an address in the processor cache tag table is the same as a protocol for storing the address in the processor cache tag table. 5. The cache control circuit and a cache control circuit in the processor are connected by a data signal line in a system bus connecting the processor, the shared memory and the cache memory control device. The cache memory control device according to claim 3, wherein: 6. A system bus I / O which is inserted between a system bus to which each processor and the shared memory is connected and an input / output bus to which the device is connected, and has both a DMA control function and a memory control function. 6. The cache memory control device according to claim 1, comprising a bus bridge.