KR0164919B1 - Multi-processor having directory cache in memory module - Google Patents

Abstract

The present invention relates to a multiprocessor comprising a directory cache in a memory module, the multiprocessor comprising a directory cache in a memory module comprising a system bus operating under a separate transaction protocol, at least one memory module coupled to the system bus, In a shared memory multiprocessor having a plurality of processor modules each coupled to the system bus, the memory module separately includes a directory and a directory cache that provides faster access time than the memory, each block stored in the memory. Maintain state information in the directory cache that specifies whether the block of memory is valid. Thus, multiple processors including directory cache in the memory module of the present invention alleviate bottlenecks in memory modules and improve system performance when running write-invalidate cache coherency protocols due to fast memory access. have.

Description

Multiple processors with directory cache in memory modules

1 illustrates a typical shared memory multiprocessor system.

2 illustrates a typical shared memory multiprocessor system in which each processor module includes a cache.

3 illustrates a conventional shared memory multiprocessor, illustrating a problem when a write-invalidate cache coherency scheme is used under a multiprocessor environment using a separate transaction bus.

4 is a timing diagram illustrating a problem when a write-invalidate cache coherency maintenance scheme is used in a multiprocessor environment using a separate transaction bus.

5 illustrates a shared memory multiprocessor system including an improved memory module of the present invention.

6 illustrates the contents of the directory cache of the present invention.

7 illustrates, in block diagram form, an improved memory module of the present invention.

8 illustrates memory contents of a Synapse N + 1 multiprocessor.

9 illustrates a shared memory multiprocessor system in which an improved memory module of the present invention and a conventional memory module are mixed.

* Explanation of symbols for main parts of the drawings

100,100 ': memory module 200,200': processor module

300; Detachable transaction bus 400,400 ': processor

500, 500 ': cache 600,600': directory cache

700700 ': Memory 710: Data storage device

720: memory controller 730: memory-bus interface

740: working buffer

The present invention relates to a multiprocessor, and more particularly, to a memory module for a shared memory multiprocessor using a split transaction bus.

Shared memory multiprocessor systems are a very economical way to increase system computing power and speed, largely due to the fact that high performance microprocessors can be economically interconnected via shared memory modules and a common bus.

1 illustrates the structure of a typical shared memory multiprocessor system in which multiple processor modules are coupled with multiple shared memory modules by a common bus.

However, two fundamental problems are inherent in such a system configuration. In other words, bus contention occurs when multiple processor modules try to access a common bus at the same time, and memory contention occurs when multiple processor modules try to access a single memory module at the same time. This is it. These problems increase memory access time, which in turn reduces the execution time of multiprocessor systems.

One way to reduce access conflicts on a common bus is to allow the common bus to transmit as much information as possible without unnecessary rest. For example, a non-split transaction bus that occupies the common bus from the processor module sending an access request to the memory module over the common bus to receiving a response. Rather than using an access request transfer process and a response transfer process for a memory module, another processor module or memory module may use the common bus while not using a common bus between the access request transfer process and the response process of the memory module. The use of split transaction-bus, which enables this, can help reduce access conflicts on the common bus. A more detailed description of the separate transaction bus is described, for example, in US Pat. No. 5,067,071 to D. J. Schanin et al.

Even if the bandwidth of the common bus increases, one memory module can handle one memory access request at a time, resulting in memory conflicts that occur when multiple processor modules attempt to access one memory module at the same time. System degradation due to the present still exists. Therefore, in order to reduce common bus access collisions and memory access collisions, it is important to reduce the traffic between the processor module and the memory module as much as possible, and the processor module is a block of memory modules that the processor is expected to use frequently. The number of access requests to common buses and memory modules can be reduced by storing them in their own caches, which have a smaller capacity than memory modules but provide much faster access times. 2 illustrates a configuration of a shared memory multiprocessor system in which a cache is included in all processor modules.

However, in such shared-memory multiprocessor systems, each processor module uses its own cache, so if one processor module writes to a block stored in its own cache, the result of that write operation is different for all other processors. There is a so-called cache coherence problem that must be reflected in those blocks that are stored in their own cache in the modules. In order to solve the cache coherence problem and to reduce the number of bus and memory access requests of the processor module, various cache coherency methods have been proposed. Among these schemes, one of the most widely used schemes for shared memory multiprocessor systems with a common bus is a write-invalidate cache coherence scheme.

In this write-invalidate cache coherence scheme, the cache within the processor module maintains state information for each block stored therein, which state information is stored in at least three possible cache block states (i.e., MODIFIED, INVALID, and SHARED). Express one. The MODIFIED state means that the block has been changed most recently in the cache, but the memory module has not yet been updated. The INVALID state means that the block has been invalidated by another processor module. The SHARED state means that the block has not been altered in the cache, invalidated by another processor module, and is consistent in content with the block stored in the memory module. The cache coherence scheme generally operates as follows for a block access request from a processor in a processor module. In the following cache coherence method, block replacement selects a block to be replaced in its own cache when a cache failure occurs in a processor module, and the selected block is updated (for example, a MODIFIED state). ), It copies the block (ie, an updated copy of that block) to the corresponding memory module.

Read-hit-A cache in the processor module holds a block that has been requested to be read in the SHARED or MODIFIED state. If the cache is held in the MODIFIED state, the processor module performs a read operation on the block. .

Read-miss-if the cache in the processor module does not hold a block that has been requested to read, or has a block that has been requested to be read in an INVALID state (an invalidation cache failure) In this case, the processor module performs block replacement first and performs the following operation. Otherwise, the processor module immediately performs the following operation.

The processor module sends a broadcast read request for the block to a memory module and another processor module. If one of the other processor modules holds the requested block in the MODIFIED state, the processor module provides the block for the broadcast read request and updates the corresponding block in the memory module. If another processor module does not hold the requested block in the MODIFIED state, the memory module holding the requested block provides that block for the broadcast read request. Accordingly, the processor module receives the requested block, stores it in its own cache in the SHARED state, and performs a read operation.

Write-hit-A cache in the processor module holds a block in which a write request is made in a SHARED or MODIFIED state, and holds it in a MODIFIED state, and the processor module immediately performs a write operation on the block. do. If the cache in the processor module holds the requested block in the SHARED state, the processor module sends an invalidation request for the block to another processor module so that all other processor modules are stored in their cache. After invalidating a copy of the block, a write operation is performed on the requested block stored in its own cache, and the state of the cache block is changed to MODIFIED.

Read-miss-if the cache in the processor module does not hold a block that has been requested to write, or if a block that has been requested to hold a write requested in the INVALID state (invalid cache failure), holds that block in the cache If not, the processor module performs block replacement first and performs the following operation, otherwise it performs the next operation immediately.

The processor module sends a broadcast read with invalidation request containing the invalidation request for that block to the memory module and other processor modules so that all other processor modules can copy a copy of the requested block stored in their cache. In addition to invalidating, if one of the other processor modules holds a copy of the requested block in the MODIFIED state, the processor module provides the block for the broadcast read request containing the invalidated request. Alternatively, if neither processor module holds the requested block in the MODIFIED state, the memory module holding the requested block provides the block for the broadcast read request containing the invalidation request. Accordingly, the processor module receives the requested block, stores it in its cache in the MODIFIED state, and performs a write operation.

Various variations of the write-invalidate cache coherence protocol described above are described, for example, in Per Stenstrom's A Survey of Cash Coherence Schemes for Multiprocessors (IEE Computer, June 1990, pp. 12-24), J. Archibald and JL Baer. Coherence Protocols: Evaluation Using A Multiprocessor Simulation Model (ACM Transaction on Computer Systems, Nov. 1986, pp. 273-298).

However, typical shared memory multiprocessor systems, such as those in FIG. 2 with the conventional memory module architecture, which drive the various write-invalid cache coherence protocols described above, also perform as described below under a multiprocessor environment using a separate transaction bus. Decrease factors occur.

As described above, in the write-invalidate cache coherency maintaining scheme, the processor module reads a broadcast read request for a block when a read failure occurs, and a broadcast read including an invalidation request for the block when a write failure occurs. Send the request to a memory module and another processor module. The separate transaction bus also releases the bus between the memory access request and the corresponding response, allowing the bus to be used by other modules during that period.

In this situation, if an invalidation cache failure occurs for block X in processor module 1, and then a cache failure occurs for another block Y in processor module 2, then (one memory module and one request buffer in this memory module). processor module 1 implies a broadcast read request for block X or a broadcast read request containing an invalidation request. Processor module 2 implies a broadcast request or invalidation request for block Y. Sends one broadcast read request to a memory module and another processor module. Accordingly, the memory module starts a memory read operation for block X for a broadcast read request for block X or a broadcast read request containing an invalidation request, as shown in the example of FIG. Because a can process only one memory access request at a time, a broadcast read request for block Y or a broadcast read request containing an invalidation request is stored in the request buffer. Thus, processing a request from processor module 2 may result in the memory module completing a response to a request from processor module 1, or holding block X in the MODIFIED state (i.e., holding an updated copy of block X). Delay until the other processor module sends information to the memory module that it will provide block X on behalf of the memory module.

4 shows the operation of the case where processor module 3 holds block X in MODIFIED state for a request from processor module 1 during the above operation. Hardware Performance Analysis of Multiple Processors, Vol. 16, No. 5, pp., 399-409, September 1989.) and Encore Multimax multiprocessors (Daniel Tabak's Multiprocessors, Prentice Hall, 1990., Shanin This is illustrated using the timing diagram of the separate transaction bus used in US Pat. No. 5,067,071, et al. As mentioned above, since the memory module does not know what state the requested block X is stored in the cache of other processor modules, the memory access operation is performed once for a broadcast read request or a broadcast read request including an invalidation request. If you later send a snooping result that processor module 3, which is storing block X in an updated state, will provide that block, it stops that task in process and the next request in block 4, the request for block Y, Processing will begin.

However, one of the other processor modules holds block X in the MODIFIED state for a broadcast read request for a block X to which the memory module has been sent or a broadcast read request containing an invalidation request, and the processor module has a memory module. If it can be known in advance in step 1 of FIG. 4 that block X is provided instead of the memory module, the memory module performs processing for a broadcast read request for block Y or a broadcast read request containing an invalidation request. You can start without delay in order to reduce the actual memory access time.

It is therefore a primary object of the present invention to provide an improved memory module for a multiprocessor system using a separate transaction bus, thereby maintaining cache coherency and reducing the actual memory access time.

A multiprocessor comprising a directory cache in a memory module according to the present invention for achieving the above object is a system bus operating under a separate transaction protocol, at least one memory module coupled to the system bus, and each coupled to the system bus. In a shared memory multiprocessor having a plurality of processor modules, the memory module includes a directory and a directory cache that provides faster access time than the memory, and the memory block is valid for each block stored in the memory. State information specifying whether or not is kept in the directory cache.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 5, an exemplary block diagram of a shared memory multiprocessor using the improved memory module of the present invention is shown. As shown, at least one memory module 100 and at least two processor modules 200 and 200 ′ are coupled to a shared memory multiprocessor by a separate transaction bus 300. Each processor module 200 or 200 'includes a processor 400 or 400' and a cache 500 or 500 ', and the improved memory module 100 or 100' of the present invention is a directory cache 600 or 600 '. ) And memory (700 or 700 ').

In describing the embodiments of the present invention, since the memory modules 100 or 100 'have the same structure and function, only the memory module 100 will be described in detail below.

In the memory 700 and the cache 500 or 500 ', data is divided into blocks of the same size and stored. Access to a block stored in the cache 500 or 500 'is initiated by passing the block's physical address along with a request for access to the block from the processor 400 or 400'. For each cache block stored (500 or 500 '), cache block state information indicating the current state of the block (e.g., MODIFIED, SHARED, INVALID status, etc.) is maintained.

As described above, when an invalidation cache failure for a block occurs in one processor module 200 in the write-invalid cache coherence maintaining scheme, a broadcast read request including a broadcast read request or an invalidation request for the block is generated. The memory module 100 and other processor modules 200 'are transmitted to the conventional memory module 100 in a state in which the block is updated to one of the other processor modules 200' in response to the request. For example, it is not known until another processor module 200 'tells whether it is stored in a MODIFIED state, so in most cases one of the processor modules 200' In spite of providing it, it will start processing the request, which increases the memory access latency. However, as in the present invention, whether the block is valid for each block stored in the memory 700, that is, any one of the processor modules 200, 200 'updates the block. The directory cache 600, which provides faster access time than the memory 700, whether or not it is being stored in a closed state (e.g., MODIFIED state), thereby accessing the directory cache 600 for the transmitted request By deciding in advance whether or not to start memory access for a server, unnecessary memory access can be eliminated to reduce the actual memory access time.

In order to achieve this improvement, the present invention maintains a separate directory cache 600 in the memory module 100 that provides faster access time than the memory 700 and the memory 700, the directory cache 600 is As shown in FIG. 6, for each memory block stored in the memory 700, whether the block is valid regardless of the number of processor modules 200 and 200 ', that is, the processor module 200 or 200' Stores two pieces of memory block state information that indicate whether it is saving in an updated state (eg, MODIFIED state), for example one of the DIRTY state and the CLEAN state.

In the DIRTY state, the corresponding memory block stored in the memory 700 is not valid and is stored in the cache 500 or 500 'in the processor module 200 or 200' as an updated state (for example, a MODIFIED state). It means that there is. The CLEAN state means that the non-DIRTY state, that is, the corresponding memory block stored in memory 700, is probably valid.

Referring back to FIG. 5 again, communication between major elements of the shared memory multiprocessor occurs on system 300. System bus 300 includes three buses, an address bus, a data bus, and a control bus, and uses a separate transaction protocol as described above. The control bus may also include COMMAND, M-INHIBIT lines.

The COMMAMD line transmits instructions including a broadcast read request, a broadcast read request with invalidation, an invalidation request, and a block eviction request between the memory module 100 and the processor module 200, 200 ′.

The M-INHIBIT line is updated by another processor module 200 'for a broadcast read request that contains a broadcast read request or invalidation request for a block sent by the processor module 200 where the cache failure occurred. The memory module 100 is used to inform the memory module 100 whether the memory module 100 is stored in the stored state (eg, the MODIFIED state). That is, if there is a processor module 200 'that stores the block in an updated state, the processor module 200' applies the M-INHIBIT signal value through the M-INHIBIT line. Meanwhile, the memory module 100 may stop the processing of the read request when the M-INHIBIT signal is applied by checking the M-INHIBIT line.

Referring now to FIG. 7, an embodiment of a memory module 100 according to an embodiment of the present invention is shown in block diagram form. As shown, the memory module 100 stores a data storage device 710 for storing each memory block: for each of the stored memory blocks, for storing one of at least two memory block states as described above. Directory cache 600: Memory controller 720: Memory-bus interface 730 that connects memory 700 and directory cache 600 to system bus 300 under the control of memory controller 720: System bus ( A job buffer 740 is temporarily stored prior to processing the request sent via 300 or temporarily storing a response for output to the system 300 bus.

When a processor module 200 or 200 ′ transmits a broadcast read request, a broadcast read request, an invalidation request, a block eviction request, etc., including an invalidation request for a block, through the system bus 300, a memory controller The snooping management unit 720 checks / modifies the state information in the directory cache 600 for the block using the physical address transmitted with the request through the memory-bus interface 730, and the type and the type of request. Status information from the directory cache 600 for the block determines whether to ignore the request. That is, if the request is a broadcast read request containing a broadcast read request or an invalidation request and the status information from the directory cache 600 for the block is DIRTY, the snooping management unit of the memory controller 720 may request the request. In this case, the operation is performed in the same manner as that of the existing memory module, and the request is stored in the work buffer 740.

When a request sent from the processor module 200 or 200 'is stored in the job buffer 740, the memory manager of the memory controller 720 accesses the job buffer 740, interprets the request to be processed, and requests the request. The overall address of the data storage device 710, such as performing a memory access to the block using the physical address of the control and synchronization. The memory controller 720 also checks the M-INHIBIT line and the like for the request being accessed in the memory or the request stored in the working buffer and ignores the request. In addition, in order to transmit the requested block to the processor module 200 through the system bus 300, the corresponding block received from the data storage device 710 is stored in the working buffer 740, and the memory-bus interface 730 Transmits the block to the requested processor module through the controller.

Meanwhile, a concept similar to the present invention is Synapse N + 1 multiprocessor (Tightly Coupled Multiprocessor System Speeds Memory-access Times of Steven J. Frank, Electronics, Jan. 1984, James Archibald et al. Cache Coherence Protocols: Evaluation Using A Multiprocessor Simulation Model , ACM Trans.on Computer System, Vol. 4, No. 4, pp 273-298, Nov. 1986), Synapse N + 1 multiprocessor has many differences from the present invention as described below. First, unlike the present invention, as shown in FIG. 8, the Synapse N + 1 multiprocessor maintains one bit of tag bit in each memory block without maintaining the directory cache 600 separately, thereby providing information on the above-described DIRTY or CLEAN. Save it. Therefore, the present invention determines whether to start the memory access to the corresponding block for the transmitted request by accessing the fast directory cache 600 to prevent unnecessary memory access, whereas the system is different from the present invention. In this case, memory access is started unconditionally to determine whether to transmit the accessed block to the requesting processor module according to the tag bit information of the accessed block. In other words, the present invention differs significantly from the Synapse N + 1 multiprocessor in terms of the structure of the memory module and the method, purpose and operation of retaining the DIRTY / CLEAN bits. In addition, the present invention converts / maintains directory cache 600 state information for a broadcast read request, invalidation request, and block eviction request including an invalidation request or an invalidation request as described below. Does not use an invalidation request, and converts the tag bits only for broadcast read requests, broadcast read requests, and block egress requests that contain invalidation requests.

Hereinafter, an exemplary operation of the memory module 100 including the directory cache 600 according to an embodiment of the present invention maintains three cache block state information, namely, a MODIFIED state, an INVALID state, and a SHARED state. Each case of the read hit, read failure, write hit, and write failure of the write-invalidate cache coherency maintaining scheme will be described. In each case it is assumed that the processor 400 in the processor module 200 of FIG. 4 has made a request to access a block with the cache 500. In addition, in the following embodiments, block replacement means that the processor module 200 selects a block to be replaced in its own cache 500 when a cache failure occurs, and the selected block is updated. In other words, if it exists in the MODIFIED state, the block (ie, an updated copy of the block) is copied to the corresponding memory module through a block eject request. At this time, the memory module 100 of the present invention converts the state information in the directory cache 600 for the block to the CLEAN state in response to the block eviction request, and updates the corresponding memory block.

Read hit-When the cache 500 in the processor module 200 holds a block that has been requested to be read in the SHARED or MODIFIED state, the processor module 200 does not transmit any request to the memory module 100. Read the block.

Read failure-The cache 500 in the processor module 200 does not hold a block that has been requested to read, or holds a block that has been requested to read in an INVALID state, and does not hold the block in the cache 500. If not, the processor module 200 performs block replacement first and performs the following operation, otherwise, immediately performs the next operation.

The processor module 200 transmits a broadcast read request for the block to the memory module 100 and the other processor module 200 ′. At this time, the processor module 200 ′ storing the requested block in the MODIFIED state sends an M-INHIBIT signal to the M-INHIBIT line to notify the memory module 100 to ignore the request being processed or stored in the working buffer. Authorizes, and instructs the processor module 200 which transmitted the request to retransmit the request, and at the same time updates the memory module 100 through a block eviction request, or updates the block using another kind of request. At the same time, the memory module 100 changes the state information in the directory cache 600 for the block to the CLEAN state and updates the memory block. The memory module 100 examines the state information in the directory cache 600 of the requested block, and if the state of the block is DIRTY (any one of the other processor modules 200 'holds the requested block in the MODIFIED state). If so) ignore the request. However, when the state of the block is CLEAN, the memory module 100 prepares to provide the block for the broadcast read request, as in the operation of the conventional memory module, and examines the M-INHIBIT line to detect the M-INHIBIT signal line. If authorized, the request can be aborted. Upon receiving the requested block, the processor module 200 stores the block in its own cache 500 in the SHARED state and performs a read operation.

Write hit-When the cache 500 in the processor module 200 holds a block that has been requested to be written in the SHARED or MODIFIED state, and if it is held in the MODIFIED state, the processor module 200 is the memory module 100. Writes to the block without sending any request. If the cache 500 in the processor module 200 holds the requested block in the SHARED state, the processor module 200 tells the other processor modules 200 'and the memory module 100 about the block. After sending the invalidation request, a write operation is performed on the requested block stored in its own cache, and the state of the cache block is changed to MODIFIED. For this request, the other processor modules 200 'storing the block in its own cache 500' convert the state of the block to the INVALID state, and the memory module 100 stores the directory cache of the block. 600) Convert the state information to the DIRTY state.

Write Failed-If the cache 500 in the processor module 200 does not hold a block that has been requested to write, or has a block that has been requested to write in an INVALID state, it does not hold the block in the cache 500. If not, the processor module 200 performs block replacement first and performs the following operation, otherwise, immediately performs the next operation.

The processor module 200 transmits a broadcast read request including an invalidation request for the block to the memory module 100 and the other processor module 200 ′. At this time, the processor module 200 'storing the requested block in the MODIFIED state transmits the block to the processor module 200' which has transmitted the request, and simultaneously converts the cache state of the block into the INVALID state. The processor module 200 ′ storing the block in the SHARED state converts the cache state of the block into the INVALID state. The memory module 100 examines the state information in the directory cache 600 of the requested block, and if the state of the block is CLEAN (the other processor module 200 'does not hold the requested block in the MODIFIED state). If the block is provided for the broadcast read request containing the invalidation request and the directory cache 600 state information of the block is changed to the DIRTY state, and the state of the block is DIRTY (another processor module 200) If any one of the ')' holds the requested block in the MODIFIED state, the request is ignored. Upon receiving the requested block, the processor module 200 stores the block in its cache 500 in the MODIFIED state and performs a write operation.

Hereinafter, an exemplary operation of the memory module 100 including the directory cache 600 according to another embodiment of the present invention is described by four cache block state information, that is, MODIFIED state, EXCLUSIVE state, SHARED state, INVALID state It is widely used in the existing commercialized multiprocessor system (advanced MESI write-invalid snooping cache coherency protocol such as Jang Sung-tae, Journal of KIISE, Vol. 21 No. 11, pp.2163-2173, November 1994 MESIs described in Shreekant Thakkar's The Symmetry Multiprocessor System 'ICPP, Vol. I, pp. 303-310, August 1988) read, invalidation, write hit and write failure of the write-invalidate cache coherence scheme. Each case is described. The EXCLUSIVE state of the cache state means that the corresponding block stored in the cache is valid, and there is no processor module storing the block rate in a valid state. A shared line is required on the system bus to maintain this state. . The shared line sends a read request to a processor module that stores a block in a valid state (that is, an EXCLUSIVE state, SHARED state, or DIRTY state) for a broadcast read request for any block from the processor module. Used to notify one processor module. In the following embodiments, block replacement means that when a cache failure occurs, the processor module 200 selects a block to be replaced in its own cache 500, and the selected block is updated. If it is in the MODIFIED state, the block (ie, an updated copy of the block) is copied to the corresponding memory module through a block evict request. At this time, the memory module 100 of the present invention converts the state information in the directory cache 600 for the block to the CLEAN state in response to the block eviction request, and updates the corresponding block in the memory module.

Read hit-When the cache 500 in the processor module 200 holds a block in which the read request is in a SHARED, EXCLUSIVE, or MODIFIED state, the processor module 200 transmits any request to the memory module 100. It also reads the block without doing anything.

Read failure-when the cache 500 in the processor module 200 does not hold a block that has been requested to read or when the block that has been read is held in an INVALID state, the block is not held in the cache 500. If not, the processor module 200 performs block replacement first and performs the following operation, otherwise, immediately performs the next operation.

The processor module 200 transmits a broadcast read request for the block to the memory module 100 and the other processor module 200 ′. At this time, the processor module 200 ′ storing the requested block in a valid state, that is, in a MODIFIED state, SHARED state, or EXCLUSIVE state, applies a shared signal to the shared line. If the state of the valid block is the EXCLUSIVE state, the processor module 200 'also converts the cache state of the block to the SHARED state. If the state of the valid block is a MODIFIED state, the processor module 200 'applies an M-INHIBIT signal to the M-INHIBIT line to notify the memory module 100 to ignore the request being processed or stored in the working buffer. Instructing the processor module 200 which has transmitted the request to retransmit the request and updating the memory module 100 first through a block eviction request or by using another type of request to update the block using the processor module 200. At the same time, the memory module 100 converts the state information in the directory cache 600 for the corresponding block stored in the memory module 100 into the CLEAN state and updates the corresponding block. The memory module 100 examines the state information in the directory cache 600 of the requested block, and if the state of the block is DIRTY (any one of the other processor modules 200 'holds the requested block in the MODIFIED state). If so) ignore the request. However, if the state of the block is CLEAN (in the case of the MESI cache protocol, as described below, the write module is hitting the block in the EXCLUSIVE state, the corresponding processor module sends the state of the cache block without sending any request to the memory module. Memory module 100 is ready to provide the block for the broadcast read request, as in the operation of a conventional memory module, M may be storing the block in the MODIFIED state. You can stop the processing of the request if the M-INHIBIT signal line is present by examining the -INHIBIT line. Receiving the requested block, the processor module 200 sends the block to the EXCLUSIVE state when the shared signal line is not applied to the shared line for the transmitted request. Otherwise, the processor module 200 sets the block to the SHARED state. Save to and perform a read operation.

Write hit-When the cache 500 in the processor module 200 holds a block that has been requested to be written in the EXCLUSIVE, SHARED, or MODIFIED state. If the cache is held in the MODIFIED state, the processor module 200 includes a memory module ( 100) performs a write operation on the block without transmitting any request, and if held in the EXCLUSIVE state, the processor module 200 writes to the block without transmitting any request to the memory module 100. It performs the work and converts the state of the cache block to the MODIFIED state. If the cache 500 in the processor module 200 holds the requested block in the SHARED state, the processor module 200 tells the other processor modules 200 'and the memory module 100 about the block. After sending the invalidation request, a write operation is performed on the requested block stored in its own cache, and the state of the cache block is changed to MODIFIED. The other processor modules 200 'storing the block in its own cache 500' for this request convert the state of the block into the INVALID state, and the memory module 100 stores the directory cache 600 of the block. ) Convert status information to DIRTY state.

Write Failed—The cache 500 in the processor module 200 does not hold a block that has been requested to write, or holds a block that has been requested to be in an INVALID state, and does not hold the block in the cache 500. If not, the processor module 200 performs block replacement first and performs the following operation, otherwise, immediately performs the next operation.

The processor module 200 transmits a broadcast read request including an invalidation request for the block to the memory module 100 and the other processor module 200 ′. At this time, the processor module 200 ′ storing the requested block in the MODIFIED state sends an M-INHIBIT signal to the M-INHIBIT line to notify the memory module 100 to ignore the request being processed or stored in the working buffer. The processor transmits the block to the processor module 200 that has transmitted the request, and converts the cache state of the block to the INVALID state. The processor module 200 ', which stores the block in the EXCLUSIVE or SHARED state, converts the cache state of the block into the INVALED state. The memory module 100 examines the state information in the directory cache 600 of the requested block, and when the state of the block is DIRTY (any one of the other processor modules 200 'holds the requested block in the MODIFIED state). If so) ignore the request. However, if the state of the block is CLEAN (when the MESI cache protocol is writing to the block in the EXCLUSIVE state as described above, the processor module MODIFIED the state of the cache block without sending any request to the memory module). (The other processor module may be storing the block in the MODIFIED state because it is converted to the state.) The memory module 100 converts / maintains the directory cache 200 state information of the block to the DIRTY state, and at the same time, the conventional memory module The operation may be prepared to provide the block for the broadcast read request containing the invalidation request, and the processing of the request may be stopped when the M-INHIBIT signal line is authorized by examining the M-INHIBIT line. . Upon receiving the requested block, the processor module 200 stores the block in its cache 500 in the MODIFIED state and performs a write operation.

In the description of the embodiment of the present invention, only the case where the memory modules 100 and 100 'are configured as the directory cache 600 and the memory 100 is described. However, as shown in FIG. 9, a part of the memory modules 100 and 100' It should be understood that the same may be applied to the case where only the memory 700 is configured. In this case, the memory module 100 composed of only the memory 700 operates in the same manner as the existing memory module, and thus corresponds to a case in which the corresponding block is stored in the CLEAN state in the memory module in the above-described embodiments.

As described above, the multiprocessor including the directory cache in the memory module of the present invention alleviates the bottleneck in the memory module and improves the performance of the system when the write-invalid cache coherency protocol is driven due to the fast memory access. Can be improved.

Claims (5)

A system bus operating under a split transaction protocol, at least one memory module coupled to the system bus, and a plurality of processor modules each coupled to the system bus In a shared memory multiprocessor having a memory module, the memory module includes a memory and a directory cache that provides faster access time than the memory, wherein the memory and the directory cache are separated from each other, the memory A shared memory multiprocessor for maintaining status information in said directory cache that specifies whether the data block is valid for each data block stored in the. 2. The method of claim 1, wherein upon receiving an access request for any data block stored in the memory module from one of the processor modules, the directory cache is first accessed and state information stored in the directory cache is stored in the arbitrary data. And perform the memory access request only when the block indicates validity. 3. The memory module of claim 2, wherein when the request is a broadcast read request containing an invalidation request, the memory module converts the state information in the directory cache to indicate that the arbitrary data block is invalid. Shared memory multiprocessor. The method of claim 1, wherein the memory module indicates that the arbitrary data block is invalid when the memory module receives an invalidation request for any data block stored in the memory module from one of the processor modules. Shared memory multiple processor, characterized in that the conversion / maintenance. The method of claim 1, wherein when the memory module receives a block extraction request for an arbitrary data block stored in the memory module from one of the processor modules, the memory module indicates that the arbitrary block is valid. Shared memory multiprocessor, characterized in that for converting.