JP3669616B2 - Microcomputer and data processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an idle wait cycle insertion technique for avoiding data contention on a bus, and is effective when applied to, for example, a microcomputer having a DMAC (Direct Memory Access Controller), in particular, a bus state controller thereof. Technology.
[0002]
[Prior art]
Devices that are targets of data transfer or access by a microcomputer have a difference in the time required until the data input or output operation is determined depending on the circuit configuration. The internal wait cycle is inserted into a device with a slow operation speed relative to the standard of the bus cycle number of the bus access operation by the microcomputer (the number of cycles of the synchronous clock signal for the bus access operation), and the slow device inputs the operation. Alternatively, the bus cycle operation can be maintained until the output operation is determined.
[0003]
In recent years, the operating frequency of an external memory bus in a microcomputer system has been remarkably increased. At this time, in the case of a device having a low operating speed, it takes time to achieve a high output impedance state of the output circuit even if the reading operation is terminated. Therefore, even if the data read from the low-speed device to the high-speed memory bus is completed, the output operation may not be completed in time for the high-speed bus cycle, and there is a possibility of colliding with the next access data on the bus. To prevent this, if there is a possibility of data collision on the bus when the next access is started, an idle wait cycle is inserted before starting the next access cycle, and data collision occurs. Can be avoided. An example of a document describing such a technique is page 184 of the SH2 User's Manual (Hitachi, Ltd., issued in September 2006).
[0004]
[Problems to be solved by the invention]
As represented by the above document, the conventional bus state controller can only set the internal wait of the bus cycle and the idle wait for each address area. That is, the microcomputer accesses a device that can be accessed by specifying an address (denoted as a memory mapped device) and a device that can be accessed without receiving an address (denoted as an I / O device). However, conventionally, idle wait setting can only be performed for each address area in a memory mapped device.
[0005]
For this reason, when data transfer in the single address mode by the DMAC is performed with respect to an I / O device in which the achievement of the high output impedance state of the output circuit after the end of the read operation is delayed, with the memory mapped device, Since an idle weight cannot be set for the O device, a necessary idle weight must be set in the memory device. For example, when the number of idle waits required for the memory mapped device is 1 cycle and the number of idle waits required for the I / O device is 3 cycles, the number of idle waits for the memory mapped device is the above-mentioned single address DMA transfer. 3 must be set. Accordingly, even if another memory mapped device is accessed following the DMA transfer of the single address, the access data of the other memory mapped device and the low-speed I / O device are accessed on the data bus. Collisions with the output data are avoided.
[0006]
However, after the single address DMA transfer, when the read / write operation for the memory mapped device is continued or when the memory mapped device in another address area is accessed, three cycles of idle wait are inserted, It has been clarified by the present inventor that an idle weight that is two cycles extra is inserted with respect to the required number of idle waits, and the access of the memory-mapped device becomes slow.
[0007]
An object of the present invention is to provide a microcomputer capable of preventing an idle wait from being undesirably inserted into an access of a memory mapped device. More specifically, an idle wait is prevented from being undesirably inserted in an access to a memory mapped device after a direct memory access in the single address mode.
[0008]
Another object of the present invention is to prevent undesirably slow access of a memory mapped device in a data processing system in which low speed I / O devices and high speed memory mapped devices are mixed.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0011]
That is, the first idle wait number (DIW) is accessed for the access of the first device (100) as the I / O device that can be accessed without receiving the address designation, and the memory that can be accessed by receiving the address designation. For the access of the second device (200) as a mapped device, a second idle wait number (EIW) can be set, and following the data transfer between the first device and the second device in the single address mode When the second device is accessed, an idle wait cycle defined by the first idle wait number is inserted before the second device, and further subsequent access to the second device is defined by the second idle wait number. Insert an idle wait cycle. For example, when the number of idle waits required for the second device is 1 cycle and the number of idle waits required for the first device is 3 cycles, the single device direct memory access transfer ends and the second device starts to access. Three idle wait cycles defined by the first idle wait number are inserted until the second device is accessed. However, in the subsequent second device access, the idle wait cycle is defined by the second idle wait number and only one cycle is required. . Therefore, when the number of idle waits can be set only for the second device as in the prior art, it is possible to eliminate the situation where the access of the second device consecutive after the direct memory access in the single address mode is delayed.
[0012]
The microcomputer according to the present invention will be described in more detail. The microcomputer according to the first aspect is provided between a first device accessible without designation of an address and a second device accessible with designation of an address. Direct memory access control means capable of single address data transfer, a central processing unit, and an external bus for the first device and the second device based on requests from the central processing unit and the direct memory access control means A semiconductor integrated circuit including a bus state controller capable of controlling an access operation. The bus state controller inserts an idle wait cycle defined by the first idle wait number after single address data transfer between the first device and the second device by the direct memory access control means, When accessing before and after the second device, an idle wait cycle defined by the second idle wait number is inserted when switching the access.
[0013]
A data processing system according to the present invention is connected to a first device accessible without designation of an address, a second device accessible by designation of an address, and the first and second devices via a bus. A microcomputer having control register means for setting the first idle wait number and the second idle wait number by the central processing unit, wherein the first device and the second device are connected in parallel. After accessing, when accessing the second device, insert an idle wait cycle defined by the first idle wait number before starting the access, and when accessing the second device before and after, when switching access The idle wait cycle defined by the second idle wait number is You type.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
<Microcomputer>
FIG. 2 shows a microcomputer according to an example of the present invention. The microcomputer 1 shown in the figure is not particularly limited, but is configured as an integrated circuit on a single semiconductor substrate such as single crystal silicon. The microcomputer 1 has a floating point unit (also referred to as FPU) 2. Further, the microcomputer 1 includes a central processing unit (also referred to as a CPU) 3 that can operate an integer. The microcomputer 1 has a 32-bit RISC (Reduced Instruction Set Computer) architecture having a 16-bit fixed length instruction set, although not particularly limited.
[0015]
In FIG. 2, what is indicated by reference numeral 4 is an address translation / cache unit (CCN). The address translation / cache unit 4 includes an instruction address translation buffer (also referred to as an instruction TLB) 40 for instructions and a unified address translation buffer (unified TLB) for data so that instruction access and data access by the CPU 3 can be parallelized. 41), and the instruction cache memory 42 and the data cache memory 43 are also individualized. A cache / address translation buffer controller (also referred to as a cache TLB controller) 44 controls the address translation / cache unit 4 as a whole.
[0016]
2 is a bus state controller, which is connected to the address translation / cache unit 4 via a 32-bit data bus 50 and a 29-bit address bus 51. A DMAC 8 is connected to the bus state controller 5 via a data bus 54 and an address bus 55.
[0017]
In the microcomputer 1, the CPU 3 and the DMAC 8 constitute a bus master module. External access by the microcomputer 1 is performed by an external bus interface circuit (PAD) 6 connected to the bus state controller 5 via a 64-bit data bus 52 and an address bus 53. The external bus interface circuit 6 is connected to an external data bus 60 and an external address bus 61.
[0018]
The microcomputer 1 includes a clock pulse generator (also referred to as CPG) 70, an interrupt control circuit 71, and serial communication interface controllers (SCI1, SCI2) as built-in peripheral circuits connected to a 16-bit peripheral data bus 56 and a peripheral address bus 57. 72, a real-time clock circuit 73, and a timer 74. These peripheral circuits are accessed by the CPU 3 or the DMAC 8 via the bus state controller 5.
[0019]
The DMAC 8 has, for example, four data transfer channels. For each data transfer channel, the source address register in which the transfer source address is set, the destination address register in which the transfer destination address is set, and the number of transfers are counted. And a channel control register in which a data transfer control mode and the like are set. The CPU 3 or the like initially sets data transfer control information for the register. When there is a data transfer request DREQ from the outside of the microcomputer 1, a data transfer request PDREQ from a peripheral circuit (such as timer 74) inside the microcomputer 1, or a data transfer request from the CPU, the control unit of the DMAC 8 controls the channel. With reference to the channel enable bit of the register, etc., it is determined whether or not the data transfer channel to be activated is operable in response to the data transfer request. Further, when the data transfer requests compete, one data transfer channel to be activated is determined according to a predetermined priority order. When one data transfer channel that should respond to the data transfer request is determined, the bus right request signal BREQ is asserted to the bus state controller 5 to request the bus right. When the bus state controller 5 asserts the bus right approval signal BACK, the DMAC 8 acquires the bus right, and the DMAC 8 performs data transfer control in response to the data transfer request via the bus state controller 5. The bus state controller 5 starts a bus cycle with the number of memory cycles corresponding to the address area of the address signal supplied from the DMAC 8.
[0020]
The DMAC 8 has a data transfer mode of a dual address mode and a single address mode. As is well known, the dual address mode is an operation in which data is transferred by designating addresses to both the transfer destination and transfer source devices, and the single address mode is the transfer destination or transfer source. In this operation, only one of the devices is addressed and data is transferred. The former is data transfer between memory mapped devices, and the latter is data transfer between a memory mapped device and an I / O device.
[0021]
The bus state controller 5 determines the access data size, the access time, the number of internal wait states and the number of idle wait states, which will be described later, according to the address area of the circuit to be accessed by the CPU 3 and the DMAC 8, and the peripheral bus bus 56, 57, and controls the bus access to the external buses 60 and 61. Further, the bus state controller 5 arbitrates contention for bus use requests from the cache TLB controller 44 and the DMAC 8. The bus state controller 5 has a data buffer 58. The data buffer 58 temporarily latches transfer data in order to absorb a difference in operation speed between circuits connected to the internal buses 50 and 51, the peripheral buses 56 and 57, and the external buses 60 and 61. Further, in the data transfer control by the DMAC 8, the DMAC 8 does not take the data latched in the data buffer 58, transfers the data from the data buffer 58 to the transfer destination, and performs unnecessary data transfer between the DMAC 8 and the data buffer 58. Transfer data to save.
[0022]
When fetching an instruction, the CPU 3 outputs an instruction address to the 32-bit instruction address bus 30 and fetches an instruction output to the instruction data bus 31. Further, the CPU 3 outputs a data address to the 32-bit data address bus 32, reads (loads) the data via the 32-bit data bus 33, and writes the data via the 32-bit data bus 34 ( Store). The instruction address and data address are logical addresses.
[0023]
The FPU 2 is not particularly limited, but does not have a memory addressing capability for accessing the data cache memory 42 or the like. The CPU 3 performs an addressing operation for accessing data on behalf of the FPU 2. This is to save the chip area by eliminating the need for the memory addressing circuit of FPU2. Data loading to the FPU 2 is performed via the 32-bit data bus 33 and the 32-bit data bus 35, and data storage from the FPU 2 is performed via the 64-bit data bus 36. Data transfer from the FPU 2 to the CPU 3 is performed using the lower 32 bits of the 64-bit data bus 36.
[0024]
CPU 3 not only fetches data for FPU 2 but also fetches all instructions including floating point instructions for FPU 2. The floating point instruction fetched by the CPU 3 is given from the CPU 3 to the FPU 2 via the 32-bit data bus 34.
[0025]
Although not particularly limited, the microcomputer 1 handles a virtual address space defined by a 32-bit virtual address and a physical address space defined by a 29-bit physical address. Address conversion information for converting a virtual address into a physical address includes a virtual page number and a corresponding physical page number. The address conversion table is formed in an external memory (not shown) of the microcomputer 1. Of the address translation information in the address translation table (not shown), recently used information is stored in the instruction TLB 40 and the unified TLB 41. The control is performed, for example, by the operating system of the microcomputer 1.
[0026]
The data unified TLB 41 stores a maximum of 64 entries of data and instruction address conversion information. The unified TLB 41 associates a physical page number corresponding to the virtual page number of the virtual address output from the CPU 3 to the data address bus 32 for data fetch from the address conversion information, and converts the virtual address into a physical address. .
[0027]
The instruction TLB 40 for instructions stores up to four entries of address translation information dedicated to instructions. In particular, the entry held by the instruction TLB 40 is a part of the address conversion information of the instruction address held by the unified TLB 41. That is, when it is found by the associative search that the instruction TLB 40 does not have target address conversion information, the address conversion information is supplied from the unified TLB 41 to the instruction TLB 40. The instruction TLB 40 performs an associative search from the address conversion information for the physical page number corresponding to the virtual page number of the virtual address output from the CPU 3 to the instruction address bus 30 for instruction fetch. As a result of the search, when there is target address conversion information (TLB hit), the virtual address is converted into a physical address using the address conversion information. As a result of the search, when there is no target address translation information (TLB miss), the cache TLB controller 44 controls an operation for obtaining the target address translation information from the unified TLB 41.
[0028]
The data cache memory 43 receives the physical address converted by the unified TLB 41 at the time of data fetching, and performs an associative search of the cache entry based on the physical address. If the search result is a read hit, data corresponding to the physical address is output to the data bus 33 or 35 from the cache line associated with the hit. If the retrieval result is a read miss, the data for one cache line including the data relating to the miss is read from an external memory (not shown) via the bus state controller 5 and the cache fill is performed. As a result, the data related to the cache miss is read to the bus 33 or 35. When the search result is a write hit, if the cache operation mode is the copy back mode, data is written in the hit entry and the dirty bit of the entry is set. When the dirty bit in the set state indicates an inconsistent state with the data in the external memory, and the dirty cache entry is evicted from the cache memory by the cache fill operation, writing back to the external memory is performed. In the write-through mode, data is written to the hit entry and data is also written to the external memory. If the search result is a write miss, in the copy back mode, the cache fill is performed, the dirty bit is set, the tag address is updated, and the data is written to the cache line that has been filled. In the write-through mode, data is written only to the external memory.
[0029]
The instruction cache memory 42 receives the physical address converted by the instruction TLB 40 at the time of instruction fetch, and performs an associative search of the cache entry based on the physical address. If the search result is a read hit, an instruction corresponding to the physical address is output to the instruction data bus 31 from the cache line associated with the hit. If the search result is a read miss, data for one cache line including the instruction relating to the miss is read from an external memory (not shown) via the bus state controller 5 and a cache fill is performed. As a result, an instruction relating to a miss is given to the CPU 3 via the instruction data bus 31.
[0030]
The instruction TLB 40, unified TLB 41, and cache TLB controller 44 constitute a memory management unit. This memory management unit can perform storage protection by setting an access right to the virtual address space in each of the privileged mode and the user mode. For example, the address translation information has protection key data for each virtual address page number. The protection key data is 2-bit data representing the access right of the page as a code, can be read only in the privileged mode, can be read and written in the privileged mode, can only be read in both the privileged and user modes, and the privileged mode. In either of the user mode and the user mode, any access right that can be read and written can be set. If the actual access type violates the access right set by the protection key data, a TLB protection violation exception is generated. When a TLB protection violation exception is generated, for example, after the protection violation is resolved by exception processing, a return instruction from exception processing is executed, and the interrupted normal processing instruction is re-executed.
[0031]
<Bus state controller>
FIG. 1 shows a detailed example of the bus state controller 5. The bus state controller 5 inputs / outputs data via the data buffer 58, outputs an address signal from the address control unit 508, and representatively shows a data acknowledge signal DACK and an area selection signal CS from the strobe generation circuit 507. Then, strobe signals such as a read signal RD and a write enable signal WE are output. Strobe signals such as the area selection signal CS, the read signal RD, and the write enable signal WE are used as access control signals for a memory mapped device such as a memory arranged outside the microcomputer 1. The data acknowledge signal DACK is a data strobe signal for an I / O device such as a protocol controller. For example, when the I / O device asserts the data transfer request signal DREQ, the I / O device performs the data input operation or the data output operation after waiting for the assertion of the data acknowledge signal DACK.
[0032]
The bus state controller 5 controls the bus access cycle according to the control data set in the control register 501. The control register 501 has a setting area for control information such as an access data size SZ, an area internal wait number ITW, an area idle wait number EIW for each address area, and further, a device idle wait number DIE for each I / O device. It has a setting area. For setting the control information for the control register 501, the request control unit 500 determines a register address supplied from the CPU 3 via the CCN 4, and the register control unit 503 is supplied via the data buffer 58 according to the determination result. This is done by writing control information 501 to the control register.
[0033]
The CCN 4 requests the bus access by asserting the request signal REQ to the request control unit 500. When read data according to the request is supplied from the data buffer 58 to the CCN 4 or when write data according to the request is output from the data buffer 58, the request control unit 500 asserts the ready signal RDY to the CCN 4. . At this time, necessary address information is given to the request control unit 500 via the bus 51.
[0034]
The DMAC 8 requests the request control unit 500 for bus access by asserting the bus request signal BREQ, acquires the bus right by the bus acknowledge signal BACK, and then sends the address information to the request control unit 500 via the bus 55 and the like. give.
[0035]
The request control unit 500 determines an access area by decoding the address information given from the CCN 4 or the DMAC 8, and the area idle wait number EIW, the area internal wait number ITW, and the access data size corresponding to the determined access area A storage area such as SZ is selected by the register control unit 503 and supplied to the external bus control unit 504. The external bus control unit 504 performs the address output operation from the address control unit 508 according to the area idle wait number EIW, the area internal wait number ITW, the access data size SZ, and the like, strobe signals CS, RD, and WE from the strobe output generation unit 507. The data output or input operation of the data buffer 58 by the data control unit 506 is controlled.
[0036]
When the operation mode of the data transfer channel activated by the DMAC 8 is designated as the single address mode, a signal 520 indicating the operation mode is given to the request control unit 500, and the memory mapped device is connected via the external bus control unit 504. When the addressed bus access cycle is activated, the strobe output generation circuit 507 is made to assert the data acknowledge signal DACK. Thus, when the DMAC 8 performs data transfer in the single address mode, the I / O device receiving the data acknowledge signal DACK can perform an input operation or an output operation in parallel with the addressed access to the memory mapped device. it can.
[0037]
Here, the bus access control content by the external bus control unit 504 based on the device idle wait number DIW and the area idle wait number EIW will be described in detail. When the external bus control unit 504 is notified by the signal 520 that the DMAC 8 is in the single address mode, the external bus control unit 504 terminates the data transfer operation in the single address mode and then continues to the next bus access. If cycle activation is requested, an idle wait cycle defined by the device idle wait number DIW is inserted, and then the next bus access cycle is activated. In addition, when a bus access cycle for a memory mapped device other than the bus access in the single address mode is switched from a read operation to a write operation in the same address area, the address area is switched, and the area is changed when the access is switched. An idle wait cycle defined by the number of idle waits EIW is inserted, and the next bus access cycle is started. The reason why the idle wait cycle is inserted when the address area is switched is to automatically avoid the possibility of data collision when the access area is changed from the low-speed device area to the high-speed device area. .
[0038]
Next, an example of an idle wait cycle insertion operation will be described. FIG. 3 shows an example of a data processing system using the microcomputer 1. What is indicated by 100 is an I / O device, which has a storage area that does not need to be addressed from the outside, such as a FIFO (First In First Out) buffer, and the like. The area is interfaced to the data bus 60. The I / O device 100 is, for example, a semiconductor device such as a communication I / O or a protocol control I / O. In FIG. 3, what is indicated by 200 is a memory mapped device, such as a semiconductor memory device.
[0039]
FIG. 4 shows an example of the operation timing when the memory mapped device continues to be accessed following the data transfer in the single address mode (single address DMA transfer). In the example shown in FIG. 4, it is assumed that the bus access cycle when the internal wait cycle is not inserted is two system clock signals (T1, T2), and the internal wait cycle is not inserted.
[0040]
First, a bus cycle (BS1) for a single address DMA transfer operation is started. In this operation, the write operation for the memory mapped device 200 and the output operation of the I / O device 100 are performed in parallel. Since this is a single address DMA transfer operation, an idle wait cycle (I1, I2, I3) IWAIT1 defined by the number of device idle waits DIW (for example, 3) is inserted after the DMA transfer. During this time, it takes time for the output buffer of the I / O device 100 to determine the high output impedance state on the data bus despite the completion of the access. During the idle wait cycle IWAIT1, the data bus Undesirable data remains on the top. Since the bus cycle BS2 for the next memory mapped device is after the idle wait cycle IWAIT1, there is no collision with the data after the end of the bus cycle BS1.
[0041]
The bus cycle BS2 is for the memory mapped device in the address area 1, and the address area is changed in the next bus cycle BS3. At this time, one cycle of idle wait cycle (I1) IWAIT2 determined by area idle wait number EIW (for example, 1) is inserted between bus cycle B2 and bus cycle B3. Since the next bus cycle BS4 is for the same address area 2 as before, no idle wait cycle is inserted at the switching of the access operation.
[0042]
FIG. 5 shows, as a comparative example, an operation in a conventional bus state controller in which the number of idle waits of the I / O device 100 cannot be set and the memory mapped device 200 handles the idle waits. When transferring data in single address mode by DMAC to / from a memory mapped device to an I / O device, an idle wait cannot be set for the I / O device, so the necessary idle wait can be assigned to the memory mapped device. Must be set. For example, as in the case of FIG. 4, when the number of idle waits required for the memory mapped device is 1 cycle and the number of idle waits required for the I / O device is 3 cycles, The idle number of 3 must be set for the mapped device. As a result, even if a single address DMA transfer is performed in the bus cycle BS1 and subsequently another memory mapped device is accessed (BS2), the other memory mapped device is accessed on the data bus. Collisions between data and output data of the low speed I / O device are avoided. However, after the single address DMA transfer, when the read / write operation for the memory mapped device is continued, or when the memory mapped device in another address area is accessed, the same as before the bus cycle BS3. Three idle cycles are inserted, and an extra idle weight of two cycles is inserted with respect to the originally required number of idle waits. When the bus cycle BS3 in FIG. 4 is compared with the bus cycle BS3 in FIG. 5, the difference is clear, and the bus state controller 5 can prevent the memory mapped device 200 from accessing slowly. Access can be speeded up.
[0043]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0044]
For example, the microcomputer may not have an address conversion function or a cache memory. Further, the microcomputer may not have a peripheral circuit. Further, a signal that gives an instruction for an input operation or an output operation to the I / O device is not limited to a data acknowledge signal.
[0045]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0046]
In other words, the number of idle waits can be set for each of the first device as the I / O device and the second device as the memory mapped device, and after the data transfer in the single address mode, it is specific to the low-speed I / O device. However, when a memory-mapped device is subsequently accessed continuously, it is possible to insert an idle wait cycle specific to a high-speed memory-mapped device. An extra idle wait cycle can be prevented from being inserted when the device is accessed.
[0047]
Therefore, in a data processing system in which low-speed I / O devices and high-speed memory-mapped devices are mixed, it is possible to prevent the memory-mapped device from being undesirably slowed and to improve data processing efficiency.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a detailed example of a bus state controller.
FIG. 2 is a block diagram of a microcomputer according to an example of the present invention.
3 is a block diagram illustrating an example of a data processing system using the microcomputer of FIG. 2;
FIG. 4 is a timing chart showing an example of an operation when an access to a memory mapped device continues after a single address DMA transfer.
FIG. 5 is a timing chart showing a comparative example of the operation when the memory mapped device continues to be accessed following the single address DMA transfer in the conventional bus state controller in which the number of idle waits of the I / O device cannot be set.
[Explanation of symbols]
1 Microcomputer
3 CPU
4 Address translation / cache unit
5 Bus state controller
6 External interface circuit
8 DMAC
100 I / O devices
200 Memory mapped device
501 Control register
Number of DIW device idle waits
Number of EIW area idle waits
ITW area internal waits

Claims (3)

A central processing unit capable of outputting a logical address signal ;
An address conversion circuit capable of converting a logical address signal output from the central processing unit into a first address signal;
A data transfer control circuit accessed by the central processing unit based on the first address signal and capable of transferring data using the second address signal;
A bus control circuit capable of performing an external bus access operation using the first address signal or the second address signal based on a request from the central processing unit and the data transfer control circuit ;
A first address bus connected to the central processing unit and the address conversion circuit;
A second address bus connected to the address conversion circuit, the data transfer circuit, and the bus control circuit and capable of transmitting the first address signal and the second address signal;
The data transfer control circuit includes:
A first data transfer between a first device accessible without designation of the second address signal and a second device accessible by designation of the second address signal is possible;
The bus control circuit includes:
Control register means designated by the first address, wherein the first idle wait number and the second idle wait number are set by the central processing unit;
Inserting an idle wait cycle defined by the first idle wait number after the first data transfer,
When accessing the second device before and after, the microcomputer inserts an idle wait cycle defined by the second idle wait number when switching the access. In the bus control circuit , an internal wait cycle number for increasing the number of cycles of the bus access operation of the second device is set in the register means for each address area by the central processing unit. 2. The microcomputer according to claim 1, wherein an internal wait cycle defined by the number of internal wait cycles corresponding to the access address area is inserted. A first device accessible without receiving an address designation;
A second device accessible by receiving an address designation;
A microcomputer connected to the first and second devices by a bus;
The microcomputer is
A central processing unit capable of outputting a logical address signal ;
An address conversion circuit capable of converting a logical address signal output from the central processing unit into an address signal;
A data transfer control circuit that is accessed by the central processing unit based on the address signal, is capable of data transfer using the address signal, and is capable of single address data transfer between the first device and the second device;
A bus control circuit capable of controlling an external bus access operation to the first device and the second device based on a request from the central processing unit and the data transfer control circuit ;
A first address bus connected to the central processing unit and the address conversion circuit and capable of transmitting a logical address signal output by the central processing unit;
A second circuit connected to the address conversion circuit, the data transfer circuit, and the bus control circuit and capable of transmitting an address signal converted by the address conversion circuit and an address signal output by the data transfer control circuit Including address bus ,
The bus control circuit includes:
Control register means specified by the address signal converted by the address conversion circuit, wherein the first idle wait number and the second idle wait number are set by the central processing unit;
Inserting an idle wait cycle defined by the first idle wait number after single address data transfer between the first device and the second device by the data transfer control circuit ;
A data processing system, wherein when the second device is accessed before and after, an idle wait cycle defined by the second idle wait number is inserted when the access is switched.

Images