JP2002108702A - Microcomputer and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a decrease in the performance of a system. SOLUTION: A central processor (3) is provided which can write data of a cache memory back to a memory in a period wherein a task managed by an operating system is not executed while valid bits of blocks whose dirty bits are effective are made effective, and the writing-back processing is carried out in the period wherein the task is not performed to reduce cases wherein the cache contents which were used last are written back right before caching, thereby reducing the decrease in the performance of the system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing technology,
Further, the present invention relates to a technique for improving a cache system, for example, a technique effective when applied to a single-chip microcomputer (hereinafter simply referred to as a "microcomputer") and a data processing device including the same.

[0002]

2. Description of the Related Art Recent control microcomputers are equipped with a cache memory system which enables high-speed processing of a large amount of data as the amount of data to be handled increases. According to this cache system, by using the data left in the cache memory by the previous external memory access,
Since the target data can be obtained at high speed, the processing performance of the system can be improved.

In the field where the operating system manages memory without the user being aware of the actual memory,
The data processing device needs to support an address translation mechanism. The address translation mechanism is a mechanism that translates a virtual address into a physical address in order to implement virtual storage. Furthermore, in order to execute the address translation mechanism at high speed, an address translation buffer (Translation lookaside buffer) holding a translation pair of a virtual address and a physical address.
(Abbreviated as "TLB") in a microcomputer is also employed. As an example of a document describing a cache system, see,
There is “Computer Architecture and Configuration Method (pages 273 to 308)” issued by Asakura Shoten on January 5th.

[0004]

The cache memory system is faster than a semiconductor memory (hereinafter referred to as "external memory") arranged outside the microcomputer, but has a small storage capacity, so that only a part of the external memory is replaced. No. There are two possible reasons for replacing the external memory by the cache memory system:
(1) Instructions and constant values are used only for reading, and (2) Results of operations (including intermediate results) performed on read data are stored.

In the case of (1), frequently used data in the external memory is copied to the cache memory (this is referred to as "caching"), and the second and subsequent references are speeded up. In this case, since only the data is referred to, the information in the cache memory matches the information stored in the external memory. In contrast, in case (2) above,
Since the contents of the data in the cache memory are changed, the information in the cache memory does not match the information stored in the external memory. Therefore, it is necessary to write back the updated contents in the cache memory to the external memory (write back).

[0006] Caching or write-back is a data exchange with a relatively low-speed external memory, and is a major factor in lowering system performance. In order to reduce such performance degradation, there are techniques such as prefetch and write-back buffer. Prefetch is a technique for caching data before it is actually needed. The write-back buffer is a technique for increasing the speed of caching by postponing the write-back in the process of writing back and caching.

[0007] In a microcomputer application system, particularly in a device built-in control device, an event driven system which starts an operation starting from a certain event (Event) is generally used. For example, there is an event-driven process in which some operation is performed according to an instruction of a person who operates the apparatus. In an event-driven system, for example, as shown in FIG.
This is a standby state of the (central processing unit). In this state, no operation is required, but immediacy for high-speed operation is required from the occurrence of an event. Further, when two consecutive events are equal to each other, as shown in FIG. 7, the cache memory is not accessed when the CPU is in an idle state, but is frequently accessed at the time of high-speed operation after the event occurs. On the other hand, when two consecutive events are different from each other, the processing after the occurrence of the event is different as shown in FIG. That is, the first block of the external memory is accessed by the occurrence of the event, and the first block of the external memory is written back and the second block of the external memory is accessed by the occurrence of the event. When two consecutive events are different from each other, caching is required for a second block different from the data of the first block used last time. At this time, the cache content used last time is written back. It has been found by the inventor of the present application that this is necessary, and this is considered to be a cause of system performance degradation.

[0008] An object of the present invention is to reduce a decrease in system performance.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a data storage area, a tag area for storing address information related to the data,
One cache block is formed including a dirty bit indicating that the content of the data has been updated and a valid bit indicating the validity of the data, and a read cache and a write cache of a memory in which the data is stored are formed. A cache system that enables the cache system, and further writes data of the cache system to the memory in a state where the dirty bit is valid while the task managed by the operating system is not executed. A central processing unit capable of backing is provided.

[0012] According to the above means, the central processing unit, while the task managed by the operating system is not executed, stores the data of the cache system in a state where the valid bit is valid for the block in which the dirty bit is valid. Is written back to the memory. If two consecutive events are different from each other,
Although caching is required for the second block different from the data of the first block used last time, the write-back processing is executed so that the task managed by the operating system is not executed as described above. Therefore, immediately before the caching of the second block, the number of cases in which the previously used cache contents are written back is reduced, which alleviates the performance degradation of the system.

Further, by monitoring the bus used for the memory access, a bus state monitoring circuit capable of detecting a period during which the memory is not accessed by the central processing unit, and a detection result of the detection stage. Based on this, the microcomputer can be configured to include a write-back control circuit for instructing the start of the write-back process during a period in which the memory is not accessed.

[0014]

FIG. 10 shows a data processing apparatus to which a microcomputer according to the present invention is applied.

The data processing device 200 is an information terminal device, although not particularly limited, and includes a microcomputer 231 and an SDRAM 23 via a system bus BUS.
2. A ROM (Read Only Memory) 234, a peripheral device control unit 235, a display control unit 236, and the like are connected to each other so as to be able to exchange signals, and perform predetermined data processing according to a predetermined program. The microcomputer 231 is a logical core of the present system, and is mainly used for addressing, reading and writing of information, data operation, instruction sequence, acceptance of interrupt, and information exchange between the storage device and the input / output device. It has a function such as activation, and performs arithmetic control, bus control, memory access control, and the like. The SDRAM 232 and the ROM 234 are positioned as external memories of the microcomputer 231.
The SDRAM 232 stores operating system software executed by the microcomputer 231, application software, and various data necessary for arithmetic processing of the microcomputer in the external storage device 2.
38 and so on. Here, the external storage device 23
Although not particularly limited, 8 is a semiconductor memory card or the like formed in a card shape including a flash memory element as a storage element. The ROM 234 stores a read-only program. The peripheral device control unit 235 controls the operation of the external storage device 238 and the keyboard 239.
Information input control is performed. The display control unit 236 controls information display on the liquid crystal display 240. The display control unit 236 includes a semiconductor chip and an image memory for drawing processing.

FIG. 1 shows the microcomputer 23
1 is shown. Although not particularly limited, the microcomputer 231 shown in the figure is configured to be integrated on a single semiconductor substrate such as single crystal silicon. The microcomputer 231 has a floating point unit (also referred to as FPU) 2. Further, the microcomputer 231 includes a central processing unit (also referred to as a CPU) 3 capable of operating an integer. The microcomputer 231 is not particularly limited, but includes a 32-bit RISC (Reduced Reduced Instruction Set) having a 16-bit fixed-length instruction set.
Instruction Set Computer (reduced instruction set computer) architecture.

In FIG. 1, what is indicated by reference numeral 4 is an address translation / cache unit (CCN).
The address translation / cache unit 4 includes an instruction address translation buffer (instruction TLB) for instructions so that instruction access and data access by the CPU 3 can be parallelized.
) And a data unified address translation buffer (also referred to as a unified TLB) 41, and an instruction cache memory 42 and a data cache memory 43 are also individualized. A cache / address translation buffer controller (also referred to as a cache TLB controller) 44 controls the address translation / cache unit 4 as a whole.

In FIG. 1, reference numeral 5 denotes a bus state controller, which is connected to the address conversion / cache unit 4 via a 32-bit data bus 50 and a 29-bit address bus 51. The bus state controller 5 includes a data bus 5
4 and the DMAC 8 via the address bus 55.

In the microcomputer 231, the CPU 3 and the DMAC 8 constitute a bus master module. External access by the microcomputer 231 is performed by a 64-bit data bus 52 and an address bus 53.
The operation is performed by an external bus interface circuit (PAD) 6 connected to the bus state controller 5 through the interface. The external bus interface circuit 6 is connected to an external data bus 60 and an external address bus 61.

The microcomputer 231 includes a clock pulse generator (CPG) 70 and an interrupt control circuit 7 as built-in peripheral circuits connected to the 16-bit peripheral data bus 56 and the peripheral address bus 57.
1, a serial communication interface controller (SCI1, SCI2) 72, a real-time clock circuit 73, and a timer 74. These peripheral circuits are accessed by the CPU 3 or the DMAC 8 via the bus state controller 5.

The DMAC 8 has, for example, four data transfer channels, and for each data transfer channel, a source address register in which a transfer source address is set, a destination address register in which a transfer destination address is set, and a transfer count. And a channel control register for setting a data transfer control mode and the like. Initial setting of the data transfer control information for the register is performed by the CPU 3 or the like. The control unit of the DMAC 8 is a microcomputer 2
When there is a data transfer request DREQ from outside the CPU 31, a data transfer request PDREQ from a peripheral circuit (such as the timer 74) inside the microcomputer, or a data transfer request from the CPU, the channel enable bit of the channel control register is referred to. Then, it is determined whether the data transfer channel to be activated in response to the data transfer request is operable. Further, when the data transfer requests conflict, one data transfer channel to be started is determined according to a predetermined priority. When one data transfer channel to respond to the data transfer request is determined, a bus right request signal BREQ is asserted to the bus state controller 5 to request a bus right. When the bus state controller 5 asserts the bus right acknowledge signal BACK, this causes the DMAC 8 to acquire the bus right,
The DMAC 8 controls data transfer in response to the data transfer request via the bus state controller 5. The bus state controller 5 starts the bus cycle with the number of memory cycles according to the address area of the address signal supplied from the DMAC 8 and the like.

The DMAC 8 has a data transfer mode of a dual address mode and a single address mode.
As is well known, both operation modes are operations in which a dual address mode performs data transfer by designating an address to both a transfer destination device and a transfer source device.
The single address mode is an operation of performing data transfer by specifying an address only for one of the transfer destination and transfer source devices. The former is for data transfer between memory mapped devices, and the latter is for data transfer between memory mapped devices and I / O.
Data transfer to and from the device.

The bus state controller 5 includes a CP
The access data size, the access time, the number of internal wait states and the number of idle wait states, which will be described later, are determined in accordance with the address area of the circuit to be accessed by the U3 or the DMAC 8, and the peripheral buses 56, 5
7, and control the bus access to the external buses 60 and 61. Further, the bus state controller 5 arbitrates contention for a bus use request from the cache TLB controller 44 and the DMAC 8. The bus state controller 5 has a data buffer 58. The data buffer 58 includes internal buses 50 and 51, peripheral buses 56 and 57,
Transfer data is temporarily latched in order to absorb a difference in operation speed between circuits connected to the external buses 60 and 61. Further, in the data transfer control by the DMAC 8, the DMAC 8
Transfers the data from the data buffer 58 to the transfer destination without taking in the data latched in the data buffer 58,
Data transfer is performed such that useless data transfer between DMAC 8 and data buffer 58 is omitted.

When fetching an instruction, the CPU 3 outputs an instruction address to a 32-bit instruction address bus 30 and fetches the instruction output to an instruction data bus 31. The CPU 3 outputs a data address to the 32-bit data address bus 32 and reads (loads) data via the 32-bit data bus 33.
Data is written (stored) via a 32-bit data bus 34. The instruction address and the data address are logical addresses.

The FPU 2 is not particularly limited, but does not have a memory addressing capability for accessing the data cache memory 42 and the like. CPU3 is FP
An addressing operation for accessing data is performed in place of U2. This is to eliminate the need for the memory addressing circuit of the FPU 2 and save chip area. Loading of data to the FPU 2 is performed via a 32-bit data bus 33 and a 32-bit data bus 35, and storage of data from the FPU 2 is performed via a 64-bit data bus 36. Data transfer from the FPU 2 to the CPU 3 is performed using the lower 32 bits of the 64-bit data bus 36.

CPU 3 not only fetches data for FPU 2 but also fetches all instructions for FPU 2 including floating point instructions. The floating-point instruction fetched by the CPU 3 is supplied from the CPU 3 to the FPU 2 via a 32-bit data bus 34.

Although not particularly limited, the microcomputer 231 handles a virtual address space defined by a 32-bit virtual address and a physical address space defined by a 29-bit physical address. Address conversion information for converting a virtual address to a physical address includes a virtual page number and a corresponding physical page number. The address conversion table is formed in the SDRAM 232 arranged outside the microcomputer 231. Of the address translation information in the address translation table, the one recently used is the instruction TLB 40 and the unified TLB 41.
Will be stored. The control is performed by, for example, an operating system (OS).

The data unified TLB 41 stores up to 64 entries of address conversion information of data and instructions. The unified TLB 41 performs an associative search of the physical page number corresponding to the virtual page number of the virtual address output to the data address bus 32 by the CPU 3 for data fetch from the address conversion information, and converts the virtual address into a physical address. .

The instruction TLB 40 for instructions stores up to four entries of address conversion information dedicated to instructions. In particular, the entry held by the instruction TLB 40 is a unified TLB
41 is a part of the address conversion information of the instruction address held. That is, if it is found by the associative search that there is no target address translation information in the instruction TLB 40, the address translation information is supplied from the unified TLB 41 to the instruction TLB 40. The instruction TLB 40 performs an associative search from the address conversion information for a physical page number corresponding to a virtual page number of a virtual address output from the CPU 3 to the instruction address bus 30 for instruction fetch. As a result of the search, if there is target address translation information (TLB hit), the virtual address is translated into a physical address using the address translation information. As a result of the search, if there is no target address translation information (TLB miss), the cache TLB controller 44 controls an operation for obtaining the target address translation information from the unified TLB 41.

In the data cache memory 43,
One area including a data storage area, a tag area for storing address information related to the data, a dirty bit indicating that the content of the data has been updated, and a valid bit indicating validity of the data. A cache block is formed.

When a task managed by the operating system is being executed by the CPU 3, the data cache memory 43 receives the physical address converted by the unified TLB 41 at the time of data fetch, and based on the received physical address, associates the cache entry with the physical address. Perform a search. If the search result is a read hit, data corresponding to the physical address is output to the data bus 33 or 35 from the cache block related to the hit. If the search result is a read miss, data for one cache block including the data related to the miss is read from the SDRAM 232 via the bus state controller 5, and cache filling is performed. As a result, data relating to the cache miss is read out to the bus 33 or 35. When the search result is a write hit, if the cache operation mode is the write-back mode, data is written to the hit entry and the dirty bit of the entry is set. The dirty bit in the set state indicates the state of inconsistency with the data of the SDRAM 232,
When the dirty cache entry is evicted from the cache memory in the cache fill operation, S
Write back to the DRAM 232 is performed. In the write-through mode, data is written to the hit entry and data writing to the SDRAM 232 is also performed. If the search result is a write miss, the cache fill is performed in the copy back mode, the dirty bit is set, the tag address is updated, and the data is written to the cache block where the fill was performed. In the case of the write-through mode, writing is performed only on the SDRAM 232.

When the task managed by the operating system is not executed by the CPU 3, as described later in detail, the data in the data cache memory 43 is stored in a state where the valid bit is valid for the block in which the dirty bit is valid. To SDRAM2
Write back to 32.

The instruction cache memory 42 receives the physical address converted by the instruction TLB 40 at the time of instruction fetch, and performs an associative search for a cache entry based on the physical address. If the search result is a read hit, an instruction corresponding to the physical address is output to the instruction data bus 31 from the cache block related to the hit. If the search result is a read miss, the data for one cache block including the instruction related to the miss is stored in the bus state controller 5.
Is read from the SDRAM 232 to perform a cache fill. Thereby, the instruction relating to the miss is provided to the CPU 3 via the instruction data bus 31.

The above-mentioned instruction TLB 40, unified TLB
41 and the cache TLB controller 44 constitute a memory management unit. This memory management unit can set the access right to the virtual address space in each of the privileged mode and the user mode to protect the memory. For example, the address conversion information has protection key data for each virtual address page number. The protection key data is 2-bit data representing a page access right by a code, and is readable only in the privileged mode, readable and writable in the privileged mode,
Only reading is possible in both the privileged mode and the user mode, and any of the read and write access rights is settable in both the privileged mode and the user mode. If the actual access type violates the access right set by the protection key data, a TLB protection violation exception is generated. When a TLB protection violation exception occurs, for example, after the protection violation is resolved by exception processing,
The return instruction from the exception processing is executed, and the interrupted normal processing instruction is executed again.

FIG. 3A shows a flow of main processing when a task managed by the operating system is not executed.

A program for efficiently executing and managing the processing units (tasks) of the CPU is called a scheduler. When the program is started, a scheduling process becomes possible. It is determined whether there is a task that can be executed after the start of the scheduling process (S31, S31).
32). In this determination, when it is determined that there is a task that can be executed (YES), the task is executed (S33). If it is determined in step S32 that there is no executable task (NO), a write-back process is performed before entering the idle state (S34). After the write-back process is performed, an idle process is performed.
U3 is shifted to a low power consumption mode to reduce power consumption (S35). When an event occurs in the low power consumption mode, a corresponding task is executed (S36). Here, according to the related art, when there is no task to be executed, the CPU is shifted to an idle state in order to reduce power consumption, but in this example, before shifting to the idle state, Write-back to the SDRAM 232 is performed, and after that, the SDRAM 232 is shifted to an idle state. This is to reduce a decrease in system performance in caching by performing write-back processing using a period in which memory access is not performed by the CPU 3.

FIG. 3B shows the write-back processing (S
34) is shown.

In the write-back process (S34),
First, dirty bits for one block are checked (S341). In this check, it is determined from the logic state of the dirty bit whether or not it is dirty (S3).
42). If it is determined in step S342 that the block is dirty (YES), the SDRA is performed on the block with the valid bit enabled.
Write back to M232, and then clear the dirty bit in the block (S343). Then, it is determined whether or not the processing has been completed for all the blocks (S344). If it is determined that the processing has not been completed for all the blocks (NO), the process returns to the determination in step S341. If it is determined in step S344 that the processing for all the blocks has been completed (YES), the write-back processing ends. still,
If it is determined in step S342 that the data is not dirty (NO), it means that the data in the data cache memory 43 has not been updated. Then, the process proceeds to the determination in step S344.

FIG. 2 shows the flow of main processing when the task is being executed in step S33.

When a read or write request for a certain address is requested from the CPU 3 (S11), it is determined whether or not the data of the address exists in the data cache memory 43 (S12). In this determination, the data of the corresponding address is stored in the data cache memory 4
3 (YES), it is determined whether the data is read or written. In this determination,
If it is determined to be “read”, the data on the data cache memory 43 is passed to the CPU 3. If it is determined in step S13 that the data is to be written, the data in the data cache memory 43 is changed to the data received from the CPU 3 (S15). Then, the dirty bit is set for the corresponding block (S16), and the system waits for a request from the CPU 3 (S24).

In the determination in step S12, the data at the corresponding address is
3 (NO), a cache memory block to be replaced is selected (S3).
17). Then, it is determined whether the corresponding block is dirty (S18). In this determination, when it is determined that the corresponding block is dirty (YES),
The data of the corresponding block is written back to the SDRAM 232 (S19). Then, the corresponding address data for the cache memory block is read from the SDRAM 232 (S20), and the process proceeds to the determination in step S13.

FIG. 9 shows the microcomputer 231.
Shows the state of the memory access in.

As shown in FIG. 9, when the first block in the SDRAM 232 is accessed by the CPU 3 and the data in the data cache memory 43 is changed at this time, when there is no task that can be executed, Write-back is performed before entering the idle state. Since the write-back is performed in this manner, when the next event occurs, the SDRAM 2
Since it is possible to access the second block in the SDRAM 232 without performing the write-back to the first block in 32, it is possible to reduce the performance degradation due to the write-back.

According to the above example, the following functions and effects can be obtained.

(1) SDRAM 232 by CPU 3
Is accessed at this time, and at this time, assuming that the data in the data cache memory 43 has been changed, when there is no longer any task that can be executed,
Because write back is performed before entering the idle state,
When the next event occurs, the SDRAM 232
It is possible to access the second block in the SDRAM 232 without performing the write-back to the first block in the above, so that a decrease in system performance due to the write-back can be reduced. That is, when there are no more tasks that can be executed by the CPU 3, the CPU 3 does not immediately shift to the idle state.
32, and then transitions to the idle state, so that S
Without writing back the DRAM 232, the SD
Since new caching of the RAM 232 is performed, a decrease in system performance due to write-back can be reduced.

(2) Since the write back is controlled by the operating system, the operating system may be changed, and the microcomputer 23
No change in hardware configuration is required.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, write-back processing can be performed by hardware. FIG. 4 shows a main configuration of a microcomputer when the write-back processing is performed by hardware. In FIG. 4, the configuration other than the cache TLB controller 44 is the same as that shown in FIG.

The microcomputer 23 shown in FIG.
1, the cache controller 44 includes a write-back control circuit 44a, a bus state control circuit 44b,
A configuration including the cache control circuit 44c is applied.

The bus state monitoring circuit 44b detects a period during which the SDRAM 232 is not being accessed by the CPU 3 by monitoring the state of the bus from the control state of the bus controller 5. Write-back control circuit 4
4a, when a dirty block exists in the data cache memory 43, a write-back command signal to the cache control circuit 44c during a period in which the SDRAM 232 is not accessed, based on the bus monitoring result by the bus state monitoring circuit 44b. give. The cache control circuit 44c includes a register for holding a flag indicating that at least one dirty block exists in the data cache memory 43. When a block in the cache memory 43 is dirty, the flag is set. Therefore, whether or not the dirty block exists can be known from the state of the flag in the cache control circuit 44c. Write-back control circuit 44a
Starts write-back control in accordance with the flag state in the cache control circuit 44c. In this write-back control, a write-back instruction signal is asserted based on the bus monitoring result by the bus state monitoring circuit 44b. The cache control circuit 44c has a basic control function as a cache TLB controller. The cache control circuit 44c controls the write back of the data cache memory 43 based on the write back instruction signal given from the write back control circuit 44a.

FIG. 5 shows a flow of the operation of the cache controller 44 shown in FIG.

When a read or write request for a certain address is requested from the CPU 3 (S11), it is determined whether or not the data of the address exists in the data cache memory 43 (S12). In this determination, the data of the corresponding address is stored in the data cache memory 4
3 (YES), it is determined whether the data is read or written. In this determination,
If it is determined to be “read”, the data on the data cache memory 43 is passed to the CPU 3. If it is determined in step S13 that the data is to be written, the data in the data cache memory 43 is changed to the data received from the CPU 3 (S15). Then, the dirty bit is set for the corresponding block (S16), and the system waits for a request from the CPU 3 (S24).

In the determination in step S12, the data at the corresponding address is
3 (NO), a cache memory block to be replaced is selected (S3).
17). Then, it is determined whether the corresponding block is dirty (S18). In this determination, when it is determined that the corresponding block is dirty (YES),
The data of the corresponding block is written back to the SDRAM 232 (S19). Then, the corresponding address data for the cache memory block is read from the SDRAM 232 (S20), and the process proceeds to the determination in step S13.

On the other hand, the status of the external address bus 60 is monitored by the bus status monitoring circuit 44b, whereby it is possible to know the period during which the SDRAM 232 is not being accessed by the CPU 3. The write-back control circuit 44a uses the bus state monitoring circuit 44b to
When it is confirmed that the DRAM 232 is not being accessed, the write back instruction signal is asserted. As a result, the cache control circuit 44c determines whether a dirty block exists (S22). If it is determined in this determination that a dirty block exists (Yes), write back to the SDRAM 232 with the valid bit of the cache block being valid, and then clear the flag of the corresponding dirty bit (S23). ). If it is determined in step S22 that there is no dirty block, the process shifts to a state of waiting for the next request from the CPU 3 without performing the write-back in step S23 (S23).
23).

As described above, since the write-back is performed using the period during which the SDRAM 232 is not accessed, for example, as shown in FIG. 9, when an event occurs, it is not necessary to perform the write-back. It is possible to reduce the performance degradation of the system due to the back.

In the above description, the invention made mainly by the present inventor is described in the field of application RIS, which is the background of the invention.
The case where the present invention is applied to a microcomputer having the C architecture has been described, but the present invention is not limited to this, and can be widely applied to various microcomputers.

The present invention can be applied on the condition that it has at least a cache system.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, while the task managed by the operating system is not being executed, the data in the cache memory is written back to the memory with the valid bit being valid for the block where the dirty bit is valid. If two consecutive events are different from each other, caching is required for a second block different from the data of the first block used last time, but the task managed by the operating system is being executed as described above. Since the write-back process is executed during the non-period, the number of cases in which the previously used cache contents are written back immediately before caching for the second block is reduced, thereby reducing the system performance degradation. Is done.

Further, by monitoring a bus used for memory access, a period during which the central processing unit does not access the memory is detected, and a write-back process is performed during the period when the memory is not accessed. , A second block different from the data of the first block used last time
When caching is required for a block, the number of cases in which the cache contents used last time are written back immediately before the caching is reduced, so that the performance degradation of the system is reduced accordingly.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a microcomputer according to the present invention.

FIG. 2 is a flowchart when a task managed by an operating system is executed in the microcomputer.

FIG. 3 is a flowchart when a task managed by an operating system is not executed in the microcomputer.

FIG. 4 is a block diagram illustrating another configuration example of the microcomputer according to the present invention.

FIG. 5 is a flowchart of a main operation in the microcomputer shown in FIG. 4;

FIG. 6 is an explanatory diagram of a state of a CPU in the microcomputer.

FIG. 7 is another state explanatory diagram of the CPU in the microcomputer.

FIG. 8 is another state explanatory diagram of the CPU in the microcomputer.

FIG. 9 is a diagram illustrating an example of a state of memory access in the microcomputer according to the present invention.

FIG. 10 is a block diagram illustrating an overall configuration example of a data processing device to which the microcomputer is applied.

[Explanation of symbols]

 3 CPU 4 Address conversion / cache unit 5 Bus state controller 6 External bus interface 40 Instruction TLB 41 Unified TLB 42 Instruction cache memory 43 Data cache memory 44 Cache TLB controller 44a Write-back control circuit 44b Bus state monitoring circuit 44c Cache control circuit 231 Microcomputer 232 SDRAM 234 ROM 235 Peripheral device control unit 236 Display control unit 237 Display 238 External storage device 239 Keyboard

Claims (4)

[Claims] 1. A storage area for data, a tag area for storing address information related to the data, a dirty bit indicating that the content of the data has been updated, and a valid bit indicating validity of the data. And a cache system that enables a read cache and a write cache of a memory in which the data is stored, and a dirty bit during a period in which a task managed by an operating system is not executed. And a central processing unit capable of writing back the data of the cache system to the memory in a state where the valid bit of the block is valid. 2. A microcomputer comprising: a central processing unit; and a cache system capable of performing a read cache and a write cache of a memory accessible by the central processing unit. A bus state monitoring circuit capable of detecting a period during which the memory is not accessed by the central processing unit by monitoring a bus used; and accessing the memory based on a detection result of the bus state monitoring circuit. A write-back control circuit for instructing the start of a write-back process during a period in which the write-back process is not performed. 3. The write-back control circuit includes a register capable of setting a flag indicating that a dirty block exists in the cache system, and the write-back control circuit sets a state of the flag set in the register. 3. The microcomputer according to claim 2, wherein write-back control is started according to the following. 4. A data processing device comprising: the microcomputer according to claim 1; and a memory arranged outside the microcomputer and accessible by the microcomputer.