JPH11134077A - Processor and system for data processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor which properly control the power consumption state of an built-in module according to whether or not dynamically changed operation is necessary. SOLUTION: Hit information(HIT) indicating a cache miss of a cache memory (4) is referred to and only when a bus controller (7) and an external interface circuit (90) need to be placed in operation, clock signals (ICLK, BCLK, and PCLK) are supplied to those circuits, but in a state of a cache hit where no external access is needed, the supply of the clock signals to the bus controller, external interface circuit, etc., is stopped. Consequently, the power consumption states of the bus controller, input/output circuit, etc., can properly be controlled according to whether or not operation dynamically changed according to the state of the cache memory is necessary and the power consumption of the data processor with the built-in cache memory can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus formed on a single semiconductor substrate such as a single-chip microcomputer, a single-chip microprocessor, or a single-chip controller, which is dynamically reduced in consumption according to the operation state thereof. The present invention relates to a technique for increasing power, for example, to a technique effective when applied to a microprocessor having a built-in cache memory.

[0002]

2. Description of the Related Art As a technique for reducing the power consumption of a microprocessor, a central processing unit sets control data in a predetermined control register or the like in accordance with an operation program thereof, so that the operation of each built-in module and the stop of the operation of the module are controlled. Japanese Patent Application Laid-Open No. Hei 7-2876 discloses a technique for enabling static control.
No. 99 is disclosed. For example, the supply of the clock signal is stopped to the built-in module selected to stop the operation. Here, "static" means that once the operation or the stop of the operation is determined according to the operation program of the central processing unit, the state is maintained until it is canceled according to the operation program.

In addition, due to a CPU mishit, the frequency of a clock signal supplied to an external peripheral circuit device is changed from a low frequency (low power consumption mode) to a high frequency (normal mode).
A multi-chip microcomputer system for changing to the above is disclosed in JP-A-7-287699.

[0004]

However, in the actual operation of the microprocessor, the built-in modules which need or do not operate dynamically change according to the operation state of the microprocessor. That is, it is often impossible to directly specify which built-in module is operated and which built-in module is not required to be operated by the operation program of the central processing unit. For example, in a microprocessor having a built-in cache memory, when a central processing unit executes a load instruction or a store instruction, and in the case of a cache hit, the central processing unit operates without operating a bus controller or an external interface circuit for accessing an external memory. The processing device can execute the instruction. On the other hand, in the case of a cache miss, the central processing unit operates the bus controller and the external interface circuit to access the external memory. It is practically impossible to directly predict or control whether or not a cache hit will occur from the operation program of the central processing unit.

For this reason, there is no idea to appropriately stop the operation of the built-in module whose operation is unnecessary or the required state changes dynamically according to a cache hit, and the power consumption of the microprocessor is unnecessarily increased in this regard. There is a problem of causing. In particular, when a cache memory is built-in, a high cache hit rate contributes to the improvement of data processing performance.However, as the cache hit rate increases, the bus controller and the external interface circuit need to access the external memory. It has been found by the inventor that the frequency of use is reduced and that continually supplying an operational clock signal to these circuits to enable operation significantly increases the wasteful power consumption.

Some cache memories have a lock function that prohibits replacement of all or a part of cache entries held by the associative memory unit. By loading data or instructions necessary for specific data processing into the cache memory in advance and locking the cache memory, a specific data processing always results in a cache hit and a certain data processing time is guaranteed, real-time control, etc. Can be handled. However, since the microprocessor does not have a means for specifying the period during which the central processing unit accesses data and instructions held by such a cache memory in the locked state, as described above, even when cache hits continue, The inventor has also found that the clock signal is continuously supplied to the controller and the external interface circuit, which wastes power.

An object of the present invention is to appropriately adjust the power consumption state of a built-in module according to the unnecessary or necessary state of an operation dynamically changed in response to a cache hit, cache mishit or an access request signal of a cache memory. To provide a data processing apparatus capable of reducing power consumption by controlling the data processing.

Another object of the present invention is to provide a data processing device capable of reducing the power consumption by stopping the operation of the built-in module which does not need to operate during the period when the cache memory is locked. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in a data processing device including a central processing unit (2) and a cache memory (4), hit information (HIT) for indicating a cache miss state of the cache memory is referred to, and the hit information (HIT) is referred to. When the hit information indicates a cache miss, the internal circuit in the operation unnecessary state is shifted to the low power consumption state, and when the hit information indicates a cache miss, the low power consumption state of the internal circuit in the low power consumption state is released. Control means (70) for performing dynamic low power consumption control. The low power consumption state of the internal circuit can be achieved by stopping the supply of clock signals (ICLK, PCLK, BCLK) to the internal circuit. The circuits to be subjected to the dynamic low power consumption control include, for example, a bus controller (7) connected to a cache memory and controlling a bus cycle for an external or peripheral circuit, and an input connected to the bus controller and interfaced with the outside. An output circuit (90).

According to the above-described means, when the cache memory changes to the cache hit state, the bus controller and the input / output circuit are controlled by the DMAC (Direct Memory Access Controller).
If no operation is performed for other circuit modules such as a controller (direct memory access controller), the supply of the clock signal to the bus controller, the input / output circuit, and the like is stopped and the power consumption is reduced.
On the other hand, when the bus controller or the input / output circuit is in the low power consumption state, or when the cache memory changes to the cache miss state, the supply of the clock signal to the bus controller or the input / output circuit is resumed to reduce the power consumption state. Cancel. As described above, the power consumption state of the bus controller and the input / output circuit can be appropriately controlled according to the operation unnecessary or necessary state dynamically changed according to the state of the cache memory, and the data processing with the built-in cache memory can be appropriately performed. The power consumption of the device can be reduced.

In the above data processing apparatus, static low power consumption control can also be performed on the peripheral circuit module. For example, there is provided control register means (STBCR1, STBCR2) in which control information for instructing supply and stop of a clock signal for synchronous operation to peripheral circuit modules is set by the central processing unit.
The central processing unit sets the peripheral circuit module (8,
The clock supply to 10) is statically controlled.

In a data processing apparatus equipped with a cache memory capable of selecting a lock function, a control means for controlling an internal circuit which does not require operation when the lock function is selected in the cache memory to a low power consumption state. (70) can be adopted. When the lock function is selected, the cache memory prohibits the replacement of all or a part of the cache entries held by the associative memory unit, and the cache hit continues as long as the central processing unit continues to access the entry for which the replacement is prohibited. I do. When the lock function is selected, such access is generally performed. Therefore, in the locked state, the bus controller and the input / output circuit do not need to perform external access. Therefore, in the locked state, by stopping the supply of the clock signal to the bus controller, the input / output circuit, and the like, it is possible to prevent unnecessary power consumption in those circuits. Therefore, it is possible to reduce the power consumption of the data processing device including the cache memory supporting the lock function.

In the data processing apparatus employing the means for reducing power consumption focusing on the lock function, the data processing apparatus further refers to hit information for indicating a cache miss state of the cache memory, which indicates a cache miss. Means for causing the internal circuit in an operation unnecessary state to transition to a low power consumption state when there is no means for releasing the low power consumption state of the internal circuit in the low power consumption state when the hit information indicates a cache miss, It is also possible to adopt at the same time.

A data processing apparatus according to another aspect of the present invention refers to an access request signal (REQ2) from the cache memory to the bus controller instead of the hit information of the cache memory, which indicates an access request. When the access request signal indicates an access request, cancels the low power consumption state of the internal circuit in the low power consumption state when the internal circuit in the operation unnecessary state transitions to the low power consumption state when not in operation. Control means for performing dynamic low power consumption control can be employed. As described above, similarly to the above, it is possible to appropriately control the power consumption state of the bus controller and the input / output circuit according to the operation unnecessary or necessary state dynamically changed according to the state of the cache memory, and to incorporate the cache memory. The power consumption of the data processing device can be reduced. However, the access request signal (REQ2) from the cache memory to the bus controller corresponds to the cache memory hit information (H
IT) issues an access request in response to a cache miss. Therefore, care must be taken that the timing of releasing the low power consumption state is delayed as compared with the case where the hit information of the cache memory is directly referred to.

Here, data processing devices having a built-in cache memory tend to increase the cache hit rate by increasing the capacity of the cache memory and the like, thereby improving the data processing capability. As the cache hit ratio increases, the frequency with which the bus controller and the external interface circuit are used for accessing the external memory decreases drastically. Considering this, when the cache memory is not in the cache miss state, stopping the supply of the clock signal to the bus controller, the external input / output circuit, and the like significantly reduces the power consumption of the data processing measures. Can be expected.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

<< Microcomputer >> FIG. 2 is a block diagram of a data processing device such as a single-chip microcomputer (single-chip microprocessor, single-chip microcontroller) according to an embodiment of the present invention. Microcomputer (MPU) 1 shown in FIG.
Is a single semiconductor substrate (semiconductor chip) made of, for example, single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
Formed. Although not particularly limited, the microcomputer 1 includes a local bus L-bus and an internal bus I-bus.
bus and a peripheral bus P-bus. These buses are provided with data, address, and control signal lines.

A central processing unit (CPU) 2 and a digital signal processor (D) are connected to the local bus L-bus.
SP) 3, cache memory (CACHE) 4, address translation unit (MMU: also referred to as memory management unit) 5, and clock pulse generator (CP
G) 14 is combined. The cache memory 4 is connected on the other hand to the internal bus I-bus.
The bus is connected to a write-back buffer (WBBUF) 6 and a bus controller (BSC) 7. The bus controller 7 is connected to an external input / output circuit (EXIF) 9 and the peripheral bus P-bus. The external input / output circuit 9 can be interfaced with an external bus EX-bus having signal lines for address, data and control signals. An external memory (MMRY) 20 is representatively shown on the external bus EX-bus. The peripheral bus P-bus includes, for example, a direct memory access controller (DMA) as a peripheral module.
C) 8 and other peripheral circuits PMD10.

The microcomputer 1 is operated in synchronization with a clock signal 15 output from a clock pulse generator (CPG) 14. The CPU 3 and DM
AC8 constitutes a bus master module. The other peripheral circuits 10 include, but are not limited to, a serial communication interface controller, a real-time clock circuit, and a timer circuit. The peripheral circuit 10 is connected to the CPU 2 or D via the bus controller 7.
Accessed by MAC8.

Although the central processing unit 2 is not particularly limited,
An operation unit represented by a general-purpose register and an arithmetic logic unit;
It includes a control register group such as a program counter, and an instruction control unit that controls an instruction fetching and decoding, an instruction execution procedure, and an arithmetic control. Central processing unit 2
Fetches an instruction from the external memory 20 or the like, and decodes the instruction with an instruction decoder to perform data processing corresponding to the instruction.

The digital signal processor 3
Is connected via its dedicated buses X-bus and Y-bus.
Memory (XMEM) 11 and Y memory (YMEM) 12
Connected to. The X memory 11 and the Y memory 12 are also interfaced to the internal bus I-bus. The memory controller (MCNT) 13 includes the X memory 11 and the Y memory 1
Access request from DSP 3 to internal bus I-
It monitors access requests from the bus side and arbitrates access requests. The memories 11 and 12 are a CPU 2
It can also be used as a work area. CPU2
Not only fetches data for DSP3, but also fetches all instructions, including fixed-point instructions for DSP3.

Although not particularly limited, the microcomputer 1 handles a virtual address space defined by a 32-bit virtual address and a physical address space defined by a 29-bit physical address. Address conversion information for converting a virtual address to a physical address includes a virtual page number and a corresponding physical page number. The address conversion table 21 is formed in the external memory 20 of the microcomputer 1. Of the address translation information in the address translation table 21, the one recently used is stored in the address translation buffer (TLB) 50. The address conversion buffer 50 has address conversion information of data and instructions, and converts a physical page number corresponding to a virtual page number of a virtual address output to the local bus L-bus by the CPU 2 for data fetch or instruction fetch from the address conversion information. Perform an associative search. As a result of the search, if there is target address translation information (TLB hit), the virtual address is translated into a physical address using the address translation information. As a result of the search, when there is no target address conversion information (TLB miss), the target address conversion information is read from the address conversion table 21 on the external memory 20. The above address conversion operation is TL
It is controlled by a B control unit (TLB-C) 51.

Although not particularly limited, the cache memory 4 is a cache memory unit (CACHE-M) 40 as a 4-way set associative type associative memory unit.
And a cache control unit (CACHE-C) 41.
The index for the cache memory unit 40 is performed by using a part of the logical address. The tag part of the entry holds the physical address, and the indexed tag part is the physical address obtained by converting the logical address by the address conversion unit 5. And a cache miss / hit is determined according to the comparison result.

FIG. 3 shows an example of the cache memory 4. The cache memory unit 40 has a memory cell array for configuring a maximum of 256 cache lines, and this memory cell array includes an address array 400 and a data array 401. One cache line includes a cache tag (address tag) CTAG constituted by a physical page number, a valid bit V, a dirty bit U, and 16-byte data LW0 to LW3 corresponding thereto. Cache tag CTAG, valid bit V and dirty bit U are stored in address array 40.
0, the data LW0 to LW3 are arranged in the data array 401. The valid bit V indicates whether valid data is included in the cache line, and is valid with a logical value “1”.
“0” means invalid. The dirty bit U is used when the cache memory 4 is used in the write-back mode, and is set to a logical value “1” when writing occurs in the write-back mode. By this dirty bit U, it is possible to know the mismatch between the data of the corresponding entry and the data of the external memory. This dirty bit U is initialized to a logical value "0" by a power-on reset.

Although not particularly limited, the cache memory section 40 is set associative and has four ways WAY0 to WAY3. As the index address for selecting the cache entry, 8 bits from bit 4 to bit 11 of the logical address signal are used. The index of the cache tag of the cache line of each way is stored in the comparator C included in the cache control unit 41.
It is compared with the corresponding physical page number by MP0 to CMP3. This physical page number is supplied from MMU5. When the cache tag CTAG matches the physical page number and the valid bit V has the logical value “1”, the signals output from the corresponding comparators CMP0 to CMP3 are set to the logical value “1”. The signal is supplied to the corresponding data array, and when it is a logical value "1", the data array 401
The 32-byte cache line data indexed by is selected. The selected cache line data is stored in the selector SE by bits 2 and 3 of the logical address.
Selected by L. The logical sum signal of the signals output from the comparators CMP0 to CMP3 is used as a hit / miss signal 42 of the cache memory.

The cache memory 4 receives the physical address converted by the address conversion unit 5 at the time of data fetch or instruction fetch, and performs an associative search for a cache entry based on the physical address as described above. If the search result is a read hit, data corresponding to the physical address is output from the cache line related to the hit to the local bus L-bus. If the search result is a read miss, data for one cache line including the data relating to the miss is read from the external memory 20 via the bus controller 7 and cache filling is performed. As a result, the data relating to the cache miss is read onto the local bus L-bus. When the search result is a write hit, if the cache operation mode is the copy back mode, data is written to the hit entry and the dirty bit of the entry is set. The inconsistent state with the data in the external memory 20 is known from the dirty bit in the set state. When the dirty cache entry is evicted from the cache memory 4 by the cache fill operation, the write back to the external memory 20 is performed. In the write-through mode, data is written to the hit entry, and data writing to the external memory 20 is also performed. If the search result is a typo,
In copyback mode, cache fill is performed and the dirty bit is set to update the tag address.
Write data to the filled cache line.
In the case of the write-through mode, writing is performed only to the external memory.

A cache fill is an operation of reading data of a cache line from the external memory 20. To write the read data to the cache line, a cache entry is replaced. At this time, if there is an invalid cache entry, the invalid cache entry is replaced. When there is no invalid cache entry, for example, LRU (Least Recently)
The cache entry that has not been used most recently is subject to replacement according to a logic such as Used. The replacement control is performed by the cache control unit 41. The write-back buffer 6 temporarily stores data to be written back to the external memory when performing a cache fill at the time of a cache miss in the cache memory, and prioritizes writing of data related to the cache miss to the associative memory unit 40. is there.

The address space to be cached by the cache memory 4 with respect to the memory space managed by the CPU 2 is not particularly limited, but is determined according to the operation mode of the microcomputer.

The cache memory 4 has a cache lock function. That is, the lock function is a function that can selectively inhibit replacement of all or a part of the cache entries held by the cache memory unit 40. In this example, storage of lock function control information is provided in a cache control register CCR in which control data is set by the CPU 2. The control information for the lock function is a 2-bit lock enable bit LE0, LE1 and a 2-bit lock status bit LST0, LST1, as exemplified in FIG.

Lock enable bits LE0, LE1
Is control information for designating an operation mode when the CPU 2 stores necessary data in the cache memory 4 in advance. LE0, LE1 = 0, 0 instructs to store data in the way indicated by the LRU logic of the cache control unit, LE0, LE1 = 0, 1 instructs to store data in way WAY3, and LE0, LE1 = 1, 0 indicates that data is stored in way WAY2, and LE0, L
E1 = 1,1 is undefined and cannot be set. The operation of storing necessary data in the cache memory 4 in advance is not particularly limited, but a prefetch instruction instructing a store operation to the cache memory unit 40 is issued by the CPU 2.
Is performed.

The lock status bits LST0, LST0
ST1 specifies a way for which replacement is prohibited (cache entry is locked). LST0, LST1 = 0,
0 does not perform the lock operation (four ways WAY0 to WAY0).
All of the way 3 are subject to replacement according to the LRU logic). LST0, LST1 = 0,1
Locks way WAY3 (way WAY0, WAY
LST0, LST1 = 1, 0 locks the way WAY2 (way WAY0, WAY).
1, WAY3 are to be replaced according to the LRU logic), and LST0, LST1 = 1, 1 locks ways WAY3, WAY2 (way WAY).
0, WAY1 are subject to replacement according to the LRU logic). The LRU logic included in the cache control unit 41 includes the lock status bits LST0,
The way specified by the LST1 bit is controlled so as to be excluded from replacement by the LRU.

The bus controller 7 includes a CPU 3 and a D
The access data size, depending on the circuit to be accessed by the MAC 8 (the address area to be accessed),
The bus cycle is controlled by controlling access time and insertion of a wait state.

The microcomputer 1 has a clock signal 15 output from a clock pulse generator 14.
Is operated synchronously. The microcomputer 1 realizes low power consumption control by selectively stopping supply of a clock signal supplied to a predetermined built-in module.
The contents are roughly classified into: first, dynamic low power consumption control using hit information HIT for indicating the cache miss state of the cache memory 4; second, low power consumption reflecting the lock state of the cache memory. Third, power control is static low power consumption control for peripheral circuits. The first
The second low power consumption control is not particularly limited, but is performed by the dynamic clock control circuit 70 included in the bus controller 7 with reference to the hit information HIT and the lock information LOCK from the cache control unit 41. The third low power consumption control is performed by the clock pulse generator 14. Hereinafter, the above three low power consumption controls will be described in detail.

<< Low Power Consumption Control >> FIG. 1 partially shows a detailed configuration of the microcomputer 1 shown in FIG. 2 focusing on the low power consumption control. CPU
2 asserts a request signal REQ1 as a memory access request signal when performing memory access.
The cache control unit 41 enables an associative search of the cache memory unit 40 by asserting the request signal REQ1.

If the result of the associative search is a cache hit, the cache control unit 41 asserts the ready signal RDY1 to the CPU2. Thereby, the CPU 2 reads the data output from the cache memory unit 40 in the case of the read access, and recognizes the completion of the data writing in the case of the write access.

If the result of the associative search is a cache miss, the cache control unit 41 asserts the request signal REQ2 to the bus controller 7 to request activation of bus access such as external memory access. The bus controller 7 responds to the request and activates a bus access to the address related to the cache miss, for example, an external memory access via the external input / output circuit 9. If the cache miss is a read miss, the bus controller 7 reads one cache line of data including the data relating to the miss from the external memory 20, asserts the ready signal RDY2, and transfers one cache line of data to the internal bus I- Output to bus. In response to this, the cache control unit 41 cache-fills the cache memory unit 40, outputs data related to a cache miss to the local bus L-bus, and outputs the ready signal RD
Assert Y1. If the search result at that time is a write miss, in the copy back mode, the same cache fill as described above is performed, the dirty bit is set, the tag address is updated, and the data is written to the filled cache line. In the case of the write-through mode, writing is performed via the bus controller 7 only to the external memory at the address related to the cache miss.

In FIG. 1, the DMAC is not particularly limited.
, A bus request signal BREQ is asserted, and in response to this, a bus acknowledgment signal BACK is asserted to acquire a bus right and start a DMA transfer operation. Although not particularly limited, the DMA transfer operation is performed via the bus controller 7.

FIG. 1 shows a DMAC 8 as a peripheral module.
And other peripheral circuits 10 are representatively shown. The external input / output circuit 9 includes an input / output buffer, a multiplexer for sharing a terminal function, and the like, and forms a so-called I / O port. In FIG. 1, for convenience, the external input / output circuit 9 is connected to an external bus interface port 90 connected to an external bus.
It is divided into an I / O port 91 assigned to an input of an external DMA transfer request signal of the MAC 8 and an I / O port 92 assigned to the peripheral circuit 10.

The clock pulse generator 14 outputs clock signals ICLK, BCLK, and PCLK, and generates a clock signal PCL of a representative peripheral circuit.
K-1, PCLK-2 and BCLK-2 are output. The frequency of the clock signal is ICLK ≧ BCLK (BCLK
-1, BCLK-2) ≧ PCLK (PCLK-1, PC
LK-2). The CPU 2 and the cache memory 4 are operated in synchronization with the clock signal ICLK. The clock signal BCLK (BCLK-1, BCLK-
2) is a synchronous clock signal used at the time of external access. Clock signal PCLK (PCLK-1, PC
LK-2) is a synchronous clock signal for the peripheral module.

The bus controller 7 has an internal bus I-bu
s, peripheral bus P-bus and external input / output circuit 9
Three types of clock signals ICLK, BCLK, and PCLK are supplied due to the nature of interfacing with the clock. A clock signal BCLK,
PCLK is supplied to the I / O port 91 by the clock signal BCL.
K-1 and PCLK-1 are supplied to the peripheral module 10, and clock signals BCLK-2 and PCLK-2 are supplied to the peripheral module 10.

The bus controller 7 has a bus arbitration logic circuit 71, an input / output control logic circuit 72, a control register 73 and a data buffer 74, and further has the dynamic clock control circuit 70 and the like. Control information for determining the operation of the bus controller 7 is set in the control register 73 by the CPU 2. The data buffer 74 is provided to absorb the difference in the operation speed of the access target circuit. The bus right arbitration logic circuit 71 receives the request signals REQ2 from the cache control unit 41 and D
It arbitrates for a bus right request based on the bus request signal BREQ from the MAC 8. When there is a bus request, the input / output control logic circuit 72 controls the activation of the bus cycle according to the access address area or the like. When the input / output control logic circuit 72 does not start a bus cycle, it is set to a module idle state. The module idle state is a state of waiting for a bus access request, and is indicated by a high level of the module idle status signal M-IDL. Module idle status signal M-ID
The low level of L indicates a busy state, and in the busy state, the bus controller 7 has started an access operation.

The dynamic clock control circuit 70 includes a module idle status signal M-IDL (see FIG. 5) indicating whether or not the module is idle, and hit information H.
IT and lock information LOCK are input, and low power consumption control is performed on the bus controller 7 and the external bus interface port 90 according to the state of the input signals.
The hit information HIT is a signal which is set to a low level when the determination result of the cache hit / miss signal 42 in the cache memory 4 is a cache miss. The hit information HIT is used as the request signal REQ2 by inverting the level of the hit information HIT. Lock information LOCK
Are the lock status bits LST0, LST1 =
The level is set to a high level other than 0,0 (the way of the cache memory is locked).

The hit information HIT and the lock information LOC
As shown in FIG. 5, a logical sum of K is obtained by a logical sum gate OR, and a logical product of the logical sum signal and the module idle status signal M-IDL is obtained by an AND gate AND. This AND signal is used as the stop signal STP. The stop signal STP is provided to the clock driver 75 of the bus controller 7 illustrated in FIG. Outputs of the clock driver 75 are clock drivers 75A to 75A.
It is distributed to each internal circuit in the bus controller 7 via 5D. Further, the stop signal STP is
It is also provided to the clock driver 901 of the external bus interface port 90. When the stop signal STP is at a high level, the clock drivers 75 and 901 receiving the stop signal STP
Etc. fix its output to high level or low level,
The supply of the clock signal to the subsequent stage is stopped. Thus, the change of the internal clock signals of the bus controller 7 and the bus interface port 90 is stopped during the high level period of the stop signal STP. When the change of the internal clock signal is stopped, the power consumption of the bus controller 7 and the internal circuits of the external interface port 90 is reduced. Here, the circuit portion of the bus controller 7 where the supply of the internal clock signal is stopped is not limited to all the internal circuits of the bus controller 7. Only a circuit portion that performs external bus control via the external interface port 90 may be used. Further, at this time, when the bus controller 7 includes a refresh controller of a DRAM (Dynamic Random Access Memory), and the DRAM is connected to the outside, the refresh controller is excluded from dynamic clock control.

FIGS. 6 and 7 show an example of a timing chart when the supply of the clock signal is stopped in accordance with the hit information HIT or the like. When a cache miss occurs at time t0 in the module idle state, the hit information HIT indicates the cache miss state in synchronization with this,
The supply of the clock signal to the bus controller 7 and a predetermined internal circuit of the external input / output circuit 9 is started. Thereafter, at time t1, the cache is hit, but the module idle status signal M-IDL is busy. This is a state where, for example, the DMAC 8 uses the bus controller 7. In this state, the supply of the internal clock signal to the bus controller 7 and the like is not stopped. At time t2, the module idle status signal M-IDL is set to the idle state. At this time, the supply of the clock signal to predetermined internal circuits such as the bus controller 7 is stopped because the hit information HIT does not indicate the cache miss state.

In the state shown in FIG. 7, in the cache hit state, the hit information HIT does not indicate a cache miss state, and the module idle status signal M-IDL is in a busy state. In this case,
The supply of the clock signal is not stopped.

FIG. 8 shows a processing flow when the lock function of the cache memory is used. First, the CPU 2 sets the lock enable LE0, LE1 of the register CCR and designates a way to store data (S
1). The CPU 2 executes the prefetch instruction and stores the data in the designated way (S2). Then C
PU2 sets the lock status bits LS0 and LS1, and selects the lock operation (S3). This prohibits the cache memory 4 from replacing the designated way. During this time, the lock information LOCK is set to the high level, the supply of the clock signal to the internal circuits in the bus controller 7 and the external bus interface port 90 is stopped, and wasteful power consumption is suppressed (S
4). This state is a period from time t0 to time t1 in FIG. The lock function is released by the lock status bit LS
An instruction is given by setting T0, LST1 = 0, 0 (S5), whereby the lock information LOCK is negated to a low level, and the cache memory operates normally (S6).

As described above, the dynamic clock control circuit 70
When the hit information HIT does not indicate a cache miss state, the bus controller 7 and the input / output circuit 9
If the operation is not performed for the MAC 8 or the like, the supply of the clock signal to predetermined internal circuits such as the bus controller 7 and the input / output circuit 9 is stopped, and a low power consumption state is set. When the cache memory 4 turns into a cache miss when the bus controller 7 or the input / output circuit 9 is in the low power consumption state, the dynamic clock control circuit 70 outputs a clock signal to the bus controller 7 or the input / output circuit 9 or the like. Is restarted to release the low power consumption state. in this way,
A microcomputer 1 having a built-in cache memory that can appropriately control the power consumption state of the bus controller 7 and the input / output circuit 9 according to the operation unnecessary or necessary state dynamically changed according to the state of the cache memory 4. Power consumption can be reduced.

When the lock function is selected for the cache memory 4, the cache memory 4 prohibits the replacement of all or a part of the cache entries held by the cache memory unit 40 during that time. Cache hits continue as long as access continues. When the lock function is selected, it is common to make an access such that cache hits are continuous, and therefore, the cache memory 4
In the locked state, there is no need for the bus controller 7 and the input / output circuit 9 to perform external access. Therefore,
The dynamic clock control circuit 70 stops the supply of the clock signal to the bus controller 7 and the input / output circuit 9 in the locked state of the cache memory 4 based on the lock information LOCK. It can be prevented from being consumed.

Further, the microcomputer 1 having the built-in cache memory 4 tends to increase the cache hit rate by increasing the capacity of the cache memory 4 and improve the data processing capability. Thus, the frequency with which the bus controller 7 and the external interface circuit 9 are used for external memory access is reduced. In view of the above tendency of the microcomputer 1, it is clear that the power consumption of the microcomputer 1 can be significantly reduced by the dynamic clock supply control by the above means.

The clock pulse generator 14 comprises:
An oscillation circuit, a frequency divider, a clock driver, and clock control registers STBCR1 and STBCR2 are provided. FIG.
To 0, the clock control registers STBCR1, STBCR
Two examples are shown. MSTP0 to MSTP8 are DMA
This is a control bit assigned to a peripheral circuit module represented by C8. When "1" is set, the corresponding clock gate is fixed at a predetermined value. For example MS
When TP1 is set to the logical value "1", the clock pulse generator 14 outputs the clock signals PCLK-1 and BCLK-.
1 is fixed to a constant value. When MSTP2 is set to the logical value "1", the clock pulse generator 14 fixes the outputs of the clock signals PCLK-2 and BCLK-2 to a constant value. Thus, the clock supply to each peripheral circuit can be statically controlled, and the static low power consumption control of the peripheral circuit can also be performed.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, in the above embodiment, the hit information HIT
, Dynamic low power consumption control is performed, but the request signal REQ2 may be used instead. As described above, the power consumption state of the bus controller 7 and the input / output circuit 9 can be appropriately controlled according to the operation unnecessary or necessary state dynamically changed according to the state of the cache memory 4 as described above. 4 can reduce the power consumption of the microcomputer incorporating the same. However,
As described above, the access request signal REQ2 from the cache memory 4 to the bus controller 7 indicates an access request in response to the hit information HIT of the cache memory 4 indicating a cache miss. Therefore, it should be noted that the timing of releasing the low power consumption state is delayed as compared with the case where dynamic clock stop control is performed by directly referring to the hit information HIT of the cache memory 4.

The replacement logic is not limited to the LRU logic, and another logic such as a random logic can be adopted.

The object of the dynamic clock stop control can be extended to peripheral circuit modules. For example, in the case of a peripheral circuit module in which activation control is performed by a CPU, a clock signal can be supplied to the peripheral circuit module in response to an activation request, and the supply of the clock signal can be stopped when the operation is completed.

The circuit part in which the supply of the clock signal is stopped by the dynamic clock stop control in the bus controller can be appropriately changed. Further, the dynamic low power consumption control is not limited to the clock signal supply stop control, and it is also possible to realize low power consumption by supplying power to the internal circuit or dynamically controlling the power supply voltage of the internal circuit. is there.

[0057]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by referring to hit information for indicating a cache miss of the cache memory or an access request signal to the bus controller, a clock signal is supplied to the bus controller and the external interface circuit only when the operation of the circuit is necessary. However, the supply of the clock signal to the bus controller, the external interface circuit, and the like can be stopped in a cache hit state that does not require external access. Therefore, it is possible to appropriately control the power consumption state of the bus controller and the input / output circuit according to the operation unnecessary or necessary state dynamically changed according to the state of the cache memory. Power consumption can be reduced.

Further, by using static low power consumption control for the peripheral circuits, wasteful power consumption can be further reduced.

When a cache memory capable of selecting a lock function is mounted, a control means for controlling an internal circuit which does not need to operate when the lock function is selected in the cache memory to a low power consumption state is employed. Thus, when the lock function is selected, it is possible to reduce power consumption in the bus controller and the input / output circuit which does not substantially require an operation for external access.

[Brief description of the drawings]

FIG. 1 is a block diagram showing in detail a circuit portion related to low power consumption control in a microcomputer according to an example of the present invention.

FIG. 2 is a block diagram showing an entire microcomputer according to an example of the present invention.

FIG. 3 is a block diagram illustrating an example of a cache memory 4;

FIG. 4 is a format diagram of a control register used for setting a lock function of a cache memory.

FIG. 5 is an explanatory diagram showing an example of a specific logical configuration for dynamic clock stop control.

FIG. 6 is a timing chart showing an example when stopping supply of a clock signal based on hit information and a module idle status signal.

FIG. 7 is a timing chart showing an example of a case where supply of a clock signal is not stopped based on hit information and a module idle status signal.

FIG. 8 is a flowchart illustrating an example of a control procedure when the lock function of the cache memory is used.

FIG. 9 is a timing chart illustrating an example of a case where supply of a clock signal is stopped using lock information.

FIG. 10 is a format diagram illustrating an example of a clock control register.

[Explanation of symbols]

Reference Signs List 1 microcomputer 2 CPU 4 cache memory 40 cache memory unit 41 cache control unit CCR cache control register HIT hit information LOCK lock information M-IDL module idle status signal REQ2 request signal 7 bus controller 70 dynamic clock control circuit STP stop signal 9 external I / O circuit 90 External bus interface port 91, 92 I / O port 14 Clock pulse generator STBCR1, CTBCR2 ICLK, BCLK, PCLK Clock signal PCLK-1, BCLK-1, PCLK-2, BCLK
-2 clock signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junichi Shiba 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Kengo Matsuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated Semiconductor Division, Hitachi Ltd. (72) Koji Hashimoto Tokyo 5-22-1, Kamizuhoncho, Kodaira City Inside Hitachi Microcomputer System Co., Ltd.

Claims (16)

[Claims] In a data processing device formed on one semiconductor substrate including a central processing unit and a cache memory, hit data for indicating a cache miss state of the cache memory is referred to, and the hit information is referred to as a cache miss. When not shown, the internal circuit in the operation unnecessary state is transited to the low power consumption state, and when the hit information indicates a cache miss, the low power consumption state of the internal circuit in the low power consumption state is released. A data processing device comprising control means for performing dynamic low power consumption control. 2. The control means stops supply of a clock signal to an internal circuit to cause the internal circuit to transition to a low power consumption state, and supplies a clock signal to the internal circuit in a clock signal stopped state. 2. The data processing device according to claim 1, wherein the low power consumption state of the internal circuit in the low power consumption state is released by restarting the operation. 3. The circuit according to claim 2, wherein the internal circuit is a bus controller connected to a cache memory and controlling a bus cycle, and an input / output circuit connected to the bus controller and interfaced with the outside. Data processing device. 4. A peripheral circuit module further comprising control register means for setting, by the central processing unit, control information for instructing supply and stop of a clock signal for synchronous operation to each peripheral circuit module. 4. The data processing apparatus according to claim 3, wherein said central processing unit can statically control clock supply to peripheral circuit modules by setting control information in said control register means. 5. A central processing unit, a cache memory,
Bus access control means, external interface means,
A clock pulse generator on a semiconductor substrate, wherein the cache memory outputs hit information to the bus access control means, wherein the cache memory outputs hit information to the bus access control means; The access control unit refers to hit information for indicating a cache miss state of the cache memory, and when it does not indicate a cache miss, stops supplying a clock signal to an internal circuit in an operation unnecessary state, A control means for performing dynamic clock signal supply control for resuming supply of a clock signal to the internal circuit in a clock signal stopped state when the hit information indicates a cache miss. Data processing device. 6. A peripheral circuit module which operates synchronously with a clock signal output from the clock pulse generator, and control information for instructing supply and stop of a clock signal for synchronous operation to each peripheral circuit module includes: Control register means set by the central processing unit, wherein the central processing unit can statically control clock supply to peripheral circuit modules by setting control information for the control register means. The data processing device according to claim 5. 7. A central processing unit, a cache memory,
A cache memory in which a lock function for prohibiting replacement of all or a part of a cache entry held by the associative memory unit can be selected, and an internal circuit in which operation is unnecessary when the lock function is selected in the cache memory And control means for controlling the power consumption to a low power consumption state, the data processing apparatus being formed on one semiconductor substrate. 8. The control means further refers to hit information for indicating a cache miss state of the cache memory, and when it does not indicate a cache miss, sets an internal circuit in an operation unnecessary state to a low power consumption state. To
8. The data processing apparatus according to claim 7, wherein when the hit information indicates a cache miss, the internal circuit in the low power consumption state is released from the low power consumption state. 9. The internal circuit is a bus controller connected to a cache memory and controlling a bus cycle, and an input / output circuit connected to the bus controller and interfaced with the outside.
The data processing device according to claim 1. 10. The control unit according to claim 7, wherein the control unit stops supplying a clock signal to an internal circuit and controls the internal circuit to a low power consumption state. The data processing device according to the item. 11. A peripheral circuit module, further comprising control register means for setting, by the central processing unit, control information for instructing supply and stop of a clock signal for synchronous operation to each peripheral circuit module. ,
11. The data processing device according to claim 10, wherein the central processing unit can statically control clock supply to a peripheral circuit module by setting control information in the control register unit. 12. A data processing device comprising a central processing unit, a cache memory, a bus controller for controlling a bus cycle, and an input / output circuit connected to the bus controller and interfaced with the outside. Referring to an access request signal to the controller, when it does not indicate an access request, the internal circuit in an operation unnecessary state is shifted to a low power consumption state, and when the access request signal indicates an access request, low power consumption is performed. A data processing apparatus comprising a control unit for performing dynamic low power consumption control for canceling a low power consumption state of the internal circuit in a power state. 13. The control means stops supply of a clock signal to an internal circuit, causes the internal circuit to transition to a low power consumption state, and supplies a clock signal to the internal circuit in a clock signal stopped state. 13. The data processing device according to claim 12, wherein the low power consumption state of the internal circuit in the low power consumption state is canceled by restarting. 14. A data processing system comprising a microprocessor and a memory accessible by the microprocessor, the microprocessor comprising a central processing unit, a cache memory, a bus controller for controlling bus cycles, and Reference is made to an input / output circuit connected to the bus controller and interfaced with the memory, and hit information for indicating a cache miss in the cache memory, and a state where operation is unnecessary when the first state does not indicate a cache miss A low power consumption state of the internal circuit in the low power consumption state when the hit information indicates the cache miss in the second state. Characterized by comprising control means for controlling power consumption. Over data processing system. 15. A central processing unit, a cache memory capable of selecting a lock function capable of prohibiting replacement of a cache entry used for associative storage, and an operation unnecessary state when a lock function is selected in the cache memory. A certain internal circuit is set to a low power consumption state, and when hit information for indicating a cache miss state of the cache memory does not indicate a cache miss, an internal circuit in an operation unnecessary state is shifted to a low power consumption state, A data processing apparatus comprising, on a single semiconductor substrate, control means for canceling the low power consumption state of the internal circuit which is in the low power consumption state when the information indicates a cache miss. . 16. A central processing unit, a cache memory capable of selecting a lock function capable of inhibiting replacement of a cache entry used for associative memory, a plurality of peripheral circuit modules, and a synchronous operation for the peripheral circuit module. Low consumption of a clock pulse generator in which control information for instructing supply and stop of a clock signal is set by the central processing unit, and an internal circuit in an operation unnecessary state when a lock function is selected for the cache memory. A power state, and when the hit information for indicating the cache miss state of the cache memory does not indicate a cache miss, the internal circuit in an operation unnecessary state is shifted to a low power consumption state; Low power consumption of the internal circuit in a low power consumption state when indicating a cache miss Control means for canceling the power state
A data processing apparatus characterized in that the data processing apparatus includes a plurality of semiconductor substrates.