JP2005293609A - Initialization method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform software-like initializing processing of a processor at a higher speed. <P>SOLUTION: In a system for performing communication between a master processor and a slave processor, an initialization method is provided for performing software-like second initializing processing using an initialization program after performing first initializing processing responding to a reset signal. The master processor sets whether the initialization program is stored in a local memory (6) or in an external memory (9) based on the kind of the reset signal, and the slave processor reads the initialization program from the selected local memory or external memory. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an initialization method.

  When a power supply of a device is turned on, a microprocessor provided in a device performs a reset operation for initializing the inside of the processor according to a reset signal given from the outside. In this reset operation, various initialization applications are executed by reading and executing an initialization process program from an external memory after a hardware initialization process for initializing the storage contents of a storage element provided in the processor. Software initialization processing for setting the program to an executable state is performed.

  The hardware initialization process is performed in response to assertion of a reset signal. The software initialization process is performed by fetching the instruction of the initialization process program from the address specified by the reset vector, triggered by the negation of the reset signal. Normally, this initialization processing program is stored in a read-only memory (hereinafter referred to as ROM) connected to the outside of the processor via a bus.

  That is, in software initialization processing, the processor gives a read request address to the ROM via the bus, so that the instruction sequence of the initialization processing program is sequentially read from the ROM and supplied to the processor via the bus. The Upon receiving this, the processor sets an appropriate value according to the system in various setting registers provided in the processor according to the supplied instruction, thereby preparing an environment in which the application program can be executed.

  By the way, there is a system that constitutes a multiprocessor in which a plurality of processors that perform such a reset operation are connected to a shared bus, and one of them functions as a master processor and the other as a slave processor. In order to reset such an entire multiprocessor system, it is necessary to perform a reset operation in all the processors.

  For this purpose, first, a reset signal is asserted to all processors, and hardware initialization processing is performed in all processors. Then, after a reset signal is asserted for a time necessary and sufficient for initializing the storage contents of the storage elements in the processor, the reset signal is negated for each processor.

  In response to the negation of the reset signal, the respective processors attempt to start access to the ROM all at once according to the address indicated by the reset vector in order to perform software initialization processing. However, a plurality of processors cannot access the ROM connected on the shared bus at the same time. For this reason, each processor sequentially accesses the ROM via arbitration (bus arbitration) of the shared bus, and sequentially reads out an instruction sequence of a program necessary for software initialization processing.

  Also, in a system incorporating a processor that performs the reset operation as described above, when the processor is not operating even after the power is turned on, the clock supply to the processor is stopped to reduce power consumption. A system has also been proposed. For example, in a system composed of multiprocessors as described above, there is a state in which the master processor is operating and the slave processor is not operating. In this case, by stopping the clock supply in the slave processor, Low power consumption is achieved.

  When the processor clock supply is stopped and the processor is subsequently used, the clock is supplied again to start the processor. At this time, the restarted processor performs a hardware initialization process in response to the assertion of the reset signal, and then accesses the ROM via the bus in accordance with the negation of the reset signal to perform the necessary initialization process. The instruction sequence of the computer program is read and software initialization processing is executed.

  However, in the above-described conventional system, in the software initialization process performed after the hardware initialization process, a program necessary for the initialization process is a low-speed memory device via the bus. The ROM had to be accessed and acquired, and the reset operation took a lot of time.

  In particular, in a system in which the clock supply of the processor is temporarily stopped to reduce power consumption, if the processor is frequently stopped and started, access to the low-speed ROM is performed each time the processor is started. Since this is executed, there is a problem in that useless time for waiting for the system to start increases.

  Further, in a multiprocessor system in which a plurality of processors are connected on a shared bus, a ROM storing an initialization process program executed by each processor is connected to the shared bus. When the accesses conflict, bus arbitration is performed, and each processor sequentially accesses the low-speed ROM. Therefore, there is a problem that the time required for initialization of all the processors is greatly increased.

  Furthermore, in a multiprocessor system, each processor is usually assigned a different role, and the contents of software initialization processing are also different. For this reason, the program used for the initialization process is different for each processor. Therefore, there is a problem that a mechanism for determining which processor executes which program among the different programs stored in the ROM is required, resulting in a complicated system configuration.

The present invention has been made to solve such a problem, and an object of the present invention is to enable a software initialization process of a processor to be performed at a higher speed.
Another object of the present invention is to make it possible to further simplify a mechanism for performing software initialization processing of a processor.

  In the initialization method of the present invention, in a system in which communication is performed between a master processor and a slave processor, after performing a first initialization process in response to a reset signal, an initialization program is used to perform software-like processing. An initialization method for performing a second initialization process, wherein the master processor sets whether an initialization program is in a local memory or an external memory based on a type of the reset signal, and the slave processor Reads out the initialization program from the selected local memory or external memory.

  When restarting after the internal clock supply is stopped after the power is turned on, the initialization program for restart can be read from the high-speed local memory to start the processor, and the restart process is performed at high speed. be able to. As a result, the power consumption of the system can be suppressed and high-speed recovery from the clock stop state can be realized. Further, when a multiprocessor system is configured, a mechanism for determining which processor executes which program is not required, and the system configuration can be simplified.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of a processor according to a first embodiment of a data processing system according to the present invention.

  The processor 10 of this embodiment holds an instruction fetch control unit 1 that controls an operation of reading and fetching a program instruction from the memory, an instruction execution unit 2 that interprets and executes the fetched instruction, and holds a copy of the contents of the memory Thus, a cache memory that supports high-speed memory access and its control unit (hereinafter abbreviated as cache unit 3), a random access memory (RAM) 6 that is a local memory, and an external such as an address bus 7 and a data bus 8 A bus control unit 4 that controls the bus and a clock control unit 5 that generates and distributes internal clocks bck and cck based on an external clock CLOCK applied thereto are provided.

  A ROM 9 which is an external memory is connected to the external buses 7 and 8, and an initialization program necessary for performing a software initialization process of the processor 10 is stored in advance here. Here, the ROM 9 is assumed as the external memory, but is not limited thereto. The RAM 6 is normally used as a work memory for the processor 10, and an initialization program is transferred from the ROM 9 via the external buses 7 and 8 and stored as necessary.

  The cache memory in the cache unit 3 is a high-speed but small-capacity buffer memory that holds a copy of the contents of the external memory connected to the processor 10. When a copy of the contents of the external memory exists in the cache memory, data for the instruction execution unit 2 is supplied from the cache memory. As far as the present invention is concerned, the presence / absence of the cache unit 3 does not have an essential meaning and will not be described in detail. In the present embodiment, as the cache memory, for example, a store-through type is used.

  The instruction fetch control unit 1 generates an address of a memory in which an instruction of an initialization program to be executed by the processor 10 is stored, and issues it to the cache unit 3 together with the instruction fetch request iaval as a request instruction address ia. At this time, the instruction fetch control unit 1 selects either the start address of the RAM 6 as the local memory or the ROM 9 as the external memory based on the address selection signal MS given from the outside, and sets it as the request instruction address ia. That is, the instruction fetch control unit 1 includes the address selection unit of the present invention.

  The cache unit 3 that has received the instruction fetch request iaval from the instruction fetch control unit 1 searches the cache memory for a valid entry by using the request instruction address ia given along with it. If a cache hit occurs, the corresponding data is read from the cache memory and supplied to the instruction execution unit 2 as instruction data id. On the other hand, when a valid entry does not exist in the cache memory and a cache miss occurs, an instruction fetch request and a request address add are supplied to the bus control unit 4.

  The bus control unit 4 selectively requests data read from either the RAM 6 or the ROM 9 in accordance with the received request address add. That is, the bus control unit 4 includes an area designation register 4a for holding information for designating an address area of the RAM 6, in which information on the area start address ASR and area size AMR is held. . Then, depending on whether the request address add received from the cache unit 3 is included in the address area of the RAM 6 specified by the pair of the head address ASR and the area size AMR, either the RAM 6 or the ROM 9 is selected. Request to read data.

  FIG. 2 is a diagram showing a memory map of the entire system including various registers in the processor 10 in addition to the RAM 6 and the ROM 9. In the example of FIG. 2, the address numbers 0x0000 — 0000 to 0x01FF_FFFF are assigned to the RAM 6, and 0xFE00 — 0000 to 0xFF00 — 0000 are assigned to each component in the processor 10 (instruction fetch control unit 1, instruction execution unit 2, cache memory 3, bus control unit 4. And 0xFF00_0000 to 0xFFFF_FFFF are assigned to the ROM 9 and assigned to various registers provided in the clock controller 5). Note that the address numbers from 0x01FF_FFFF to 0xFE00_0000 are unused.

  According to the example of FIG. 2, the address number of 0x0000_0000 is held as information of the start address ASR of the area specifying register 4a, and the area size of 01FF_FFFF is held as information of the area size AMR. Therefore, if the request address add received from the cache unit 3 is included in the range of 0x0000_0000 to 0x01FF_FFFF, the bus control unit 4 places the request address add on the address line ram_add and requests the RAM 6 to read data. To do.

  The bus control unit 4 does not include the received request address add in the address area of 0x0000_0000 to 0x01FF_FFFF specified by the pair of the head address ASR and the area size AMR in the area specifying register 4a, and If it is not included in the address areas 0xFE00 — 0000 to 0xFF00 — 0000 representing the areas of various registers in the memory-mapped processor 10, the ROM 9 is requested to read data by placing the request address “add” on the address bus 7. .

  Data requested to the RAM 6 or the ROM 9 is read from each memory and sent to the bus control unit 4 via the data line ram_data or the data bus 8. The bus control unit 4 that has received this data supplies it to the cache unit 3 as read data rdd. The cache unit 3 that has received the read data rdd supplies the data to the instruction execution unit 2 as instruction data id, and registers the instruction data in the cache memory as necessary.

  The instruction execution unit 2 that has received the instruction data id as described above interprets and executes the instruction. In the course of this execution, when it becomes necessary to refer to data stored in the RAM 6, ROM 9 or various registers in the processor 10, the instruction execution unit 2 sends a data fetch request with the requested data address oa to the cache unit 3 To issue.

  Regarding the data fetch at this time, the subsequent operations are almost the same as in the case of the instruction fetch. However, when the request address add designates the address area (0xFE00_0000 to 0xFF00_0000) of the memory-mapped register, the bus control unit 4 determines the value of the register (the area designation register 4a or a reset register (RSTR) 4b described later) Value) is read and returned to the cache unit 3 as read data rdd. Data returned from the RAM 6, ROM 9 or register to the cache unit 3 via the bus control unit 4 is finally supplied to the instruction execution unit 2 as read data rd.

  In the course of instruction execution in the instruction execution unit 2, if it becomes necessary to update the contents of the memory such as the RAM 6 or the register, the data write request is sent to the cache unit with the request data address oa and the write data wd. Issue to 3. When a cache hit occurs, the cache unit 3 writes the write data wd to the cache memory, and issues a data write request with the request address add and the write data wrd to the bus control unit 4.

  The bus control unit 4 that has received the data write request, when the received request address add is included in the address area of the RAM 6 specified by the pair of the head address ASR and the area size AMR in the area specifying register 4a. Requests the RAM 6 to write data by placing the request address add on the address line ram_add and the write data wrd on the data line ram_data. If the received request address add designates an address area of a memory-mapped register such as the area designation register 4a or the reset register 4b, the bus control unit 4 stores the address indicated by the request address add. On the other hand, write data wrd is written.

  Further, the bus control unit 4 does not include the received request address add in the address area of the RAM 6 specified by the pair of the head address ASR and the area size AMR in the area specifying register 4a, and is memory-mapped. If the address is not included in the address area of the register, the request address add is placed on the address bus 7 and the write data wrd is placed on the data bus 8 to request the ROM 9 to write data.

  The processor 10 of the present embodiment is driven by a clock CLOCK given from the outside. The clock control unit 5 generates first and second internal clocks bck and cck based on the external clock CLOCK. The first internal clock bck is supplied to the bus control unit 4, and the second internal clock cck is supplied to the other instruction fetch control unit 1, instruction execution unit 2 and cache unit 3. .

  A clock stop signal stop instructing to stop the supply of the internal clocks bck and cck is supplied from the instruction execution unit 2 to the clock control unit 5 as necessary. That is, the processor 10 can stop the supply of the internal clocks bck and cck by executing an instruction for stopping the clock in the instruction execution unit 2. There are two clock stop modes: a first mode in which both the two internal clocks bck and cck are stopped, and a second mode in which only the second internal clock cck is stopped.

  In order to restart the clock supply once stopped, either the initial activation reset signal PRST (first reset signal of the present invention) or the restart reset signal HRST (second reset signal of the present invention) is asserted. Or a reset register 4b included in the bus control unit 4 is written from an external bus master (not shown), and the reset signal (start signal wup) corresponding to the restart reset signal HRST or the program reset signal SRST described below is supplied to the bus control unit. There is a method of generating and asserting within 4. When the latter method is employed, the first internal clock bck needs to be continuously supplied to the bus control unit 4, and in this case, the above-described second mode is employed.

  Although not shown in detail in FIG. 1, the initial start reset signal PRST and the restart reset signal HRST are the components in the processor 10 (the instruction fetch control unit 1, the instruction execution unit 2, the cache unit 3, It is provided to the bus control unit 4 and the clock control unit 5). In the present embodiment, in addition to these reset signals, a program reset signal SRST (third reset signal of the present invention) that performs a reset operation independently regardless of the supply stop and restart of the internal clocks bck and cck is also prepared. ing. The program reset signal SRST is used, for example, when debugging, and is supplied only to the instruction fetch control unit 1 and the instruction execution unit 2.

  FIG. 3 is a diagram showing a detailed configuration example of the instruction fetch control unit 1. In FIG. 3, the requested instruction address ia is held in the instruction address register 11 and supplied to the cache unit 3. In a state where the processor 10 sequentially executes instructions, the value “16” is added by the adder 12 to the current address held in the instruction address register 11 as the next request instruction address ia. Is selected by the selectors 13 and 14 and held in the instruction address register 11. This increment value “16” specifies the bus width of the instruction data bus of the processor 10.

  When the processor 10 executes a branch instruction, the signal b notifying that the instruction execution unit 2 has branched is asserted. In this case, the branch destination address bad sent from the instruction execution unit 2 as the next request instruction address ia is selected by the selector 13 and held in the instruction address register 11 via the selector 14.

  The processor 10 is initialized by the initial start reset signal PRST, the restart reset signal HRST, the program reset signal SRST, and the start signal wup from the reset register 4b (hereinafter, these four signals are generically referred to as a reset signal). In this state, any address (0x0000_0000 or 0xFF00_0000) selected by the selector 15 according to the address selection signal MS given from the outside is selected by the selector 14 according to the reset signal and It is held in the address register 11.

For example, when the initial activation reset signal PRST is input, that is, when the power of the apparatus is turned on, the value of the address selection signal MS is set to “1” and a fixed value indicating the head address of the address area of the ROM 9 0xFF00_0000 "is selected and held in the instruction address register 11. On the other hand, when the restart reset signal HRST is input, that is, when the clock supply is resumed from the supply stop state of the internal clocks bck and cck, the value of the address selection signal MS is set to “0”, and the address area of the RAM 6 A fixed value “0x0000 — 0000” representing the head address of the address is selected and held in the instruction address register 11.
The case where the program reset signal SRST and the start signal wup are input is the same as the case where the restart reset signal HRST is input.

  Thus, the request instruction address ia when the reset signal is negated and the instruction fetch of the initialization program is first performed is either the leading address “0xFF00_0000” of the ROM 9 or the leading address “0x0000_0000” of the RAM 6. As described above, the selectors 14 and 15 that perform the selection operation by the address selection signal MS constitute the address selection means of the present invention.

  Further, the instruction fetch control logic 16 determines whether or not the instruction fetch request iaval can be issued according to the instruction execution status of the processor 10, the status of the cache control unit, or the like, in accordance with the given reset signal. The request instruction address ia held in the instruction address register 11 is not updated until the instruction fetch request iaval is asserted to the cache unit 3 and accepted.

  FIG. 4 is a diagram showing a detailed configuration example of a portion including the area designation register 4a of the bus control unit 4, and shows the flow of addresses and data. As shown in FIG. 4, the bus control unit 4 includes a bus I / F 21, a memory control unit 22, and an external bus control unit 23. The bus I / F 21 includes a bus command control unit 24 having the area specifying register 4a, a read data path 25, and a write data path 26.

  The memory control unit 22 includes a memory-bus I / F (MBI) 27, a memory I / F (MI) 28, and a memory-external bus I / F (MEI) 29. The external bus control unit 23 includes an external bus-bus I / F (EBI) 30, an external bus-memory I / F (EMI) 31, and an external bus I / F 32.

  The operation of the bus control unit 4 at the time of instruction fetch will be described below. Upon receiving the instruction fetch request from the cache unit 3, the bus control unit 4 receives the request address add given together with the instruction fetch request and the head address ASR set in advance in the area designation register 4a in the bus command control unit 24. And the value of the area size AMR are compared to determine whether the request address add is within the address area of the RAM 6.

  As a result of the address comparison, when the instruction fetch request is a request for the RAM 6, the bus command control unit 24 issues an instruction fetch request to the memory control unit 22. The memory control unit 22 that has received this instruction fetch request via the memory-bus I / F 27 accesses the RAM 6 connected via the memory I / F 28 and reads out the instruction data corresponding to the request address add. The read instruction data is sent back to the cache unit 3 via the memory-bus I / F 27 and the read data path 25 and finally sent to the instruction execution unit 2.

  On the other hand, as a result of the address comparison, if the instruction fetch request is a request for the ROM 9 connected to the external buses 7 and 8, the bus command control unit 24 sends an instruction fetch request to the external bus control unit 23. Issue. The external bus control unit 23 that has received this instruction fetch request by the external bus-bus I / F 30 performs bus arbitration, issues a memory transaction on the external buses 7 and 8, and waits for a response.

  When the instruction data read from the ROM 9 on the external buses 7 and 8 is output to the external buses 7 and 8, the external bus control unit 23 takes in the instruction data via the external bus I / F 32. The instruction data thus fetched is sent back to the cache unit 3 via the external bus-bus I / F 30 and the read data path 25 and finally sent to the instruction execution unit 2.

  FIG. 5 is a diagram showing a detailed configuration example of a portion that performs address determination in the bus command control unit 24 shown in FIG. As shown in FIG. 5, the bus command control unit 24 includes the region designation register 4 a described above, two comparators 41 and 42, two buffers 43 and 45, and a NAND gate 44.

  One comparator 41 compares the address area of the memory-mapped register with the request address add provided from the cache unit 3. As a result of this comparison, if the request address add is included in the address area of the memory-mapped register (when the signal match1 is asserted), an instruction fetch request command is sent to the register via the buffer 43. Issue.

  The other comparator 42 compares the request address add supplied from the cache unit 3 with the address area of the RAM 6 specified by the pair of the start address ASR and the area size AMR in the area specifying register 4a. As a result of the comparison, when the request address add is included in the size specified by the region size AMR from the start address set in the start address ASR (when the signal match2 is asserted), the buffer 45 is used. An instruction fetch request command is issued to the RAM 6.

  Further, as a result of the comparison in the two comparators 41 and 42, when the request address add given from the cache unit 3 is not included in the address area of the memory mapped register or the address area of the RAM 6 (signal match1). , 2 are not asserted), an instruction fetch request command is issued to the external buses 7, 8 via the NAND gate 44.

  FIG. 6 is a diagram showing a detailed configuration example of a portion including the reset register 4b of the bus control unit 4, and shows a flow of data writing to the reset register 4b. As shown in FIG. 6, the reset register 4b is composed of 5-bit registers PD, HD, SD, HS, and SS.

  Of these, the PD, HD, and SD bits are registers for indicating the immediately preceding reset factor, the PD bit is the initial start reset when the power is turned on, the HD bit is the restart reset when the clock supply is resumed, and the SD bit is Indicates a program restart reset during debugging. These 3 bits correspond to the information holding means of the present invention that holds the identification information of the reset factor.

  Further, the remaining 2 bits of HS and SS are written in here by an external bus master (not shown), thereby controlling the reset signal (HRST ′, SRST ′) corresponding to the restart reset signal HRST or the program reset signal SRST. This is generated inside the unit 4 and constitutes the reset internal generation means of the present invention. That is, the outputs of the HS bit and the SS bit are supplied to the OR gates 51 and 52 together with the restart reset signal HRST and the program reset signal SRST, respectively, and one of the valid ones is supplied to the subsequent stage.

  Several logic gates 51 to 57 are appropriately arranged between the PD, HD and SD bits in the reset register 4b and the initial start reset signal PRST, restart reset signal HRST and program reset signal SRST. Thus, only one of the three bits of PD, HD, and SD is set to “1”.

  That is, when the initial activation reset signal PRST is asserted, the PD bit is set to “1”. When the external restart reset signal HRST is asserted, or when the internal restart reset signal HRST ′ is asserted by writing to the HS bit, the HD bit is set to “1”. Is done. When the external program reset signal SRST is asserted or when the SS bit is written and the internal program reset signal SRST ′ is asserted, the SD bit is set to “1”. .

Further, by appropriately arranging the above-mentioned several logic gates 51 to 57, between the three types of resets,
PRST>HRST> SRST
Is given priority. Until the reset factor is newly generated, the immediately previous reset factor is held in the PD, HD, and SD bits.

  FIG. 7 is a diagram illustrating a configuration example of the clock control unit 5. The clock control unit 5 generates two internal clocks bck and cck from the external clock CLOCK supplied from the outside, and supplies them to the inside of the processor 10. That is, in this embodiment, as shown in FIG. 1, the internal clocks to the bus control unit 4 and other parts are supplied by different systems of bck and cck.

  In the present embodiment, the clock supply to the processor 10 can be temporarily stopped by an instruction from the instruction execution unit 2. For example, in order to reduce power consumption, when the idle state of the processor 10 continues for a certain time, the instruction execution unit 2 asserts the clock stop signal stop to the clock control unit 5.

  At this time, only the first mode for stopping both the internal clocks bck and cck for the entire processor 10 including the bus control unit 4 and the second internal clock cck for the part other than the bus control unit 4 in the processor 10 are stopped. One of the second modes to be performed can be selected. Depending on the selected mode, the instruction execution unit 2 asserts the clock stop signal stopbc or stopc.

  A clock stop signal stopbc for stopping the entire processor 10 is supplied to the two OR gates 61 and 65. The clock stop signal stopbc that has passed through the OR gate 61 is held in the C register 62, then supplied to the negative logic terminal of the AND gate 64, and the logical product of the external clock CLOCK supplied to the positive logic terminal of the AND gate 64. Is taken and output as the internal clock cck.

  On the other hand, the clock stop signal stopbc that has passed through the OR gate 65 is held in the B register 66, supplied to the negative logic terminal of the AND gate 68, and the external clock CLOCK supplied to the positive logic terminal of the AND gate 68. A logical product is taken and output as the internal clock bck.

  With this configuration, when the clock stop signal stopbc is asserted, the signals “1” are input to the negative logic terminals of the AND gates 64 and 68, so the supply of the two internal clocks bck and cck is stopped. Will be.

  Further, the clock stop signal stopc for stopping other than the bus control unit 4 in the processor 10 is supplied only to the OR gate 61. The clock stop signal stopc that has passed through the OR gate 61 is held in the C register 62, then supplied to the negative logic terminal of the AND gate 64, and the logic of the external clock CLOCK supplied to the positive logic terminal of the AND gate 64. The product is taken and output as the internal clock cck.

  With such a configuration, when the clock stop signal stopc is asserted, the signal “1” is input to the negative logic terminal of the AND gate 64, so that the supply of the internal clock cck is stopped. On the other hand, since the clock stop signal stopc is not supplied to the OR gate 65, the signal “1” is not input to the negative logic terminal of the AND gate 68 by the assertion of the clock stop signal stopc, and the internal clock bck is supplied. Will continue.

  The OR gates 61 and 65 are also supplied with outputs of AND gates 63 and 67, respectively. The AND gate 63 takes the logical product of the output of the C register 62 supplied to the positive logic terminal and the activation signal wup supplied to the negative logic terminal and supplies the logical product to the OR gate 61. The AND gate 67 takes the logical product of the output of the B register 66 supplied to the positive logic terminal and the start signal wup supplied to the negative logic terminal and supplies the logical product to the OR gate 65.

  The contents stored in the C register 62 and the B register 66 are stored in the internal restart generated by writing to the reset register 4b (HS bit in FIG. 6) from the initial startup reset signal PRST, the restart reset signal HRST, or an external bus master. It can be rewritten by asserting the start reset signal HRST ′.

  For example, in a state where the internal clock bck is supplied only to the bus control unit 4, the supply of the internal clock cck to parts other than the bus control unit 4 can be resumed by asserting the internal restart reset signal HRST ′. It is configured. In the state where the supply of the internal clocks bck and cck to the entire processor 10 is stopped, the supply of the internal clocks bck and cck is resumed by asserting the initial start reset signal PRST or the restart reset signal HRST. It is configured to be able to.

Next, a startup sequence when the processor 10 according to the present embodiment configured as described above is used alone will be described below.
First, a startup process sequence by the initial startup reset signal PRST when the apparatus is turned on will be described.

  When the apparatus is powered on, first, the initial activation reset signal PRST is asserted to perform hardware initialization processing. At this time, the values of various registers in the processor 10 including the area specifying register 4a and the reset register 4b in the bus control unit 4 are all initialized to “0”, for example.

  Then, the initial activation reset signal PRST is asserted for a time sufficient for performing the hardware initialization process, and when the power supply is stabilized, the initial activation reset signal PRST is negated. When the initial activation reset signal PRST is negated, the initialization program is read in accordance with the address indicated by the reset vector in order to perform software initialization processing.

  Immediately after the power is turned on, since the valid initialization program data is not held in the RAM 6, the value of the address selection signal MS is set to “1”. Thus, the instruction fetch control unit 1 issues an instruction fetch request from the initial address “0xFF00_0000”.

  In response to this, the bus control unit 4 determines whether or not the given request address add of “0xFF00_0000” is included in the address area of the RAM 6 specified by the head address ASR and the area size AMR in the area specifying register 4a. And either RAM 6 or ROM 9 is accessed according to the result. At this time, the address area of the RAM 6 is initialized to φ, and the given request address add also specifies the address area of the ROM 9, so that the bus control unit 4 is connected to the external buses 7 and 8. The ROM 9 is accessed.

  The initialization program stored in the ROM 9 is defined so as to refer to the value of the reset register 4b in the first sequence. Immediately after the power is turned on, it is confirmed that the PD bit in the reset register 4b is set to "1", and a routine including processing necessary when the initial activation reset signal PRST is negated is executed.

  After the processor 10 is started in this manner, address information (head address ASR and area size AMR) necessary for accessing the RAM 6 is set in the area designation register 4a. In the example of FIG. 2, the value “0x0000_0000” is set in the head address ASR, the value “0x01FF_FFFF” is set in the area size AMR, and 32 Mbytes are mounted as the address area of the RAM 6. After the necessary value is set in the area specifying register 4a, the value of the address selection signal MS is switched to "0" and restarted from the ROM 9 or other devices connected on the external buses 7 and 8. The program is loaded into the RAM 6 in advance.

Next, a startup process sequence by the restart reset signal HRST when the supply of the internal clock is resumed will be described.
Here, as an example, after the processor 10 is started, the supply of the internal clocks bck and cck to the entire processor 10 is stopped when the required processing has not been performed for a certain period of time. A restart sequence in the case of restarting by an external restart reset signal HRST will be described.

  When the restart reset signal HRST is asserted from the outside, the registers (C register 62 and B register 66 in FIG. 7) that stop supplying the internal clocks bck and cck in the clock control unit 5 are reset, and the internal clocks are reset. Supply of bck and cck is resumed. At the same time, hardware initialization processing is performed except for information necessary for memory access (such as the start address ASR and area size AMR in the area designation register 4a).

  When an SDRAM is used as the local memory connected to the processor 10, the processor 10 has information necessary for memory access in addition to the area designation register 4a for storing information of the start address ASR and area size AMR. , A control register for setting the minimum number of cycles between DRAM operations which differ for each DRAM type, an access mode control register for setting a DRAM access mode, and a mode set for setting information to be written to the DRAM when the DRAM mode is set Configuration register for setting information such as register, DRAM type, bus width, direct connection / DIMM usage, etc. Address number for setting DRAM RAS address bit number, CAS address bit number, bank address bit number Comprising register, status register indicating the state of the DRAM controller, the refresh control register for setting an auto-refresh or self-refresh of the DRAM, and the refresh timer register sets the refresh interval of the auto-refresh. All of these registers are initialized by the initial startup reset signal PRST, but are not initialized by the restart reset signal HRST or the program reset signal SRST.

  When the restart reset signal HRST is negated after the hardware initialization process, instruction fetch from the address “0x0000_0000” selected by the address selection signal MS (= 0) is started. At this time, since the values of the start address ASR and the area size AMR in the area specifying register 4a are not initialized by the assertion of the restart reset signal HRST, the instruction fetch request at this time is issued to the RAM 6. This eliminates the need for access to the low-speed ROM 9 and allows the processor 10 to be restarted at high speed.

  Here, it is also possible to instruct the ROM 9 to issue an instruction fetch request by setting “1” as the value of the address selection signal MS. When instruction fetch from the ROM 9 is executed when the processor 10 is restarted, the initialization program stored in the ROM 9 refers to the value of the reset register 4b in the first sequence, and the HD in the reset register 4b By confirming that the bit is set, it is possible to omit the process of resetting the information already set in the area specifying register 4a when the power is turned on, and to speed up the restart process of the processor 10 accordingly. be able to.

  It should be noted that after the supply of the internal clock cck is stopped, the processor 10 is restarted by an external restart reset signal HRST, or when the supply of the internal clock bck, cck or the internal clock cck is stopped, an internally generated restart reset signal HRST The operation of the restart sequence when the processor 10 is restarted by 'is the same as described above.

Next, the activation process sequence by the program reset signal SRST will be described.
When the program reset signal SRST is asserted from the outside, the program currently being executed in the instruction execution unit 2 is forcibly interrupted, and hardware initialization processing is performed on the instruction fetch control unit 1.

  Thereafter, when the program reset signal SRST is negated, instruction fetch from the address “0x0000 — 0000” selected by the address selection signal MS (= 0) is started. At this time, since the values of the start address ASR and the area size AMR in the area specifying register 4a are not initialized by the assertion of the program reset signal SRST, the instruction fetch request at this time is issued to the RAM 6. This eliminates the need for access to the low-speed ROM 9 and allows the processor 10 to be restarted at high speed.

  Here, it is also possible to instruct the ROM 9 to issue an instruction fetch request by setting “1” as the value of the address selection signal MS. When instruction fetch from the ROM 9 is executed at the time of program reset, the initialization program stored in the ROM 9 refers to the value of the reset register 4b in the first sequence, and the SD bit in the reset register 4b is set. As a result, it is possible to perform the necessary resetting process only for the register of the instruction fetch control unit 1 and omit other unnecessary processes, and restart the processor 10 correspondingly. The speed can be increased.

  As described above in detail, according to the processor 10 of the present embodiment, when performing a software initialization process, each reset signal and address of the initial activation reset signal PRST, the restart reset signal HRST, and the program reset signal SRST are addressed. In response to an instruction using the selection signal MS, it is possible to select activation from the ROM 9 connected to the external buses 7 and 8 or activation from the RAM 6 connected to the processor 10 as a local memory.

  Thereby, at the time of restart after the supply of the internal clocks bck and cck is stopped after the power is turned on, the initialization program for restart can be read from the high-speed RAM 6 and the processor 10 can be started. The startup process can be performed at high speed. Even when the ROM 9 is accessed at the time of restarting, the value of the reset register 4b is read to branch within the initialization program stored in the ROM 9, and only the starting process according to the reset contents is selectively performed. Can be executed. Therefore, even in a system in which the clock supply is frequently stopped and started by the processor 10 to reduce power consumption, the wasted time of waiting for the start of the system can be significantly shortened.

  Further, even when a multiprocessor system is configured by connecting a plurality of processors 10 as described above to a shared bus, for example, when restarting after the supply of internal clocks bck and cck is temporarily stopped by a slave processor The slave processor can read the initialization program for restart from the high-speed RAM 6 and can perform the restart process at high speed. At this time, since an instruction fetch request is not issued from the slave processor to the external buses 7 and 8, access to the ROM 9 from a plurality of processors does not compete, and bus arbitration processing is unnecessary. Can do.

  Further, even when the multiprocessor system is configured as described above, the start address of the memory storing the initialization program to be executed by each processor is selected by the address selection signal MS. Therefore, a mechanism for determining which processor executes which program in the ROM 9 becomes unnecessary, and the system configuration can be simplified.

Next, a second embodiment of the data processing system according to the present invention will be described.
FIG. 8 is a block diagram illustrating a configuration example of a multiprocessor system in which the processor according to the second embodiment is mounted as a slave processor.

  In FIG. 8, 71 is a master processor, 72 is a slave processor, and RAMs 73 and 74 which are local memories are connected to each. In addition to the master processor 71 and slave processor 72, the external buses 7 and 8 that are shared buses include a ROM 9, a shared memory 75, a DMAC (Direct Memory Access Controller) 76 that performs direct data transfer between the memory and the memory, An ASIC (Application Specific Intergrated Ciucuit) 77 that generates a signal for controlling the slave processor 72 is connected.

  The master processor 71 is always operating after the power is turned on, and a normal processor can be used. On the other hand, the slave processor 72 is configured to be able to stop and start the supply of the internal clock to reduce power consumption after the power is turned on, and a processor unique to this embodiment is used.

FIG. 9 is a block diagram illustrating a configuration example of the slave processor 72 according to the present embodiment.
The slave processor 72 of this embodiment has substantially the same configuration as the processor 10 shown in FIG. 1, but the configurations of the instruction fetch control unit 81 and the bus control unit 84 are different from those in FIG. In addition to the program reset signal SRST and the address selection signal MS, the instruction fetch control unit 81 is input with an activation suppression signal WAIT.

  The instruction fetch control unit 81 is configured as shown in FIG. As shown in FIG. 10, in the instruction fetch control unit 81 of the present embodiment, compared to the instruction fetch control unit 1 shown in FIG. 3, the inverter 85 that inverts the logic of the activation suppression signal WAIT, and the output of the inverter 85 An AND gate 86 that adds a logical product with the output of the instruction fetch control logic 16 is added.

  With this configuration, even if the instruction fetch control logic 16 determines the instruction execution status of the processor 72, the status of the cache control unit, etc. The instruction fetch request iaval is not issued to the cache unit 3 unless the activation suppression signal WAIT is negated. As described above, the inverter 85 and the AND gate 86 constitute the start inhibiting means of the present invention.

  The bus control unit 84 is configured in substantially the same manner as shown in FIG. However, in the present embodiment, when the transaction generated on the external buses 7 and 8 according to the specified protocol is a request from another device to the own processor, the external bus control unit 23 takes in the command and performs the corresponding processing. It has a mechanism to start.

  Specifically, the external bus control unit 23 always monitors transactions that have occurred on the external buses 7 and 8, and when a valid transaction occurs, fetches the address information for the resources in its own processor. Compare with the address information assigned in advance. As a result of this comparison, if the request is recognized as a request for the resource in the processor, the command of the transaction is fetched and access to the internal resource specified by the address information is started.

  FIG. 11 is a diagram illustrating a configuration example of the external bus control unit 23. As shown in FIG. 11, the external bus control unit 23 of the present embodiment caches response data from the four-stage cache command buffer 91 and the external buses 7 and 8 that hold commands and write data from the cache unit 3. A response data buffer 92 for sending out to the unit 3, a four-stage bus command buffer 93 for holding commands and write data from the external buses 7 and 8, and a read data buffer 94 for receiving read data from the RAM 74 as a local memory. I have.

  The external bus control unit 23 further selects a selector 95 for selecting any of the data stored in the four-stage cache command buffer 91, and a selector for selecting any of the data stored in the four-stage bus command buffer 93. 96, a command arbitration unit 97 for arbitrating the address bus 7, a data arbitration unit 98 for arbitrating the data bus 8, and a memory-mapped register 99.

  The register 99 corresponds to the area designation register 4a and the reset register 4b shown in FIG. 9, and includes information on the start address ASR and area size AMR of the RAM 74, and reset type identification information PD, HD, SD and internal reset write information HS and SS are held. The register 99 is configured so that both commands from the cache unit 3 and commands from the external buses 7 and 8 can be accessed.

  As described above, in the first embodiment described above, the area designation register 4a for storing the start address ASR and the area size AMR is provided in the bus I / F 21 (see FIG. 4), but in the second embodiment, The register 99 for storing these pieces of information is provided in the external bus control unit 23. In this case, the bus I / F 21 receives the value set in the register 99 from the external bus control unit 23.

Next, the startup sequence of the multiprocessor system using the processor 72 according to the present embodiment as a slave processor as described above will be described below.
First, a startup process sequence by the initial startup reset signal PRST when the apparatus is turned on will be described.

  When the apparatus is turned on, an initial activation reset signal PRST is asserted to the master processor 71, and an initial activation reset signal PRST and an activation suppression signal WAIT are asserted to the slave processor 72. When the initial activation reset signal PRST is asserted, both the master processor 71 and the slave processor 72 perform hardware initialization processing. At this time, the values of the registers in the processors 71 and 72 including the information of the head address ASR and the area size AMR are all initialized to “0”, for example.

  When the hardware initialization process is performed and the power supply is stabilized, the initial activation reset signal PRST is negated. In the master processor 71, when the initial activation reset signal PRST is negated, in order to perform subsequent software initialization processing, the master processor 71 initializes from the ROM 9 connected to the external buses 7 and 8 in accordance with the address indicated by the reset vector. The program is read out. At this time, the activation suppression signal WAIT remains asserted. Therefore, in the slave processor 72, the instruction fetch request iaval is not issued, and the initialization program is not read.

  When the initialization process in the master processor 71 is completed, the master processor 71 sets the internal resources of the slave processor 72 (information such as the start address ASR and the region size AMR) to appropriate values via the external buses 7 and 8. That is, the address area of the RAM 74 connected to the slave processor 72 is appropriately set by writing from the master processor 71 to the register 99 via the data arbitration unit 98 of FIG. Then, the master processor 71 activates the DMAC 76 and transfers an initialization program required by the slave processor 72 from, for example, the ROM 9 to the RAM 74.

  At this time, in the external bus control unit 23 of FIG. 11 provided in the slave processor 72, the address given via the address bus 7 from the DMAC 76 for the data direct transfer between the memory and the memory is set in the register 99. It is determined whether the address is in the address area of the RAM 74 specified by the pair of the start address ASR and the area size AMR.

  In this case, since the address area of the RAM 74 is set in advance in each information of the start address ASR and the area size AMR in the register 99, the external bus control unit 23 is sent from the ROM 9 via the data bus 8. The initialization program data thus received is sent to the memory control unit 22, and the initialization program is stored in the corresponding address area of the RAM 74.

  In this embodiment, since the information of the head address ASR and the area size AMR is held in the external bus control unit 23 instead of the bus I / F 21, the memory control unit 22 and the external bus are not used without using the bus I / F 21. The initialization program can be transferred only by the control unit 23. Further, since the DMAC 76 performs the transfer process independently of the master processor 71, the necessary software transfer process can be performed in the RAM 74 of the slave processor 72 without bothering the processing unit of the master processor 71.

  The DMAC 76 notifies the master processor 71 of the completion of the transfer process using an interrupt signal. The master processor 71 that has detected the transfer completion interrupt signal from the DMAC 76 accesses the ASIC 77 when it becomes necessary thereafter, and negates the activation suppression signal WAIT. When the activation suppression signal WAIT is negated, in the slave processor 72, the instruction fetch control unit 81 fetches an instruction from the initial address “0x0000_0000” selected by the address selection signal MS in which the value of “0” is set. The request iaval is issued to the bus control unit 84 via the cache unit 3.

  At this time, in the bus command control unit 24 in the bus control unit 84, the request address add given together with the instruction fetch request iaval, the value of the start address ASR and the region size AMR received from the register 99 in the external bus control unit 23 To determine whether the request address add is within the address area of the RAM 74.

  Here, since the address area of the RAM 74 is set to the start address ASR and the area size AMR, the bus command control unit 24 determines that the instruction fetch request iaval is a request for the RAM 74 and Issue an instruction fetch request. Upon receiving this instruction fetch request, the memory control unit 22 accesses the RAM 74 connected via the memory I / F 28 to read out the instruction data corresponding to the request address add, and supplies it to the instruction execution unit 2. Execute.

  Thereafter, if the required processing has not been performed in the slave processor 72 for a certain period of time, the instruction execution unit 2 of the slave processor 72 supplies the clock control unit 5 with the clock stop signal stopc. Thus, the supply of the internal clock cck supplied to other than the bus control unit 84 is stopped.

  The master processor 71 resumes the supply of the internal clock cck by writing to the HS bit of the register 99 included in the slave processor 72 when the necessity arises thereafter, and also performs hardware initialization processing and software. Perform basic initialization processing. At this time, the startup sequence of the initialization program necessary for performing the software initialization process is the same as that described in the first embodiment, and high-speed restart from the RAM 74 is executed.

  As described above, in the second embodiment, in the activation processing sequence based on the initial activation reset signal PRST when the power is turned on, the slave processor 72 is stopped while issuing the instruction fetch request iaval by asserting the activation suppression signal WAIT. The initialization program is transferred to the RAM 74, and then the activation suppression signal WAIT is negated to issue an instruction fetch request iaval to the RAM 74.

  Therefore, the slave processor 72 does not need to access the ROM 9 via the shared bus even in the startup processing sequence when the power is turned on. As a result, the initialization program can be read from the high-speed RAM 74 and the slave processor 72 can be activated. In addition, a plurality of processors connected on the shared bus do not start access to the ROM 9 all at once, so that arbitration of the shared bus can be made unnecessary, and the startup process can be performed at high speed.

  The initialization program to be executed in the slave processor 72 is stored in the RAM 74. When the initialization process of the slave processor 72 is performed, the initialization program can be read from the head address of the RAM 74 selected by the address selection signal MS. Therefore, a mechanism for determining which processor executes which program is not required, and the system configuration can be simplified.

  Note that each of the embodiments described above is merely an example of a specific example for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. It is. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.

  For example, in each of the above embodiments, the start address of the initialization program is selected based on the address selection signal MS given from the outside, but the start address may be selected internally. FIG. 12 is a diagram illustrating a configuration example of the instruction fetch control unit in that case. In this example, the restart address is selected according to the value set in the register in the LSI. In FIG. 12, the same blocks as those shown in FIG. 10 are denoted by the same reference numerals.

  In the instruction fetch control unit 101 shown in FIG. 12, several logic gates 102 to 105 and a register 106 are added to the instruction fetch control unit 81 shown in FIG. The AND gate 102 calculates the logical product of the address selection signal MS and the initial activation reset signal PRST and outputs the result to the OR gate 105. The AND gate 103 calculates the logical product of the signal btdir, the signal set_btdir, and the logical inversion signal of the initial activation reset signal PRST, and outputs the result to the OR gate 105. The AND gate 104 takes a logical product of the logical inversion signal of the signal set_btdir, the logical inversion signal of the initial activation reset signal PRST, and the output signal of the register 106 and outputs the result to the OR gate 105.

  The OR gate 105 calculates the logical sum of the output results of the AND gates 102 to 104 and outputs the result to the register 106. Thus, the register 106 takes in the value of the address selection signal MS from the external terminal when the initial activation reset signal PRST is asserted. When the initial activation reset signal PRST is negated and the signal set_btdir is asserted, the value of the signal btdir is fetched. In other states, the stored value is held. Here, it is assumed that the signals btdir and set_btdir are asserted when the instruction execution unit 2 executes a write instruction to the register 106.

  The selector 15 selects either “0x0000_0000” or “0xFF00_0000” according to the value held in the register 106. For example, when the value held in the register 106 is “1”, the address “0xFF00_0000” is selected, and when the value held in the register 106 is “0”, the address “0x0000_0000” is selected.

  With the configuration described above, the initial activation reset signal PRST is asserted when the power is turned on, and the value of the address selection signal MS is taken from the external terminal to select the start address of the initialization program. Further, the instruction execution unit 2 executes a write instruction to the register 106 before the clock supply is stopped, so that the value of the register 106 is set to “0”, so that the restart reset signal after the clock supply is stopped. At the time of restart by HRST, “0” in the register 106 can be referred to and “0x0000 — 0000” (RAM start address) can be selected as the start address of the initialization program.

  Note that, here, a mixed type of the external terminal of the address selection signal MS and the register setting is shown, but it is also possible to adopt a configuration with only register setting. Also, by moving the register 106 to another unit and making it a memory map, it is possible to write to the register 106 from the master processor during the operation of the slave processor, and to select the start address of the initialization program as the master A configuration that can be controlled from the processor is also possible.

  As described above, the address selection means for selecting the start address of the initialization program stored in the local memory or the external memory connected via the bus based on the address selection signal is provided. When restarting after the clock supply is stopped, the initialization program for restarting can be read from the high-speed local memory to start the processor, and the restarting process can be performed at high speed. As a result, the power consumption of the system can be suppressed and high-speed recovery from the clock stop state can be realized.

In addition, an access suppression means for suppressing an access request to the memory storing the initialization program based on the activation suppression signal is provided, and is connected via an external bus while the access request to the memory is being suppressed. The initialization program stored in the external memory is transferred to the local memory, and after the access request suppression is canceled, the start address of the initialization program stored in the local memory is selected. Even in the activation process sequence at the time, the initialization program can be read from the high-speed local memory and activated without accessing the external memory. Also, a plurality of processors connected on the external bus do not start accessing the external memory all at once, and the arbitration of the shared bus can be made unnecessary, so that the startup process can be performed at high speed.
Further, when a multiprocessor system is configured, a mechanism for determining which processor executes which program is not required, and the system configuration can be simplified.

The various aspects of the present invention are summarized as follows.
(1) A data processing system for performing a software initialization process by reading a necessary initialization program from a memory after performing a hardware initialization process in response to a reset signal,
A data processing system comprising address selection means for selecting a start address of the initialization program stored in a local memory or an external memory connected via a bus based on an address selection signal.

(2) The address selection means selects the start address of the initialization program stored in the external memory based on the address selection signal when the first reset signal is given from the outside at power-on. The data processing system according to (1) above, wherein

(3) When the second reset signal is given from the outside at the time of restart after the clock supply is stopped, the address selection means stores the initialization program stored in the local memory based on the address selection signal. The data processing system according to (1) above, wherein a start address is selected.

(4) When the second reset signal is given from the outside, the hardware initialization process initializes information other than information necessary for memory access including the address area of the local memory. The data processing system according to (3) above.

(5) When the third reset signal is given from the outside for compulsory initialization, the address selection means is configured to store the initialization program stored in the local memory based on the address selection signal. The data processing system according to (1), wherein a start address is selected.

(6) When the third reset signal is given from the outside, the hardware initialization process initializes only the minimum information including the fetch control unit that controls the instruction fetch of the program. The data processing system according to (5), characterized in that it is characterized in that

(7) The initialization program in the local memory transfers and stores the initialization program stored in the external memory when a first reset signal is given from the outside at power-on. The data processing system according to (1) above.

(8) The data processing system according to (3), further comprising reset internal generation means for generating a reset signal equivalent to the second reset signal inside the apparatus.

(9) The data processing system according to (5), further comprising a reset internal generation unit that generates a reset signal equivalent to the third reset signal inside the apparatus.

(10) An information holding unit that holds information for identifying whether the reset operation performed on the data processing system is the first reset, the second reset, or the third reset,
The data processing system according to (1), wherein the identification information in the information holding unit is read based on an instruction of the initialization program, and processing according to the result is performed.

(11) A data processing system for performing a software initialization process by reading a necessary initialization program from a memory after performing a hardware initialization process in response to a reset signal,
A data processing system comprising: an access deterring unit that deters an access request to the memory storing the initialization program based on a start deterrence signal.

(12) Address selection means for selecting a start address of the initialization program stored in the local memory or an external memory connected via a bus based on an address selection signal;
Data transfer means for transferring the initialization program stored in the external memory to the local memory while the access suppression means is suppressing access requests to the memory,
(11) In the above (11), the address selection means selects the start address of the initialization program stored in the local memory based on the address selection signal after canceling the inhibition of the access request. Data processing system.

(13) A register that holds information representing the address area of the local memory and a register that holds information for generating a reset signal equivalent to a reset signal supplied from the outside inside the apparatus, and is connected to the external bus The data processing system as described in (12) above, wherein these registers are accessible from another bus master device.

(14) A plurality of data processing devices are connected on the shared bus. In each data processing device, a hardware initialization process is performed according to a reset signal, and then a necessary initialization program is read from the memory. A data processing system that performs software initialization processing in at least one data processing device included in the data processing system,
An address selection means for selecting a start address of the initialization program stored in a local memory or an external memory connected via a bus based on an address selection signal;
An access deterring means for deterring an access request to the memory storing the initialization program based on an activation deterrent signal;
Data transfer means for transferring the initialization program stored in the external memory to the local memory while the access suppression means is suppressing access requests to the memory,
A data processing system wherein the address selection means selects a start address of the initialization program stored in the local memory based on the address selection signal after canceling the inhibition of the access request.

(15) The data processing system according to (14), wherein the data transfer by the data transfer means is performed using a DMAC that performs direct memory-to-memory transfer.

It is a block diagram which shows the structural example of the processor which concerns on 1st Embodiment of the data processing system by this invention. It is a figure which shows the memory map of the whole system containing RAM, ROM, and a register | resistor. It is a figure which shows the detailed structural example of an instruction fetch control part. It is a figure which shows the detailed structural example of the part containing the area | region designation | designated register of a bus control part, and is a figure which shows the flow of an address and data. It is a figure which shows the detailed structural example of the part which performs address determination within a bus command control part. It is a figure which shows the detailed structural example of the part containing the reset register of a bus control part, and is a figure which shows the flow of the data write with respect to the said reset register. It is a figure which shows the structural example of a clock control part. It is a block diagram which shows the structural example of the multiprocessor system which mounts the processor by 2nd Embodiment as a slave processor. It is a block diagram which shows the structural example of the processor by 2nd Embodiment. It is a figure which shows the structural example of the instruction fetch control part by 2nd Embodiment. It is a figure which shows the structural example of the external bus control part by 2nd Embodiment. It is a figure which shows the other structural example of an instruction fetch control part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Instruction fetch control part 2 Instruction execution part 3 Cache unit 4 Bus control part 4a Area designation register 4b Reset register 5 Clock control part 6 RAM (local memory)
7 Address bus 8 Data bus 9 ROM (external memory)
10 processor 14, 15 selector (address selection means)
23 External bus control unit 24 Bus command control unit 71 Master processor 72 Slave processor 73, 74 RAM (local memory)
76 DMAC
77 ASIC
81 Instruction fetch control unit 84 Bus control unit 85 Inverter 86 AND gate 99 Register 101 Instruction fetch control unit 106 Register PRST Initial activation reset signal (first reset signal)
HRST Restart reset signal (second reset signal)
SRST Program reset signal (third reset signal)
MS address selection signal ASR start address information AMR region size information PD, HD, SD reset type identification bit HS, SS internal reset write bit bck, cck internal clock stopc, stopbc clock stop signal WAIT start inhibition signal

Claims (3)

In a system in which communication is performed between a master processor and a slave processor, a second initialization process in software is performed using an initialization program after performing a first initialization process in response to a reset signal. An initialization method,
The master processor sets whether the initialization program is in a local memory or an external memory based on the type of the reset signal,
The initialization method, wherein the slave processor reads an initialization program from the selected local memory or external memory.   The initialization method according to claim 1, further comprising a reset register that stores information on the reset signal. The initialization method according to claim 1, wherein the reset signal is any one of an initial startup reset signal, a restart reset signal, and a program reset signal.

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