JP2004038601A - Cache memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the efficient use of a cache memory by suppressing the capacity consumption of the cache memory without increasing the hardware quantity even in the presence of a repeated command generated by loop unrolling. <P>SOLUTION: When the same command data are present in a cache data holding part 22 in the execution of a repeated command string generated by loop unrolling, a pointer corresponding to the command data is stored in a reuse information retention part 24 to prevent the consumption of the entry of the cache data holding part 22. Therefore, even if the repeated command generated by loop unrolling or the like is present, the capacity consumption of the cache memory can be suppressed without increasing the hardware quantity to efficiently use the cache memory. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cache memory device for improving memory access performance in a computer system, and more particularly to a cache memory device that effectively uses a capacity when processing a repetition instruction by loop unrolling or the like.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the performance of processors has been remarkably improved due to improvements in semiconductor technology.
However, since the performance improvement of the memory for storing the instructions executed by the central processing unit is relatively gradual in comparison with the performance improvement of the central processing unit, the instruction waiting of the central processing unit occurs, and the performance of the processor depends on the memory. There is a problem of being limited.
[0003]
To cope with this, a high-performance processor has a cache system between the main storage device and the central processing unit, and the cache memory device retains instructions accessed by the central processing unit, so that the second and subsequent accesses can be performed at high speed. And the substantial access speed of the main storage device is increased.
[0004]
Hereinafter, a conventional cache memory device will be described with reference to FIGS. 21, 22, 23, 24, and 25.
FIG. 21 is a block diagram showing a configuration of a conventional cache memory device, and FIG. 22 is a flowchart showing an operation flow of the conventional cache memory device. FIG. 23 is a diagram showing a program in C language before expansion, FIG. 24 is a diagram showing a program after expansion, and FIG. 25 is a diagram exemplifying a state in which a program expanded in the prior art is stored in a cache data holding unit. is there.
[0005]
FIG. 21 also shows a central processing unit 1 that is a component of the processor and executes instructions, and a main storage device 3 that stores instructions to be executed by the central processing unit 1.
[0006]
The central processing unit 1 is configured to sequentially execute the instructions read from the main storage device 3 via the cache memory device 7.
The cache memory device 7 includes a cache control unit 71 that controls the entire cache memory device, and a cache data holding unit 72 that stores a maximum of four entries of instruction data in the main storage device 3 in 16-byte units under the control of the cache control unit 71. It is composed of
[0007]
In FIG. 22, this control flow is started when the central processing unit 1 outputs a fetch request signal S11.
Next, the cache data holding unit 72 is controlled to determine whether or not the instruction data corresponding to the fetch address A11 exists in the cache data holding unit 72 (S415).
[0008]
Next, when the instruction data exists, the cache data holding unit 72 is controlled, and the instruction data corresponding to the fetch address A11 held by the cache data holding unit 72 is output to the central processing unit 1 (S416).
[0009]
If the instruction data does not exist, the access request signal S71 and the access address A71 are controlled, and the instruction data is read from the main storage device 3 in units of 16 bytes (S417).
[0010]
Next, the cache data holding unit 72 is controlled, the fetch address A11 and the read data D31 are registered in the cache data holding unit 72, and the process proceeds to S416 (S418).
[0011]
As described above, the cache data holding unit 72 stores the read instruction data in response to the fetch request of the central processing unit, so that the cache data holding unit 72 stores the next fetch request for the same address. Since the data can be directly supplied to the central processing unit 72 and the access to the main storage device is not required, the apparent access speed of the main storage device to the central processing unit can be improved.
[0012]
However, in the cache memory device having the conventional configuration, there is a problem that the efficiency is reduced at the time of executing a repeat instruction generated by loop unrolling or the like. Hereinafter, this state will be described.
[0013]
Loop unrolling is a method of arranging an instruction sequence executed in a loop of a program a plurality of times, thereby reducing the number of executions of an instruction for determining a loop end condition or a branch instruction for loop repetition.
[0014]
For example, when loop expansion is performed on the C language program in FIG. 23, instruction data including a repetition instruction as shown in FIG. 24 is generated.
When this instruction data is executed by a processor having a cache memory device having a conventional configuration, the cache data holding is performed as the central processing unit 1 executes the instruction data 831, instruction data 832, instruction data 833, and instruction data 834. Instruction data 831, instruction data 832, instruction data 833, and instruction data 834 are stored in each entry of the unit 72.
[0015]
After that, when the central processing unit 1 executes the subsequent instruction data 835, since there is no empty entry in the cache data holding unit, it is necessary to replace the entry in which the instruction data is already stored and store new instruction data. There is.
[0016]
As a result, after the central processing unit executes the instruction data of FIG. 23, the data stored in the cache data holding unit is as shown in FIG. 25, and when the central processing unit attempts to execute the instruction data 831 again. Since the instruction data 831 does not already exist in the cache data holding unit, it is necessary to read it again from the main storage device.
[0017]
As described above, in a processor equipped with a conventional cache memory device, when a repetitive instruction sequence generated by loop unrolling or the like is executed, the capacity of the cache memory becomes insufficient, and the cache memory device operates efficiently. There was a problem that not.
[0018]
[Problems to be solved by the invention]
One method of solving this problem is to increase the number of entries in the cache data holding unit. In this case, however, the amount of memory for storing cache data increases, and the hardware amount of the cache memory device increases. The other problem that the number of the pixels increases.
[0019]
In view of the above problems, the cache memory device of the present invention suppresses the capacity consumption of the cache memory without increasing the amount of hardware even when there is a repeat instruction or the like generated by loop unrolling. The purpose is to enable the use of the system.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a cache memory device according to claim 1 of the present invention is a cache memory provided with a cache system for storing instruction data used in the past among instruction data in a main storage device and efficiently fetching instructions. A cache data holding unit that reads instruction data corresponding to an address requested by the central processing unit from a main storage device and stores the address and the instruction data, and a memory device that corresponds to the address requested by the central processing unit. A pointer indicating the instruction data of the cache data holding unit and a reuse information holding unit storing the address; and the same instruction data as the instruction data read from the main storage device are present in the cache data holding unit. A reuse judging unit for judging whether or not there is an address requested by the central processing unit. A cache control unit that supplies corresponding instruction data to the central processing unit when stored in the cache data holding unit or the reuse information holding unit, and the address requested by the central processing unit is the cache data. When present in the holding unit, the instruction data corresponding to the address requested by the central processing unit stored in the cache data holding unit is output to the central processing unit, and the address requested by the central processing unit is the cache data. If not present in the holding unit but present in the reuse information holding unit, the instruction data indicated by the pointer corresponding to the address requested by the central processing unit stored in the cache data holding unit is sent to the central processing unit. And the address requested by the central processing unit is also stored in the cache data holding unit. If the instruction data does not exist in the main information storage unit, the instruction data corresponding to the address requested by the central processing unit is read from the main storage unit and output to the central processing unit, and is the same as the instruction data read from the main storage unit. When it is determined that the instruction data does not exist in the cache data holding unit, the instruction data read from the main storage device and the corresponding address are stored in the cache data holding unit and are different from the address requested by the central processing unit. If it is determined that the same instruction data as the instruction data read from the main storage device exists even in the address, the data read from the main storage device is stored in the cache data storage portion. Without reusing the pointer pointing to the same instruction data as the address. It is stored in an information holding unit.
[0021]
2. The cache memory device according to claim 1, wherein the cache data holding unit stores the instruction data stored in the main storage device in units of cache lines of a predetermined size. A pointer for indicating the cache line is stored as a pointer to be stored in the usage information holding unit, and the comparison of instruction data in the reuse determination unit is performed in units of the cache line.
[0022]
The cache memory device according to claim 3 is the cache memory device according to claim 1 or 2, wherein the instruction corresponding to the address requested by the central processing unit read from the main storage device at the time of the last cache miss. A read data holding unit for storing data, wherein when the address requested by the central processing unit does not exist in either the cache data holding unit or the reuse information holding unit, the central processing unit Read the instruction data corresponding to the address requested by the main storage device and output the read instruction data to the main storage device, and compare the instruction data read from the main storage device with the instruction data in the read data holding unit. When the instruction data read from the main storage device and its address are stored in the holding unit and the addresses match. Even if the address is different from the address requested by the central processing unit, the data read from the main storage device is not stored in the cache data holding unit, and the pointer pointing to the same instruction data as the address is rewritten. It is stored in a usage information holding unit.
[0023]
According to a fourth aspect of the present invention, in the cache memory device according to the first or second aspect, an address requested by the central processing unit output from the cache data holding unit at the time of a previous cache hit is provided. A fetch line holding unit for storing instruction data, wherein if the address requested by the central processing unit does not exist in the cache data holding unit or the reuse information holding unit, the central processing unit The instruction data corresponding to the address requested by the device is read and output to the main storage device, and the instruction data read from the main storage device is compared with the instruction data in the fetch line holding unit. Instruction data read from the main storage device and its address are stored in a data holding unit. If the addresses match, even if the address is different from the address requested by the central processing unit, the data read from the main storage device is not stored in the cache data holding unit, and the same instruction data as the address is designated. The pointer to be used is stored in the reuse information holding unit.
[0024]
With the above configuration, even when there is a repeat instruction or the like generated by loop unrolling, it is possible to suppress the cache memory capacity consumption and increase the efficiency of the cache memory without increasing the amount of hardware. be able to.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3, 4, 5, and 6. FIG.
[0026]
FIG. 1 is a block diagram showing a configuration of the cache memory device according to the first embodiment of the present invention, and FIG. 2 is a flowchart showing an operation flow of the cache memory device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a program in C language before expansion according to the first embodiment, and FIG. 4 is a diagram illustrating a program after expansion according to the first embodiment. FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are diagrams illustrating an example in which the program developed in the first embodiment is stored in the cache data holding unit and the reuse information holding unit. It shows how it goes.
[0027]
FIG. 1 also shows a central processing unit 1 that is a component of the processor and executes instructions, and a main storage device 3 that stores instructions to be executed by the central processing unit 1. The central processing unit 1 is configured to sequentially execute the instructions read from the main storage device 3 via the cache memory device 2.
[0028]
The cache memory device 2 includes a cache control unit 21 that controls the entire cache memory device, and instruction data in the main storage device 3 corresponding to an address requested by the central processing unit 1 in 16-byte units under the control of the cache control unit 21. And a reuse determination unit 23 that determines whether the same instruction data as the read data D31 read from the main storage device 3 exists in the cache data storage unit 22. And a reuse information holding unit 24 that stores a maximum of four pointers corresponding to the address requested by the central processing unit 1 under the control of the cache control unit 21.
[0029]
In FIG. 2, this control flow is started when the central processing unit 1 outputs a fetch request signal S11.
Next, it is determined whether or not an address that matches the fetch address A11 requested by the central processing unit 1 exists in the cache data holding unit 22, and whether or not the requested instruction data exists (S411). .
[0030]
If the requested instruction data does not exist, it controls the reuse information holding unit 24 and determines whether or not the pointer corresponding to the fetch address A11 exists in the reuse information holding unit 24 (402).
[0031]
When the pointer does not exist, the access request signal S21 and the access address A21 are used as control signals, and the instruction data is read from the main storage device 3 in units of 16 bytes (403). When the pointer exists, the reuse information holding unit 24 The instruction data registered in the cache data holding unit 22 indicated by the pointer corresponding to the fetch address A11 to be held is output to the central processing unit 1 (S408).
[0032]
Next, the reuse determining unit 23 determines whether the same instruction data as the read data D31 read from the main storage device 3 exists in the cache data holding unit 22 (S404).
[0033]
If the same instruction data exists in the cache data holding unit 22, the pointer of the cache line holding the same instruction data as the read data D31 and the fetch address A11 are registered in the reuse information holding unit 24 (S405).
[0034]
In S404, if the same instruction data as the read data D31 does not exist in the cache data holding unit 22, the fetch address A11 and the read data D31 are registered in the cache data holding unit 22 (S406), and the instruction data is stored in the central processing unit. 1 (S407).
[0035]
Further, when the instruction data corresponding to the fetch address A11 is held in the cache data holding unit 22 in S401, the instruction data corresponding to the fetch address A11 stored in the cache data holding unit 22 is output to the central processing unit 1. (S407).
[0036]
When the pointer corresponding to the fetch address A11 is held in the reuse information holding unit 24 in S402, the registration of the cache data holding unit 22 indicated by the pointer corresponding to the fetch address A11 held by the reuse information holding unit 24 The instruction data thus output is output to the central processing unit 1 (S408).
[0037]
The operation of the cache memory device 2 configured as described above when the C language program shown in FIG. 3 is executed will be described.
The assembler program shown in FIG. 4 is an example of the result of compiling the C language program shown in FIG. 3 with loop unrolling. In this example, the instruction of the processor has a fixed length of 4 bytes.
[0038]
The operation of the cache memory device of FIG. 1 when the assembler program of FIG. 4 is executed will be described below.
In the initial state, the cache data holding unit 22 does not hold any instruction data, and the reuse information holding unit 24 does not hold any pointer.
[0039]
First, the central processing unit 1 requests the cache memory device 2 to supply instruction data at address 0x0000 using the fetch request signal S11 and the fetch address A11 as control signals.
[0040]
Upon receiving this request, the cache control unit 21 determines whether or not the instruction data at the address 0x0000 exists in the cache data holding unit 22 (S401 in FIG. 2). As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0000 in the initial state, the cache control unit 21 determines whether the pointer corresponding to the address 0x0000 is registered in the reuse information holding unit 24. Is determined (S402 in FIG. 2).
[0041]
As a result, since the reuse information holding unit 24 does not hold the pointer corresponding to the address 0x0000 in the initial state, the cache control unit 21 uses the access request signal S21 and the access address A21 as control signals, The 16-byte instruction data 811 starting at address 0x0000 is read (S403 in FIG. 2).
[0042]
Next, the cache control unit 21 determines whether the same instruction data as the 16-byte instruction data 811 read from the main storage device 3 exists in the cache data holding unit 22 (S404 in FIG. 2). .
[0043]
As a result, in the initial state, the cache data holding unit 22 does not hold the above-described instruction data, so that the cache control unit 21 sets the fetch address 0x0000 and the instruction data 811 starting from the address 0x0000 read from the main storage device 3. Is registered in the cache data holding unit 22 (S406 in FIG. 2).
[0044]
Next, the cache control unit 21 causes the central processing unit 1 to output the instruction data at the address 0x0000 stored in the cache data holding unit 22 (S407 in FIG. 2). With the above operation, the central processing unit 1 obtains the requested instruction data at the address 0x0000 and starts executing the instruction.
[0045]
According to the above operation, the information stored in the cache data holding unit 22 and the reuse information holding unit 24 respectively store the instruction data 811 corresponding to 0x0000 in the cache data holding unit 22 as shown in FIG. Nothing is stored in the usage information holding unit 24.
[0046]
Next, the central processing unit 1 requests the cache memory device 2 to supply the instruction data at the address 0x0004 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute the subsequent instruction.
[0047]
Upon receiving this request, the cache control unit 21 determines whether or not the instruction data at the address 0x0004 exists in the cache data holding unit 22 (S401 in FIG. 2). As a result, since the cache data holding unit 22 holds the instruction data corresponding to the address 0x0004, the instruction data at the address 0x0004 stored in the cache data holding unit 22 is output to the central processing unit 1 (S407 in FIG. 2). .
[0048]
Through the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0004 and start executing the instruction.
Thereafter, since the cache data holding unit 22 holds the instruction data corresponding to the corresponding address also for the instruction data of the addresses 0x0008 and 0x000C, the cache data holding unit 22 stores the instruction data in the operation of S407 in the flowchart of FIG. Is output to the central processing unit 1.
[0049]
Next, with respect to the instruction data at addresses 0x0010, 0x0014, 0x0018, and 0x001C, 16-byte instruction data 812 starting from address 0x0010 is obtained by the same control as the above-mentioned addresses 0x0000, 0x0004, 0x0008, and 0x000C. After being stored in the cache data holding unit, the cache memory device 2 outputs the instruction data to the central processing unit 1, and as a result, the information respectively stored in the cache data holding unit 22 and the reuse information holding unit 24 is as shown in FIG. Thus, the instruction data of the instruction data 812 is added.
[0050]
Next, the central processing unit 1 requests the cache memory device 2 to issue instruction data at address 0x0020 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute the subsequent instruction.
[0051]
Since the cache data holding unit 22 and the reuse information holding unit 24 do not hold the corresponding addresses, the cache control unit 21 uses the access request signal S21 and the access address A21 as control signals, and stores the address 0x0020 from the main storage device 3. The first 16 bytes of instruction data 813 are read (S403 in FIG. 2).
[0052]
Next, the cache control unit 21 determines whether the same instruction data as the 16-byte instruction data 813 read from the main storage device 3 exists in the cache data holding unit 22 (S404 in FIG. 2). .
[0053]
As a result, since the cache data holding unit 22 holds the same instruction data as the above-mentioned instruction data (entry “1” of the cache data holding unit in FIG. 6), the cache control unit 21 The fetch address 0x0020 and the entry “1” of the cache data holding unit 22 holding the instruction data are registered (S405 in FIG. 2).
[0054]
Next, the cache control unit 21 centrally processes the instruction data corresponding to the address 0x0010 as the instruction data stored in the cache data storage unit 22 for the entry “1” corresponding to the fetch address 0x0020 stored in the reuse information storage unit 24. Output to the device 1 (S408 in FIG. 2).
[0055]
With the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0020 and start executing the instruction.
Further, the information stored in the cache data holding unit 22 and the reuse information holding unit 24 change as shown in FIG. 7 by the above operation.
[0056]
Next, the central processing unit 1 requests the cache memory device 2 to issue instruction data at address 0x0024 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute the subsequent instruction.
[0057]
Upon receiving this request, the cache control unit 21 determines whether or not the instruction data at the address 0x0024 exists in the cache data holding unit 22 (S401 in FIG. 2). As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0024, the cache control unit 21 determines whether the pointer corresponding to the instruction data at the address 0x0024 is registered in the reuse information holding unit 24. It is determined whether or not it is (S402 in FIG. 2).
[0058]
As a result, since the reuse information holding unit 24 holds the pointer corresponding to the instruction data at the address 0x0024, the cache control unit 21 sets the entry “1” corresponding to the fetch address 0x0024 stored in the reuse information holding unit 24. The instruction data corresponding to the address 0x0014 is actually output to the central processing unit 1 as the instruction data stored in the cache data holding unit 22 ("S408" in FIG. 2).
[0059]
Through the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0024 and start executing the instruction.
Thereafter, since the reuse information holding unit 24 holds the instruction data corresponding to the corresponding pointer also at the instruction data of the addresses 0x0028 and 0x002C, the operation of the reuse information holding unit 24 is performed by the operation of S408 in the flowchart of FIG. The instruction data stored in the cache data holding unit 22 is output to the central processing unit 1 for the entry “1” corresponding to the corresponding address held by.
[0060]
Next, with respect to the instruction data from address 0x0030 to address 0x005C, the cache memory device outputs the instruction data to the central processing unit 1 by the same control as the above-mentioned address from address 0x0020 to address 0x002C. The information stored in the storage 22 and the reuse information storage unit 24 change as shown in FIG.
[0061]
As described above, in the cache memory device according to the first embodiment, when the same instruction data exists in the cache data holding unit even when the repeated instruction sequence generated by the loop unrolling is executed, the reuse information is held. Since a pointer corresponding to the instruction data is stored in the section and the entry of the cache data holding section is not consumed, even when there is a repeated instruction generated by loop unrolling, without increasing the amount of hardware, The capacity consumption of the cache memory can be suppressed, and the cache memory can be used efficiently.
(Embodiment 2)
Next, a cache memory device according to a second embodiment of the present invention will be described with reference to FIGS. 3, 4, 9, 10, 11, 12, 13, and 14. FIG.
[0062]
FIG. 9 is a block diagram illustrating a configuration of a cache memory device according to the second embodiment of the present invention, and FIG. 10 is a flowchart illustrating an operation flow of the cache memory device according to the second embodiment of the present invention. FIGS. 11, 12, 13, and 14 are diagrams illustrating a state where the program developed in the second embodiment is stored in the cache data holding unit and the reuse information holding unit. It shows how it goes.
[0063]
FIG. 9 also shows a central processing unit 1 that is a component of the processor and executes instructions, and a main storage device 3 that stores instructions to be executed by the central processing unit 1.
[0064]
The central processing unit 1 is configured to sequentially execute the instructions read from the main storage device 3 via the cache memory device 5.
The cache memory device 5 includes a cache control unit 51 that controls the entire cache memory device, and command data in the main storage device 3 corresponding to an address requested by the central processing unit 1 in 16-byte units under the control of the cache control unit 51 A cache data holding unit 22 for storing a maximum of four entries, a read data holding unit 531 for storing read data D31 read when a cache miss occurred immediately before under the control of the cache control unit 51, and a read data read from the main storage device. D31, a reuse determination unit 532 that determines whether the instruction data stored in the read data holding unit 531 is the same, and reuse information corresponding to an address requested by the central processing unit 1 under the control of the cache control unit 51. And a reuse information holding unit 24 for storing up to four entries of There.
[0065]
Next, the operation of the cache memory device will be described with reference to FIG.
In FIG. 10, first, a fetch request signal S11 from the central processing unit 1 is output.
[0066]
Steps S401, S402, S403, S406, S407, and S408 are the same as the operations shown in the flowchart of FIG.
[0067]
After reading the instruction data corresponding to the fetch address A11 from the main storage device 3, the cache control unit 51 determines whether the read data D31 read from the main storage device 3 and the cache data immediately before being stored in the read data holding unit 531. It is determined whether the instruction data at the time of the miss is the same (S409).
[0068]
If they are the same, the cache control unit 51 stores the fetch address A11 and the pointer held by the read data holding unit 531 in the reuse information holding unit 24 (S410).
[0069]
If they are not the same, the fetch address A11 and the read data D31 are registered in the cache data holding unit 22 (S406), and the cache control unit 51 reads the read data D31 read from the main storage device and the cache data in which the read data D31 is stored. The entry of the holding unit 22 is stored in the read data holding unit 531 (S411).
[0070]
The operation of the cache memory device 5 configured as described above when the C language program shown in FIG. 3 is executed will be described.
The operation of the cache memory device 5 of FIG. 9 when the assembler program of FIG. 4 is executed will be described below.
[0071]
In the initial state, the cache data holding unit 22 does not hold any instruction data, the reuse information holding unit 24 does not hold any pointer, and the read data holding unit 531 does not hold any instruction data.
[0072]
First, the central processing unit 1 requests the cache memory device 5 for instruction data at address 0x0000 using the fetch request signal S11 and the fetch address A11 as control signals.
[0073]
Upon receiving this request, the cache control unit 51 determines whether or not the instruction data at the address 0x0000 exists in the cache data holding unit 22 (S401 in FIG. 10).
[0074]
As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0000 in the initial state, the cache control unit 51 determines whether the pointer corresponding to the address 0x0000 is registered in the reuse information holding unit 24. Is determined (S402 in FIG. 10).
[0075]
As a result, since the reuse information holding unit 24 does not hold the pointer corresponding to the address 0x0000 in the initial state, the cache control unit 51 sets the access request signal S51 and the access address A51 as control signals, and The 16-byte instruction data 811 starting from address 0x0000 is read (S403 in FIG. 10).
[0076]
Next, the cache control unit 51 determines whether the instruction data 811 read from the main storage device matches the instruction data held by the read data holding unit 531 (S409 in FIG. 10).
[0077]
As a result, the read data holding unit 531 does not hold any instruction data in the initial state, and the instruction data does not match. Therefore, the cache control unit 51 caches the fetch address 0x0000 and the instruction data 811 read from the main storage device 3. It is registered in the data holding unit 22 (S406 in FIG. 10).
[0078]
Next, the cache control unit 51 stores the instruction data 811 read from the main storage device 3 and the entry (here, “0”) of the cache data holding unit storing the read data D31 in the read data holding unit 531. (S411 in FIG. 10).
[0079]
Next, the cache control unit 51 controls the cache data holding unit 22 to cause the central processing unit 1 to output the instruction data at the address 0x0000 stored in the cache data holding unit 22 (S407 in FIG. 10).
[0080]
With the above operation, the central processing unit 1 obtains the requested instruction at the address 0x0000 and starts executing the instruction.
By the above operation, the information stored in the cache data holding unit 22, the reuse information holding unit 24, and the read data holding unit 531 are stored in the cache data holding unit 22, the read data holding unit 531 as shown in FIG. Stores instruction data 811 corresponding to 0x0000, and nothing is stored in the reuse information holding unit 24.
[0081]
Next, the central processing unit 1 requests the cache memory device 5 to issue instruction data at address 0x0004 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute the subsequent instruction.
[0082]
In response to this request, the cache control unit 51 determines whether or not the instruction data at the address 0x0004 exists in the cache data holding unit 22 (S401 in FIG. 10).
[0083]
As a result, since the cache data holding unit 22 holds the instruction data corresponding to the address 0x0004, the cache control unit 51 causes the central processing unit 1 to output the instruction data at the address 0x0004 stored in the cache data holding unit 22 ( S407 in FIG. 10).
[0084]
Through the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0004 and start executing the instruction.
Thereafter, since the cache data holding unit 22 holds the instruction data corresponding to the corresponding address also for the instruction data of the addresses 0x0008 and 0x000C, the cache data holding unit 22 stores the instruction data in the operation of S407 in the flowchart of FIG. Command data to be output to the central processing unit 1.
[0085]
Next, the central processing unit 1 requests the cache memory device 5 to issue instruction data at the address 0x0010 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute a subsequent instruction.
[0086]
Upon receiving this request, the cache control unit 51 determines whether or not the instruction data at the address 0x0010 exists in the cache data holding unit 22 (S401 in FIG. 10).
[0087]
As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0010, the cache control unit 51 determines whether the pointer corresponding to the address 0x0010 is registered in the reuse information holding unit 24. (S402 in FIG. 10).
[0088]
As a result, since the reuse information holding unit 24 does not hold the pointer corresponding to the address 0x0010, the cache control unit 51 uses the access request signal S51 and the access address A51 as control signals, and stores the address 0x0010 from the main storage device 3. The first 16 bytes of instruction data 812 are read (S403 in FIG. 10).
[0089]
Next, the cache control unit 51 determines whether the instruction data 812 read from the main storage device matches the instruction data held by the read data holding unit 531 (S409 in FIG. 10).
[0090]
As a result, since the instruction data 811 held by the read data holding unit 531 does not match the instruction data 812 read from the main storage device 3, the fetch address 0x0010 and the instruction data 812 read from the main storage device 3 are It is registered in the cache data holding unit 22 (S406 in FIG. 10).
[0091]
Next, the cache control unit 51 stores the instruction data 812 read from the main storage device 3 and the entry (here, “1”) of the cache data holding unit 22 in which the instruction data 812 is stored, in the read data holding unit. 531 (S411 in FIG. 10).
[0092]
Next, the cache control unit 51 outputs the instruction data at the address 0x0010 stored in the cache data holding unit 22 to the central processing unit 1 (S407 in FIG. 10). With the above operation, the central processing unit 1 obtains the requested instruction data at the address 0x0010 and starts executing the instruction.
[0093]
Next, for the instruction data at addresses 0x0014, 0x0018, and 0x001C, the cache memory device 5 outputs the instruction data to the central processing unit 1 under the same control as the addresses 0x0004, 0x0008, and 0x000C described above. As a result, the information stored in the cache data holding unit 22, the reuse information holding unit 24, and the read data holding unit 531 changes as shown in FIG.
[0094]
Next, the central processing unit 1 requests the instruction data at the address 0x0020 to the cache memory device 5 using the fetch request signal S11 and the fetch address A11 as control signals to execute the subsequent instruction.
[0095]
Since the cache data holding unit 22 and the reuse information holding unit 24 do not hold the corresponding addresses, the cache control unit 51 uses the access request signal S51 and the access address A51 as control signals, and stores the address 0x0020 from the main storage device 3. The first 16 bytes of instruction data 813 are read (S403 in FIG. 10).
[0096]
Next, the cache control unit 51 determines whether the instruction data 813 read from the main storage device matches the instruction data held by the read data holding unit 531 (S409 in FIG. 10).
[0097]
As a result, since the instruction data 812 stored in the read data holding unit 531 matches the instruction data 813 read from the main storage device 3, the cache control unit 51 stores the fetch address 0x0020 in the reuse information holding unit 24 with the fetch address 0x0020. The entry number “1” stored in the data holding unit is registered (S410 in FIG. 10).
[0098]
Next, the cache control unit 51 determines that the entry data “1” corresponding to the fetch address 0x0020 stored in the reuse information storage unit 24 is the instruction data actually stored in the cache data storage unit 22 as the instruction data corresponding to the address 0x0010. Is output to the central processing unit 1 (S408 in FIG. 10).
[0099]
With the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0020 and start executing the instruction.
Further, by the above operation, the information stored in the cache data holding unit 22, the reuse information holding unit 24, and the read data holding unit 531 change as shown in FIG.
[0100]
Next, the central processing unit 1 requests the instruction data at the address 0x0024 to the cache memory device 5 using the fetch request signal S11 and the fetch address A11 as control signals to execute the subsequent instruction.
[0101]
Upon receiving this request, the cache control unit 51 determines whether or not the instruction data at the address 0x0024 exists in the cache data holding unit 22 (S401 in FIG. 10).
[0102]
As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0024, the cache control unit 51 determines whether the pointer corresponding to the instruction data at the address 0x0024 is registered in the reuse information holding unit 24. Is determined (S402 in FIG. 10).
[0103]
As a result, since the reuse information holding unit 24 holds the pointer corresponding to the instruction data at the address 0x0024, the cache control unit 51 sets the entry “1” corresponding to the fetch address 0x0024 stored in the reuse information holding unit 24. The instruction data (actually, the instruction data corresponding to the address 0x0014) stored in the cache data holding unit 22 is output to the central processing unit 1 (S408 in FIG. 10).
[0104]
Through the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0024 and start executing the instruction.
Thereafter, since the reuse information holding unit 24 holds the instruction data corresponding to the corresponding address also for the instruction data at the addresses 0x0028 and 0x002C, the reuse information holding unit 24 performs the operation of S408 in the flowchart of FIG. The instruction data stored in the cache data holding unit 22 for the entry “1” corresponding to the held address is output to the central processing unit 1.
[0105]
Next, with respect to the instruction data from address 0x0030 to address 0x005C, the cache memory device outputs the instruction data to the central processing unit 1 by the same control as the above-mentioned address from address 0x0020 to address 0x002C. The information stored in the storage unit 22 and the information stored in the reuse information storage unit 24 change as shown in FIG.
[0106]
As described above, in the cache memory device according to the second embodiment, when the same instruction data exists in the cache data holding unit even when the repeated instruction sequence generated by the loop unrolling is executed, the reuse information is held. A storage unit for storing a pointer corresponding to the instruction data, and further comprising a reuse determination unit for comparing the instruction data read from the main storage device with the instruction data read at the time of the immediately preceding cache miss. The target of comparison of the instruction data read from the main memory can be limited to the instruction data read immediately before from the main storage device. Even if there is a repeated instruction generated by loop unrolling, the amount of hardware can be reduced. It is possible to reduce cache memory capacity consumption and increase the efficiency of cache memory usage without increasing Kill.
(Embodiment 3)
Next, a cache memory device according to the third embodiment of the present invention will be described with reference to FIGS. 3, 4, 15, 15, 16, 17, 18, 19, and 20. FIG.
[0107]
FIG. 15 is a block diagram showing a configuration of the cache memory device according to the third embodiment of the present invention, and FIG. 16 is a flowchart showing an operation flow of the cache memory device according to the third embodiment of the present invention. FIG. 17, FIG. 18, FIG. 19, and FIG. 20 are diagrams illustrating an example in which the program developed in the third embodiment is stored in the fetch line holding unit and the reuse information holding unit. It shows how it goes.
[0108]
FIG. 15 also shows a central processing unit 1 that is a component of the processor and executes instructions, and a main storage device 3 that stores instructions to be executed by the central processing unit 1.
[0109]
The central processing unit 1 is configured to sequentially execute the instructions read from the main storage device 3 via the cache memory device 6.
The cache memory device 6 includes a cache control unit 61 that controls the entire cache memory device, and instruction data in the main storage device 3 corresponding to an address requested by the central processing unit 1 in 16-byte units under the control of the cache control unit 61 A fetch line holding unit 631 for storing instruction data of a cache line that has just hit a cache hit immediately before being held by the cache data holding unit under the control of the cache control unit 61 under the control of the cache control unit 61; From the read data D31 read from the fetch line holding unit 631, the reuse determination unit 632 that determines whether the instruction data is the same as the instruction data stored in the fetch line holding unit 631, and the fetch address A11 and the fetch address A11 according to the control of the cache control unit 51. Up to the corresponding pointer And a re-use information holding unit 24 for entry storage.
[0110]
In FIG. 16, this control flow is started when the central processing unit 1 outputs a fetch request signal S11.
Steps S401, S402, S403, S406, S407, and S408 are the same as the operations shown in the flowchart of FIG.
[0111]
After reading the instruction data corresponding to the fetch address in S403, the cache control unit 61 determines whether the read data D31 read from the main storage device 3 is the same as the instruction data stored in the fetch line holding unit 631. It is determined whether or not it is (S412).
[0112]
If they match, the cache control unit 61 controls the reuse information holding unit 24, and stores the fetch address A11 and the pointer held by the fetch line holding unit 631 in the reuse information holding unit 24 (S413).
[0113]
After outputting the instruction data to the central processing unit 1 in S407, the cache control unit 61 stores a pointer to the cache line containing the instruction data output from the cache data holding unit 22 to the central processing unit 1 and the cache line. The stored instruction data is stored in the fetch line holding unit 631 (S414).
[0114]
The operation of the cache memory device 6 configured as described above when the C language program shown in FIG. 3 is executed will be described.
The assembler program shown in FIG. 4 is an example of the result of compiling the C language program shown in FIG. 3 with loop unrolling. In this example, the instruction of the processor has a fixed length of 4 bytes.
[0115]
The operation when the assembler program of FIG. 4 is executed on the cache memory device 6 of FIG. 15 will be described below.
In the initial state, the cache data holding unit 22 does not hold any instruction data, the reuse information holding unit 24 does not hold any pointer, and the fetch line holding unit 631 does not hold any instruction data. .
[0116]
The central processing unit 1 requests the cache memory device 6 to supply the instruction at the address 0x0000 by controlling the fetch request signal S11 and the fetch address A11.
Upon receiving this request, the cache control unit 61 controls the cache data holding unit 22 and determines whether or not an instruction at the address 0x0000 exists in the cache data holding unit 22 (S401 in FIG. 16).
[0117]
As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0000 in the initial state, the cache control unit 61 registers the pointer corresponding to the address of the address 0x0000 in the reuse information holding unit 24. It is determined whether or not it has been performed (S402 in FIG. 16).
[0118]
As a result, since the reuse information holding unit 24 does not hold the pointer corresponding to the address 0x0000 in the initial state, the cache control unit 61 uses the access request signal S21 and the access address A21 as control signals, The 16-byte instruction data 811 starting at address 0x0000 is read (operation of S403 in FIG. 16).
[0119]
Next, the cache control unit 61 determines whether the instruction data 811 read from the main storage device matches the instruction data held by the read data holding unit 631 (operation S412 in FIG. 16).
[0120]
As a result, the read data holding unit 631 does not hold any instruction data in the initial state, and the instruction data does not match. It is registered in the cache data holding unit 22 (operation of S406 in FIG. 16).
[0121]
Next, the cache control unit 61 outputs the instruction data at the address 0x0000 stored in the cache data holding unit 22 to the central processing unit 1 (operation of S407 in FIG. 16).
[0122]
Next, the cache control unit 61 stores a pointer “0” to the cache line including the instruction data at the address 0x0000 output from the cache data holding unit to the central processing unit 1 and fetches the instruction data included in the cache line into the fetch line. It is stored in the holding unit 631.
[0123]
With the above operation, the central processing unit 1 obtains the requested instruction data at the address 0x0000 and starts executing the instruction.
By the above operation, the information stored in the cache data holding unit 22, the reuse information holding unit 24, and the fetch line holding unit 631, respectively, becomes as shown in FIG.
[0124]
Next, the central processing unit 1 requests the cache memory device 5 to supply the instruction data at the address 0x0004 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute the subsequent instruction.
[0125]
Upon receiving this request, the cache control unit 51 determines whether or not the instruction data at the address 0x0004 exists in the cache data holding unit 22 (operation of S401 in FIG. 16).
[0126]
As a result, since the cache data holding unit 22 holds the instruction data corresponding to the address 0x0004, the cache control unit 51 outputs the instruction data at the address 0x0004 stored in the cache data holding unit 22 to the central processing unit 1. (Operation of S407 in FIG. 16).
[0127]
Next, the cache control unit 61 stores a pointer “0” to the cache line containing the instruction data at the address 0x0004 output from the cache data holding unit to the central processing unit 1 and fetches the instruction data contained in the cache line into the fetch line. The data is stored in the holding unit 631.
[0128]
Through the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0004 and start executing the instruction.
Thereafter, since the cache data holding unit 22 holds the instruction data corresponding to the corresponding addresses also at the instruction data of the addresses 0x0008 and 0x000C, the cache data holding unit 22 stores the instruction data at the operation 407 in the flowchart of FIG. Is output to the central processing unit 1.
[0129]
Next, the central processing unit 1 requests the cache memory device 6 for instruction data at address 0x0010 using the fetch request signal S11 and the fetch address A11 as control signals in order to execute the subsequent instruction.
[0130]
Upon receiving this request, the cache control unit 61 determines whether or not the instruction data at the address 0x0010 exists in the cache data holding unit 22 (operation of S401 in FIG. 16).
[0131]
As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0010, the cache control unit 61 determines whether a pointer to the address 0x0010 is registered in the reuse information holding unit 24. (Operation of S402 of FIG. 16).
[0132]
As a result, since the reuse information holding unit 24 does not hold the address corresponding to the address 0x0010, the cache control unit 61 uses the access request signal S61 and the access address A61 as control signals, and stores the address 0x0010 from the main storage device 3. The 16-byte instruction data 812 at the head is read (operation of S403 in FIG. 16).
[0133]
Next, the cache control unit 61 controls the reuse determination unit 632 to determine whether the instruction data 812 read from the main storage device 3 matches the instruction data held by the fetch line holding unit 631. (Operation of S412 in FIG. 16).
[0134]
As a result, since the instruction data 811 held by the fetch line holding unit 631 does not match the instruction data 812 read from the main storage device 3, the fetch address 0x0010 and the instruction data 812 read from the main storage device 3 are It is registered in the cache data holding unit 22 (operation of S406 in FIG. 16).
[0135]
Next, the cache control unit 61 outputs the instruction data at the address 0x0010 stored in the cache data holding unit 22 to the central processing unit 1 (operation of S407 in FIG. 16).
[0136]
Next, the cache control unit 61 fetches the pointer “1” to the cache line including the instruction data at the address 0x0010 output from the cache data holding unit 22 to the central processing unit 1 and the instruction data included in the cache line. It is stored in the line holding unit 631.
[0137]
With the above operation, the central processing unit 1 obtains the requested instruction data at the address 0x0010 and starts executing the instruction.
Next, for the instruction data at addresses 0x0014, 0x0018, and 0x001C, the cache memory device 6 outputs the instruction data to the central processing unit 1 under the same control as the addresses 0x0004, 0x0008, and 0x000C described above. As a result, the information respectively stored in the cache data holding unit 22 and the reuse information holding unit 24 changes as shown in FIG.
[0138]
Next, the central processing unit 1 requests the cache memory device 6 to supply the instruction data at the address 0x0020 using the fetch request signal S11 and the fetch address A11 as control signals to execute the subsequent instruction.
[0139]
Since the cache data holding unit 22 and the reuse information holding unit 24 do not hold the corresponding address, the cache control unit 61 uses the access request signal S61 and the access address A61 as control signals, and stores the address 0x0020 from the main storage device 3. The 16-byte instruction data 813 at the head is read (operation of S403 in FIG. 16).
[0140]
Next, the cache control unit 61 determines whether the instruction data 813 read from the main storage device 3 matches the instruction data 812 held by the fetch line holding unit 631 (operation of S412 in FIG. 16). ).
[0141]
As a result, the instruction data 812 stored in the fetch line holding unit 631 and the instruction data 813 read from the main storage device 3 match, so that the cache control unit 61 stores the fetch address 0x0020 in the reuse information holding unit 24 with the read address 0x0020. The pointer “1” stored in the data holding unit is registered (operation of S413 in FIG. 16).
[0142]
Next, the cache control unit 61 determines that the entry data “1” corresponding to the fetch address 0x0020 stored in the reuse information storage unit 24 is the instruction data actually stored in the cache data storage unit 22 as the instruction data corresponding to the address 0x0010. Is output to the central processing unit 1 (operation of S408 in FIG. 16).
[0143]
Next, the cache control unit 61 controls the cache data holding unit 22 and the fetch line holding unit 631, and sets a pointer to a cache line containing the instruction at the address 0x0010 output to the central processing unit 1 by the cache data holding unit. “1” and the instruction data included in the cache line are stored in the fetch line holding unit 631.
[0144]
With the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0020 and start executing the instruction.
Further, by the above operation, the information stored in the cache data holding unit 22 and the information stored in the reuse information holding unit 24 change as shown in FIG.
[0145]
Next, the central processing unit 1 requests the cache memory device 6 to supply the instruction data at the address 0x0024 using the fetch request signal S11 and the fetch address A11 as control signals to execute the subsequent instruction.
[0146]
In response to this request, the cache control unit 61 controls the cache data holding unit 22 and determines whether or not the instruction data at the address 0x0024 exists in the cache data holding unit 22 (operation of S401 in FIG. 16).
[0147]
As a result, since the cache data holding unit 22 does not hold the instruction data corresponding to the address 0x0024, the cache control unit 61 determines whether or not the pointer corresponding to the address of the address 0x0024 is registered in the reuse information holding unit 24. Is determined (operation of S402 in FIG. 16).
[0148]
As a result, since the reuse information holding unit 24 holds the pointer corresponding to the address of the address 0x0024, the cache control unit 61 sets the pointer “1” corresponding to the fetch address 0x0024 stored in the reuse information holding unit 24. The instruction data corresponding to the address 0x0014 is actually output to the central processing unit 1 as the instruction data stored in the cache data holding unit 22 (operation of S408 in FIG. 16).
[0149]
Next, the cache control unit 61 stores a pointer “1” to the cache line containing the instruction data at the address 0x0010 output from the cache data holding unit to the central processing unit 1 and fetches the instruction data contained in the cache line into the fetch line. The information is stored in the holding unit 631 (operation of S414 in FIG. 16).
[0150]
Through the above operation, the central processing unit 1 can obtain the requested instruction data at the address 0x0024 and start executing the instruction.
Thereafter, since the reuse information holding unit 24 holds the pointer corresponding to the corresponding address also for the instruction data of the addresses 0x0028 and 0x002C, the reuse information holding unit 24 operates by the operation of S408 in the flowchart of FIG. The instruction data stored in the cache data holding unit 22 for the entry “1” corresponding to the held address is output to the central processing unit 1.
[0151]
Next, for the instruction data from addresses 0x0030 to 0x005C, the cache memory device outputs the instruction data to the central processing unit 1 under the same control as the above-mentioned addresses from 0x0020 to 0x002C. The information stored in the storage 22 and the information stored in the reuse information storage unit 24 change as shown in FIG.
[0152]
As described above, in the cache memory device according to the third embodiment, when the same instruction data exists in the cache data holding unit even when the repeated instruction sequence generated by the loop unrolling is executed, the reuse information is held. Section stores a pointer corresponding to the instruction data, and limits the comparison of the instruction data to the instruction data of the cache line that has just hit the cache. In addition, the capacity consumption of the cache memory can be suppressed without increasing the amount of hardware, and the cache memory can be used efficiently.
[0153]
【The invention's effect】
As described above, in the cache memory device according to the present invention, when the same instruction data is present in the cache data holding unit even when the repeated instruction sequence generated by the loop unrolling is executed, the same is stored in the reuse information holding unit. Since the pointer corresponding to the instruction data is stored and the entry of the cache data holding unit is not consumed, even when there is a repeat instruction generated by loop unrolling, the amount of hardware in the cache memory is not increased without increasing the amount of hardware. Capacity consumption can be suppressed, and efficient use of the cache memory can be achieved.
[0154]
In addition, by providing a reuse determination unit that compares the instruction data read from the main storage device with the instruction data read at the time of the immediately preceding cache miss, the target of comparison of the instruction data read from the main storage device is set to Can be limited to the instruction data read from the main storage device, and even when there are repeated instructions generated by loop unrolling, the capacity consumption of the cache memory is suppressed without increasing the amount of hardware. However, efficient use of the cache memory can be enabled.
[0155]
Further, by limiting the comparison of the instruction data to the instruction data of the cache line that has just hit the cache, even if there is a repeated instruction generated by loop unrolling, the amount of hardware is not increased. The capacity consumption of the cache memory can be suppressed, and the cache memory can be used efficiently.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a cache memory device according to a first embodiment of the present invention.
FIG. 2 is a flowchart showing an operation flow of the cache memory device according to the first embodiment of the present invention;
FIG. 3 is a diagram showing a program in C language before expansion according to the first embodiment.
FIG. 4 is a diagram showing an expanded program according to the first embodiment;
FIG. 5 is a diagram illustrating an example in which a program developed in the first embodiment is stored in a cache data holding unit and a reuse information holding unit;
FIG. 6 is a diagram exemplifying a state where a program developed in the first embodiment is stored in a cache data holding unit and a reuse information holding unit;
FIG. 7 is a diagram illustrating an example of a state where a program developed in the first embodiment is stored in a cache data holding unit and a reuse information holding unit;
FIG. 8 is a diagram illustrating an example in which a program developed in the first embodiment is stored in a cache data holding unit and a reuse information holding unit;
FIG. 9 is a block diagram showing a configuration of a cache memory device according to a second embodiment of the present invention.
FIG. 10 is a flowchart showing an operation flow of the cache memory device according to the second embodiment of the present invention;
FIG. 11 is a diagram illustrating an example in which a program developed in the second embodiment is stored in a cache data holding unit, a reuse information holding unit, and a read data holding unit;
FIG. 12 is a diagram illustrating an example in which a program developed in the second embodiment is stored in a cache data holding unit, a reuse information holding unit, and a read data holding unit;
FIG. 13 is a diagram illustrating an example in which a program developed in the second embodiment is stored in a cache data holding unit, a reuse information holding unit, and a read data holding unit;
FIG. 14 is a diagram illustrating an example in which a program developed in the second embodiment is stored in a cache data holding unit, a reuse information holding unit, and a read data holding unit;
FIG. 15 is a block diagram showing a configuration of a cache memory device according to a third embodiment of the present invention.
FIG. 16 is a flowchart showing an operation flow of the cache memory device according to the third embodiment of the present invention;
FIG. 17 is a diagram illustrating an example of a state where a program developed in the third embodiment is stored in a fetch line holding unit and a reuse information holding unit;
FIG. 18 is a diagram exemplifying a state where a program developed in the third embodiment is stored in a fetch line holding unit and a reuse information holding unit;
FIG. 19 is a diagram exemplifying a state where a program developed in the third embodiment is stored in a fetch line holding unit and a reuse information holding unit;
FIG. 20 is a diagram exemplifying a state where a program developed in the third embodiment is stored in a fetch line holding unit and a reuse information holding unit;
FIG. 21 is a block diagram showing a configuration of a conventional cache memory device;
And FIG. 22 is a flowchart showing an operation flow of a conventional cache memory device.
FIG. 23 is a diagram showing a program in C language before expansion.
FIG. 24 is a diagram showing a program after expansion.
FIG. 25 is a diagram illustrating an example of a state where a program developed in the related art is stored in a cache data holding unit.
[Explanation of symbols]
1 Central processing unit
S11 Fetch request signal
A11 Fetch address
2 Cache memory device
21 Cache control unit
22 Cache data holding unit
23 Reuse determination unit
24 Reuse information storage
S21 access request signal
A21 access address
3 Main storage device
D31 Read data
5 Cache memory device
51 Cache control unit
531 Read data holding unit
532 Reuse determination unit
S51 Access request signal
A51 access address
6. Cache memory device
61 Cache control unit
631 fetch line holding unit
632 Reuse determination unit
S61 Access request signal
A61 access address
7 Cache memory device
71 Cache control unit
72 Cache data holding unit
S71 Access request signal
A71 access address
811 Instruction data
812 instruction data
813 Instruction data
814 instruction data
815 instruction data
816 instruction data
831 instruction data
832 instruction data
833 instruction data
834 instruction data
835 instruction data

Claims (4)

A cache memory device provided with a cache system for storing instruction data used in the past and efficiently fetching instruction data among instruction data in a main storage device, wherein instruction data corresponding to an address requested by a central processing unit is mainly stored. A cache data holding unit that reads from the storage device and stores the address and the instruction data;
A reuse information holding unit that stores the address and the pointer that indicates the instruction data of the cache data holding unit corresponding to the address requested by the central processing unit,
A reuse determination unit that determines whether the same instruction data as the instruction data read from the main storage device exists in the cache data holding unit;
A cache control unit that supplies corresponding instruction data to the central processing unit when an address requested by the central processing unit is stored in the cache data holding unit or the reuse information holding unit; When the address requested by the central processing unit is present in the cache data holding unit, the instruction data corresponding to the address requested by the central processing unit stored in the cache data holding unit is output to the central processing unit, When the address requested by the central processing unit does not exist in the cache data holding unit but exists in the reuse information holding unit, the pointer corresponding to the address requested by the central processing unit stored in the cache data holding unit is used. The designated instruction data is output to the central processing unit, and an address requested by the central processing unit is output. If the cache does not exist in the cache data holding unit or the reuse information holding unit, the command data corresponding to the address requested by the central processing unit is read from the main storage device and output to the central processing unit. If it is determined that the same instruction data as the instruction data read from the main storage device does not exist in the cache data holding unit, the instruction data read from the main storage device and the corresponding address are stored in the cache data holding unit. If it is determined that the same instruction data as the instruction data read from the main storage device exists in the cache data holding unit even if the address is different from the address requested by the central processing unit, the instruction data is read from the main storage device. The data is not stored in the cache data holding unit but is stored in the same address as the address. Cache memory device and to store the pointer to the instruction data to the re-use information holding unit. The cache data holding unit stores the instruction data stored in the main storage device in units of cache lines of a predetermined size,
Storing a pointer indicating the cache line as a pointer to be stored in the reuse information holding unit,
2. The cache memory device according to claim 1, wherein the comparison of the instruction data in the reuse determination unit is performed for each cache line. A read data holding unit that stores instruction data corresponding to an address requested by the central processing unit read from the main storage device at the time of the last cache miss,
If the address requested by the central processing unit does not exist in the cache data holding unit nor in the reuse information holding unit, read instruction data corresponding to the address requested by the central processing unit from the main storage device. The command data output to the main storage device and the command data read from the main storage device are compared with the command data in the read data holding unit. If they do not match, the command data read from the main storage device is stored in the cache data holding unit. And if the addresses match, the data read from the main storage device is not stored in the cache data holding unit even if the address is different from the address requested by the central processing unit, and the address and the address are stored. A pointer pointing to the same instruction data is stored in the reuse information holding unit. Claim 1 or the cache memory apparatus according to claim 2, wherein. A fetch line holding unit that stores instruction data corresponding to an address requested by the central processing unit output from the cache data holding unit at the time of the last cache hit,
If the address requested by the central processing unit does not exist in the cache data holding unit nor in the reuse information holding unit, read instruction data corresponding to the address requested by the central processing unit from the main storage device. The instruction data output to the main storage device and the instruction data read from the main storage device are compared with the instruction data in the fetch line holding unit. If they do not match, the instruction data read from the main storage device is stored in the cache data holding unit. And if the addresses match, the data read from the main storage device is not stored in the cache data holding unit even if the address is different from the address requested by the central processing unit, and the address and the address are stored. A pointer pointing to the same instruction data is stored in the reuse information holding unit. Motomeko 1 or the cache memory apparatus according to claim 2, wherein.

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