CN103210377A - Information processing system - Google Patents

Information processing system Download PDF

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Publication number
CN103210377A
CN103210377A CN 201080070129 CN201080070129A CN103210377A CN 103210377 A CN103210377 A CN 103210377A CN 201080070129 CN201080070129 CN 201080070129 CN 201080070129 A CN201080070129 A CN 201080070129A CN 103210377 A CN103210377 A CN 103210377A
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information
processing system
state
bus
information processing
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CN 201080070129
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Chinese (zh)
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CN103210377B (en )
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山下浩一郎
山内宏真
铃木贵久
栗原康志
早川文彦
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富士通株式会社
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/325Power saving in peripheral device
    • G06F1/3275Power saving in memory, e.g. RAM, cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3206Monitoring a parameter, a device or an event triggering a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3237Power saving by disabling clock generation or distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/12Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply acting upon the main processing unit
    • Y02D10/128Clock disabling
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/13Access, addressing or allocation within memory systems or architectures, e.g. to reduce power consumption or heat production or to increase battery life
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing
    • Y02D10/10Reducing energy consumption at the single machine level, e.g. processors, personal computers, peripherals or power supply
    • Y02D10/14Interconnection, or transfer of information or other signals between, memories, peripherals or central processing units

Abstract

Access conflicts for a shared resource (106) are resolved while minimizing power consumption in an information processing system (100). A bus controller (108) detects first information expressing a cache hit or a cache miss of a CPU (101) and a CPU (102) using a cache miss detection unit (119). In addition, the bus controller (108) detects second information expressing an activated state or an inactivated state of a DMA controller (103) and a DMA controller (104) using a high-speed I/O detection unit (120). The bus controller (108) generates a setting signal on the basis of the first information and the second information using a generation unit (123).

Description

信息处理系统 Information processing system

技术领域 FIELD

[0001] 本发明涉及监视访问冲突的信息处理系统。 [0001] The present invention relates to monitoring access violation information processing system.

背景技术 Background technique

[0002] 近年来,在一个系统内采用具有多个核的多核处理器系统的方式的信息处理系统日益增加。 Information Processing System [0002] In recent years, multi-core processor system having a plurality of cores in one embodiment of the system is increasing. 在多核处理器系统的总线中,会传输从多个核产生的各种类型的数据。 In the multi-core processor system bus, various types of data will be transmitted from a plurality of nucleation. 具体地,总线中会传输从CPU (Central Processing Unit)、DMA (Direct Memory Access)控制器、DSP (Digital Signal Processor)等产生的数据。 In particular, the bus can transfer data from CPU (Central Processing Unit), DMA (Direct Memory Access) controller, DSP (Digital Signal Processor) and the like generated. 从CPU对存储器的访问是在I个周期中传输的数据量即传输单位小的访问,从DMA控制器、DSP等高速传输设备对存储器的访问是传输单位大的访问。 Access from the CPU to the memory is in the I cycle, i.e., a small amount of data transmission units of access, access to the memory from the DMA controller, the DSP device is a high-speed transmission of large transmission access units.

[0003] 这样,对于传输单位各不相同的访问,在设计信息处理系统时,被设计成访问的总量不产生外溢(over flow)。 [0003] Thus, different access to the transmission unit, when designing an information processing system, is not designed to access the total amount of spillover (over flow). 但是,在输入输出对象的1/0是I个端口,或者端口数受到限制的情况下,有时会在该端口产生访问冲突。 However, the input and output objects is I 1/0 ports, or in the case of restricted port number, an access violation may occur in the port.

[0004] 作为消除访问冲突的技术,存在使总线宽度、时钟频率变大,进行更高速化来消除访问冲突的技术(以下,称为“现有技术I”。)。 [0004] As a technique to eliminate an access violation, so that the presence of the bus width, the clock frequency is increased, a higher speed of access to eliminate collision technique (hereinafter, referred to as "prior art I".). 另外,作为其他的技术,存在控制存储器的输入输出的存储器控制器具有临时保留访问要求的排队(queuing)系统,由此来使访问冲突的影响最小化的技术(以下,称为“现有技术2”。)。 Further, as another technology, there are input and output control of the memory controller has a memory queue (Queuing) temporary system access requirements, thereby making the influence of an access violation minimization technique (hereinafter referred to as "prior art 2".).

[0005] 另外,作为其他的消除访问冲突的技术,公开了一种存储器控制器监视高速缓存缺失,当高速缓存缺失次数达到阈值以上时,使DMA的周期挪用模式(cycle steal mode)下的传输单位变小的技术(例如,参照下述专利文献I。)。 Transmission [0005] Further, as another technique to eliminate access violation, cache miss discloses monitoring A memory controller, the cache when the deletion reaches above the threshold frequency, so that the DMA cycle steal mode (cycle steal mode) under technical smaller units (e.g., see Patent Document I.).

[0006] 专利文献1:日本特开2010 - 15275号公报 [0006] Patent Document 1: JP 2010 - 15275 Patent Publication No.

发明内容 SUMMARY

[0007] 但是,在上述的现有技术中,在现有技术I所涉及的技术中,即使未发生访问冲突时也増大处理能力,因此存在着消耗电力増大利用效率降低的问题。 [0007] However, in the above-described prior art, the prior art technology related to I, the access violation does not occur even when the enlargement of processing capacity also, there is a problem that large power consumption efficiency zo reduced. 另外,即使应用了现有技术2所涉及的技术,也会产生对于访问要求的响应的延迟的问题。 Further, even if the application of the prior art technique according to two, can cause problems for the response delay of access requirements.

[0008] 另外,在专利文献I所涉及的技术中,关于来自CPU、DMA控制器、DSP等的访问,存在难以确定哪个访问是来自CPU的访问这样的问题。 [0008] Further, in the technique of Patent Document I involved, with respect to access from the CPU, the DMA controller, the DSP, etc., it is difficult to determine which is accessible from the CPU to access problems. 另外,在专利文献I所涉及的技术中,在执行存在实时限制的处理的过程中的情况下,如果减小DMA控制器的传输单位,则存在DMA控制器的传输效率降低,违反实时限制的可能性变高的问题。 Further, in the technique of Patent Document I involved in the process of performing processing in real-time constraints in the present case, if the transmission unit is reduced DMA controller, there is a reduction in transmission efficiency of the DMA controller, real-time constraints violation the possibility becomes high.

[0009] 本发明的目的在于,为了消除上述现有技术中的问题点,而提供一种抑制消耗电力并且能够消除访问冲突的信息处理系统。 [0009] The object of the present invention is to eliminate the above problems of the prior art, and to provide a method for inhibiting the power consumption of the information processing system can be eliminated and an access violation.

[0010] 为了解决上述课题,达成目的,公开的信息处理系统包含与总线连接的CPU、与总线连接的设备、被CPU或者设备访问的存储器以及设定消耗电力模式的电源模式控制电路,电源模式控制电路基于表示CPU内的高速缓存的高速缓存命中或者高速缓存缺失的第I信息和表示设备的激活状态或者非激活状态的第2信息,来设定消耗电力模式。 [0010] In order to solve the above problems and achieve the object, the disclosed information processing system including a CPU connected to a bus, the devices connected to the bus, the power consumption mode is a CPU or a memory device access control circuit, and setting the power mode, power mode based on the control circuit indicates that the cache in the CPU cache hit or cache miss information I, and the second device information indicating the active state or the inactive state, the power consumption mode is set. [0011] 根据本信息处理系统,实现在存储器访问冲突时设定为超频时钟避免访问冲突,在没有访问时停止时钟供给能够削减消耗电力这样的效果。 [0011] The present information processing system, set the clock to avoid access conflict overclock memory access conflicts, stopping the clock supply can be reduced power consumption of such effects in the absence of access based.

附图说明 BRIEF DESCRIPTION

[0012] 图1是表示实施方式所涉及的信息处理系统100的硬件的框图。 [0012] FIG. 1 is a block diagram of hardware of an information processing system embodiment 100.

[0013] 图2是表示生成部123和设定部118的动作的说明图。 [0013] FIG. 2 is a diagram illustrating the operation of the generating unit 123 and a setting portion 118.

[0014] 图3是表示信息处理系统100处于状态I时的动作的说明图。 [0014] FIG. 3 is a diagram showing the information processing system 100 is an operation explanatory diagram when the state I.

[0015] 图4是表示信息处理系统100处于状态2时的动作的说明图。 [0015] FIG. 4 is an explanatory diagram 100 is in the operation state 2:00 information processing system.

[0016] 图5是表不信息处理系统100处于状态3时的动作的说明图。 [0016] FIG. 5 is an explanatory diagram 100 is in an operation state in Table 3 is not the information processing system.

[0017] 图6是表示信息处理系统100处于状态4时的动作的说明图。 [0017] FIG. 6 is a diagram 100 illustrates the operation of FIG. 4 is a state in the information processing system.

[0018] 图7是表不信息处理系统100处于状态5 — I时的动作的说明图。 [0018] FIG. 7 is a table of the information processing system 100 is not a state 5 - explanatory view of an operation when I.

[0019] 图8是表不信息处理系统100处于状态5 — 2时的动作的说明图。 [0019] FIG. 8 is a table 100 in a state without an information processing system 5 - 2 during the operation described in FIG.

具体实施方式 detailed description

[0020] 以下参照说明书附图,详细地说明公开的信息处理系统的优选实施方式。 [0020] The following description with reference to the drawings, preferred embodiments of an information processing system disclosed in detail.

[0021](信息处理系统100的硬件) [0021] (hardware information processing system 100)

[0022] 图1是表示实施方式所涉及的信息处理系统100的硬件的框图。 [0022] FIG. 1 is a block diagram of hardware of an information processing system embodiment 100. 在图1中,信息处理系统100包含CPUlOl、CPU102、DMA控制器103以及DMA控制器104。 In FIG 1, the information processing system 100 comprises CPUlOl, CPU102, DMA controller 103, and DMA controller 104. 并且,信息处理系统100包含存储器控制器105、共享资源106、电源模式控制电路(以下称为“PMU (PowerManagement Unit”))107以及总线控制器108。 Further, the information processing system 100 includes a memory controller 105, the shared resource 106, power mode control circuit (hereinafter referred to as "PMU (PowerManagement Unit")) 107 and a bus controller 108. 另外,各部通过总线109彼此连接。 Further, each part connected to one another through a bus 109. 另外,作为与用户或其他机器之间的输入输出装置,信息处理系统100也可以与显示器、键盘等连接。 Further, between the input and output device or other machine with a user, the information processing system 100 may be connected to a display, keyboard or the like.

[0023] CPUlOl、CPU102掌管信息处理系统100的整体控制。 [0023] CPUlOl, CPU102 controls the entire control information processing system 100. 这样,信息处理系统100采用包含多个核的多核处理器系统的方式。 Thus, the information processing system 100 by way of a multi-core processor system comprising a plurality of cores. 另外,信息处理系统100也可以是具有一个核的单核处理器系统。 Further, the information processing system 100 may be a single-processor system having a core. 另外,多核处理器系统是指包含搭载有多个核的处理器的计算机系统。 Further, the system refers to a multi-core processor computer system comprising a plurality of cores mounted processors. 如果搭载有多个核,则可以是搭载有多个核而成的单一处理器,也可以是由单核的处理器并列而成的处理器组。 If multiple cores are mounted, it may be mounted with a single processor core formed by a plurality of, and may be tied by a single core processor from processor group.

[0024] 另外,CPUlOl具有作为CPU的寄存器组之一的、保存CPUlOl的状态即状态信息的状态寄存器110、高速缓存111。 [0024] Further, as CPUlOl has one register set of the CPU, i.e., the state of state saving CPUlOl state information register 110, a cache 111. 同样地,CPU102具有状态寄存器112和高速缓存113。 Likewise, CPU102 having a status register 112 and cache 113. 作为状态寄存器110、状态寄存器112所保存的状态信息,例如是运算结果的正负、溢出的产生等伴随着程序执行的状态。 As the state register 110, status register 112 saved state information, for example, a negative result of the operation, and the like accompanied by generation of an overflow state of the program execution.

[0025] 另外,状态寄存器110、状态寄存器112将CPU101、CPU102是否访问了共享资源106的信息作为状态信息之一加以保存。 [0025] Further, the status register 110, status register 112 to CPU 101, the CPU 102 whether to access the shared resource information 106 to be stored as one of the state information. 将CPU101、CPU102所进行的共享资源106的数据传输设为PIO (Programmed I/O)传输。 The data transmission of the shared resource CPU101, CPU102 performed 106 to PIO (Programmed I / O) transmission. 其中,作为产生PIO传输的情况,是CPUlOl、CPU102检索高速缓存111、高速缓存113内的数据,在检索后所要求的数据不存在的情况下,访问了共享资源106的情况。 Wherein, as the generated PIO transfer is CPUlOl, CPU102 retrieved cache 111, the data within the cache 113, in the case after retrieving the requested data does not exist, a case where access to the shared resource 106. 在以下说明中,将在高速缓存111、高速缓存113中数据存在的情况称为“高速缓存命中”,将数据不存在的情况称为“高速缓存缺失”。 In the following description, the cache 111, the presence of the data cache 113 is called a "cache hit", the case where the data is not present is called a "cache miss."

[0026] 其中,作为产生PIO传输的其他情况,也存在CPUlOl、CPU102不检索高速缓存111、高速缓存113内的数据,而访问共享资源106的情况。 [0026] wherein, as otherwise generated PIO transmission, there CPUlOl, CPU102 not retrieve a cache 111, the data within the cache 113, and 106 access the shared resource. 该动作也包含在前述内容中定义的高速缓存缺失中。 This operation is also included in the definition of cache misses in the foregoing disclosure. 因此,通过参照状态寄存器110、状态寄存器112,就能够判断CPU101、CPU102进行了高速缓存命中或者高速缓存缺失的情况。 Thus, by referring to the status register 110, status register 112, CPU 101 can judge, where the CPU 102 has been a cache hit or cache misses.

[0027] DMA控制器103、DMA控制器104是不借助CPUlOl、CPU102对共享资源106进行数据传输的装置。 [0027] DMA controller 103, DMA controller 104 is not aid CPUlOl, CPU102 of the shared resource 106 is the data transmission device. 另外,DMA控制器103具有通过对值进行设定能够控制DMA控制器103的控制寄存器114。 Further, by having a DMA controller 103 capable of controlling the set value register 114 controls the DMA controller 103. 同样地,DMA控制器104具有控制寄存器115。 Similarly, DMA controller 104 includes a control register 115. 其中,控制寄存器114、控制寄存器115中还包含保存DMA控制器103、DMA控制器104的状态信息的区域(field)。 Wherein the control register 114, control register 115 further comprises a DMA controller 103 to save, the state information area of ​​the DMA controller 104 (field).

[0028] DMA控制器103、DMA控制器104也可以能够改变作为在I个周期中传输的数据量的传输单位。 [0028] DMA controller 103, DMA controller 104 may also be changed as the amount of data in the I transmission period of a transmission unit. 例如,对于DMA控制器103、DMA控制器104而言,传输单位可以与总线109的总线宽度一致,传输单位也可以小于总线109的总线宽度。 For example, 103, DMA controller 104 DMA controller, the transmission unit may coincide with the bus width of the bus 109, a transmission unit may be smaller than the bus width of the bus 109. 在传输单位与总线109的总线宽度一致的情况下,DMA控制器103、DMA控制器104能够以最高效率进行数据传输。 In the same bus width of bus 109 and a transmission unit case, DMA controller 103, DMA controller 104 can perform data transmission with maximum efficiency. 以下,将传输单位与总线109的总线宽度一致的情况称为“高密度传输”,将传输单位小于总线109的总线宽度的情况称为“低密度传输”。 Hereinafter, the case where the bus width of the bus and the same transmission unit 109 is referred to as "high density transfer", the transfer unit is less than the bus width of bus 109 is a condition called "low density transfer."

[0029] 存储器控制器105是协调CPUlOl〜DMA控制器104访问共享资源106的访问权的冲突的装置。 [0029] The memory controller 105 is a controller 104 to coordinate CPUlOl~DMA conflicting access means access to the shared resource 106. 另外,存储器控制器105具有保存存储器控制器105的状态的状态寄存器116。 Further state, the memory controller 105 with memory controller 105 to save the state of the register 116. 其中,假定本实施方式所涉及的信息处理系统100是便携式终端之类的资源受限的组装机器,并且假定共享资源106 —个就已经足够。 Wherein the information processing system according to the present embodiment is a portable terminal 100 is assumed such resource constrained assembling machine, and assuming the shared resource 106-- one is enough. 但是,在假如存在多个共享资源106的情况下,也可以存在多个存储器控制器105。 However, in a case where a plurality of shared resources if the presence of 106, may also be present a plurality of memory controller 105.

[0030] 共享资源106是CPUlOl〜DMA控制器104所访问的存储器。 [0030] The shared resource 106 is a memory accessed by controller 104 CPUlOl~DMA. 存储器是例如ROM(Read Only Memory)> RAM (Random Access Memory)、闪存ROM 等。 The memory is, for example, ROM (Read Only Memory)> RAM (Random Access Memory), a flash ROM.

[0031] PMU107管理信息处理系统100的消耗电力。 [0031] PMU107 management information processing system 100 of the power consumption. 例如,PMU107使针对总线109的时钟停止,由此来变成降低信息处理系统100的消耗电力的低消耗电力模式。 For example, PMU107 so stops the clock bus 109, thereby reducing the consumption power mode into an information processing system 100 is power consumption. 或者,PMU107将对总线109的时钟设定成规定值,来变成通常模式。 Alternatively, PMU107 bus 109 will be set to a predetermined value of the clock, to become a normal mode. 或者,PMU107将对总线109的时钟设定成比规定值大的时钟,由此来变成信息处理系统100的消耗电力变大的超频时钟模式。 Alternatively, PMU107 clock bus 109 will set to be larger than the predetermined value of the clock, the clock overclock thereby becomes the power consumption mode of the information processing system 100 becomes larger. 另夕卜,PMU107具有通过对值进行设定就能够控制PMU107的控制寄存器117、基于控制寄存器117来设定消耗电力模式的设定部118。 Another Bu Xi, PMU107 having a value set by the control register can be controlled PMU107 117 based on the control register 117 to set the mode setting unit 118 of the power consumption.

[0032] 总线控制器108监视CPU101〜存储器控制器105的状态信息,变更DMA控制器103、DMA控制器104,PMU107的设定。 [0032] The bus controller 108 monitors state information CPU101~ the memory controller 105 changes the DMA controller 103, DMA controller 104, the set PMU107. 另外,总线控制器108包含高速缓存缺失检测部119、高速1/0检测部120、访问冲突检测部121、设定寄存器122以及生成部123。 Further, the bus controller 108 comprises a cache miss detecting unit 119, the high-speed detection unit 1/0 120, an access violation detection unit 121, setting register 122 and a generation unit 123.

[0033] 高速缓存缺失检测部119具有检测作为在状态寄存器110、状态寄存器112中保存的信息之一的、表示高速缓存命中或者高速缓存缺失的第I信息的功能。 [0033] cache miss detecting section 119 has detected as a status register 110, one of the information stored in status register 112, the function information of I cache hit or cache miss FIG. 其中,高速缓存缺失检测部119在状态寄存器110、状态寄存器112中的至少任一方表示高速缓存缺失的情况下,将第I信息检测为高速缓存缺失。 The case wherein the cache miss detecting unit 119 in the status register 110, status register 112 indicates at least either one cache miss, the detection of the first information I cache miss.

[0034] 高速1/0检测部120具有检测表示与总线109连接的设备的激活状态或者非激活状态的第2信息的功能。 [0034] High speed 1/0 detecting section 120 has a function of detecting second information indicates the active state of devices connected to the bus 109 or the inactive state. 在此,设备是指DSP (Digital Signal Processor)、DMA控制器之类的访问共享资源106的设备。 Here, the device refers to a DSP (Digital Signal Processor), or the like to access the DMA controller 106 of the resource-sharing device. 在本实施方式所涉及的高速1/0检测部120中,将作为在控制寄存器114、控制寄存器115中保存的信息之一的、DMA控制器103、DMA控制器104是否正在使用之类的信息检测为第2信息。 In the high-speed detecting section 1/0 according to the present embodiment 120, the control register 114 as the information, one of the control information stored in the register 115, the DMA controller 103, DMA controller 104 is being used in such second information is detected.

[0035] 具体地,高速1/0检测部120将DMA控制器103、DMA控制器104正在使用的状态作为激活状态,将未使用的状态作为非激活状态,来检测第2信息。 [0035] Specifically, the detection unit 120 1/0 high speed state 103, the state of the DMA controller 104 DMA controller being used as an active state, unused state as inactive, the second information is detected. 其中,在DMA控制器103、DMA控制器104中的至少任一方正在使用的情况下,高速I/O检测部120检测第2信息作为激活状态。 Wherein, in the case of DMA controller 104 is being used at least either one of the DMA controller 103, a high-speed I / O unit 120 detects detection information as the second active state.

[0036] 访问冲突检测部121具有检测作为在状态寄存器116中保存的信息之一的、表示对共享资源106的访问冲突状态或者非冲突状态的第3信息的功能。 [0036] Access with Collision Detection section 121 has detected as one of the information stored in the status register 116, the third information indicates the function of a state or a non-conflict access a shared resource conflict state 106.

[0037] 设定寄存器122是设定总线控制器108的动作的寄存器。 [0037] register 122 is set to the setting operation of the bus controller 108 registers. 例如,设定寄存器122也可以设定是否使高速缓存缺失检测部119〜访问冲突检测部121发挥功能。 For example, the setting register 122 may be set so that if a cache miss detecting unit 119~ Access with Collision Detection unit 121 functions. 另外,设定寄存器122也可以利用在CPU101、CPU102中执行的OS (Operating System),来设定信息处理系统100是否存在实时限制的第4信息。 Further, the setting register 122 may be utilized in the CPU101, OS (Operating System) CPU102 performed to set the fourth information processing system 100 is the presence of real-time constraints. 其中,实时限制表示对在CPU101、CPU102中执行的处理设定了响应时间的状态。 Wherein the representation of real-time constraint processing performed in the CPU 101, the CPU 102 is set in a state where response time. 另外,第4信息可以在信息处理系统100起动时设定,也可以在起动后中途改变值。 Further, the fourth information may be set in the information processing system 100 is started, the value can be changed during the post-startup.

[0038] 生成部123基于高速缓存缺失检测部119〜设定寄存器122的值,生成针对DMA控制器103、DMA控制器104以及PMU107的设定信号。 [0038] The generating unit 123 119~ 122 based on the set value of the register cache miss detecting unit 103 generates, DMA controller 104 and a setting signal for the DMA controller PMU107. 设定信号中包含针对PMU107的PMU设定信号、针对DMA控制器103、DMA控制器104的DMA设定信号。 PMU contains setting signal for setting the signals PMU107, a DMA controller 103, DMA controller 104 DMA setting signal.

[0039] 具体地,作为生成的信息,生成部123对PMU107生成将高速缓存缺失检测部119〜设定寄存器122的各信息设为I位的至少4位PMU设定信号。 [0039] Specifically, as the information generated by the generating unit 123 generates a cache miss PMU107 detecting unit 119~ setting information register 122 is set for each of at least four bits of the I setting signal PMU. 另外,生成部123对DMA控制器103、DMA控制器104,生成由高速缓存缺失检测部119〜设定寄存器122的值的组合而决定的I位DMA设定信号。 Further, generating unit 123 DMA controller 103, DMA controller 104, detection of loss generating unit is set by the cache 119~ combination of values ​​of the register 122 and determines the I-bit DMA setting signal. 关于更为详细的PMU设定信号和DMA设定信号的内容,结合图2后述。 On the content of the PMU more detail setting signal and DMA setting signal, after 2 described later in conjunction with FIG.

[0040] 图2是表示生成部123和设定部118的动作的说明图。 [0040] FIG. 2 is a diagram illustrating the operation of the generating unit 123 and a setting portion 118. 设定部118根据基于由生成部123生成的高速缓存缺失检测部119〜设定寄存器122这4个值的PMU设定信号,来设定PMU107的动作。 The setting unit 118 based on the absence of the generation unit 123 generates the cache unit detecting the setting signal 119~ setting register 122 PMU four values, the setting operation PMU107. 另外,在图2中,一并说明与由生成部123的生成DMA设定信号对应的DMA控制器103、104的动作。 Further, in FIG. 2, in conjunction with the operation of the DMA controller DMA set by the generating unit 123 generates a signal corresponding to 103, 104.

[0041] 另外,图2中表示的表201、表202表示与PMU设定信号对应的生成部123和设定部118的动作。 [0041] Further, table 201 in FIG. 2 shows, the table 202 represents an operation setting signal corresponding to the PMU generating unit 123 and the set portion 118. 具体地,表201图示了基于第I信息、第2信息的组合的生成部123和设定部118的动作,表202进一步地图示了基于第3信息、第4信息的组合的生成部123和设定部118的动作。 Specifically, based on the operation table 201 illustrates generation unit 123 and the setting information portion I of the composition, the second information 118, table 202 illustrates further based on a combination of the third information, fourth information generating unit 123 and a setting operation unit 118.

[0042] 生成部123生成作为LSB (Least Significant Bit)的第0位表示第2信息、第I位表示第3信息、第2位表示第I信息,第3位表示第4信息的PMU设定信号。 [0042] The generating unit 123 generates second information as the LSB (Least Significant Bit) of the bit 0, bit I represents the third information, the second information indicates the first I, bit 3 indicates a fourth set of information PMU signal. 以下,如果表示第2信息的第0位是“0”则表示非激活状态,如果是“I”则表示激活状态。 Hereinafter, if bit 0 represents the second information is "0" indicates an inactive state, if it is "I" indicates an active state. 同样地,如果表示第3信息的第I位是“0”则表示非冲突状态,如果是“I”则表示冲突状态。 Likewise, if the representation of the third I-bit information is "0" indicates a non-conflict state, if the "I" indicates a state of conflict. 另外,如果表不第I彳目息的第2位是“0”则表不闻速缓存命中,如果是“ I ”则表不闻速缓存缺失。 Further, if the Table I, two left foot not mesh information is "0", the table does not smell cache hit, if the "I" is missing cache table does not smell. 另外,如果表示第4信息的第3位是“0”则表示没有实时限制,如果是“I”则表示具有实时限制。 Further, if the representation of the four third information is "0" indicates that there is no real-time constraints, if it is "I" indicates that have real-time constraints.

[0043] 首先说明表201的第I行第I项。 [0043] First, Table I, line 201 to item I. 生成部123可以在第I信息表示高速缓存命中并且第2信息表示非激活状态时,生成使PMU107设定成低消耗电力模式的PMU设定信号。 When the generation unit 123 may represent the first cache hit information I and the second information indicates an inactive state, generates a setting signal PMU PMU107 set to a low power consumption mode. 其中,将第I彳目息是闻速缓存命中并且第2彳目息是非激活状态的彳目息处理系统100的状态称为“状态I”。 Wherein the first message I left foot mesh smell cache hit rate and a second inactive state of the left foot mesh left foot mesh information processing system 100 is referred to as the state of "state I". 另外,生成部123在信息处理系统100处于状态I的情况下,不生成DMA设 Further, generating unit 123 in the information processing system 100 is in the state I, the DMA set is not generated

定信号。 Given signal.

[0044] 具体地,在信息处理系统100处于状态I的情况下,生成部123生成第0位是“O”、第I位是“ O ”、第2位是“ O ”、第3位是“ O ”的“ OOOO ”作为PMU设定信号。 [0044] Specifically, in the information processing system 100 is in state I the case, the generation unit 123 generates the 0th bit is "O", bit I is "O", the second bit is a "O", No. 3 "O" is "OOOO" as the setting signal PMU. 生成的PMU设定 PMU generated set

信号被设定给控制寄存器117。 Signal is set to the control register 117.

[0045] 设定部118也可以在第I信息表示高速缓存命中并且第2信息表示非激活状态时,设定低消耗电力模式。 [0045] The setting unit 118 may represent the first cache hit information I and the second information indicates an inactive state, to set a low power consumption mode. 例如,假定CPU101、CPU102均是高速缓存命中,DMA控制器103、DMA控制器104均未使用的状态I的情况。 For example, suppose CPU 101, the CPU 102 are a cache hit, the state of the DMA controller 103, DMA controller 104 is not used in the case where I. 此时,设定部118从控制寄存器117读取“0000”,设定低消耗电力模式。 In this case, the setting unit reads 118117 "0000" from the control register set the low power consumption mode. 在成为低消耗电力模式的情况下,PMU107停止针对总线109的时钟。 In the case of a low power consumption mode becomes, PMU107 stop the clock for the bus 109. 此时,持续共享资源106中与DRAM相关的更新时钟的供给。 In this case, continuous supply of the shared resource 106 to update the clock associated with DRAM. 其中,与状态I相关的信息处理系统100的详细动作结合图3后述。 Wherein said state I 3 associated with the operation of the information processing system 100 in detail in connection with FIG.

[0046] 下面,说明表201的第2行第I项。 [0046] Next, the second row of table 201 item I. 另外,生成部123也可以在第I信息表示高速缓存命中并且第2信息表示激活状态时,生成使PMU107设定成通常模式的PMU设定信号。 Further, the generation unit 123 may represent a cache hit and the second information indicates the active state, generates a setting signal PMU PMU107 set to the normal mode in the first information I. 其中,将第I ί目息是闻速缓存命中并且第2彳目息是激活状态的彳目息处理系统100的状态称为“状态2”。 Wherein the first information I ί mesh smell cache hits and the second state of the left foot is left foot mesh mesh information of the information processing system 100 in the active state referred to as "state 2." 另外,生成部123在信息处理系统100处于状态2的情况下,生成表示高密度传输的“I”作为DMA设定信号。 Further, generating unit 123 in the information processing system 100 in the case of state 2, it generates a high density transfer "I" is set as the DMA signal.

[0047] 具体地,在信息处理系统100处于状态2的情况下,生成部123生成第O位是“ I ”、第I位是“O”、第2位是“O”、第3位是“O”的“0001”作为PMU设定信号。 [0047] Specifically, in the case where the information processing system 100 is in state 2, the generation of O bit generation unit 123 is "I", bit I is "O", the second bit is a "O", No. 3 "O" of "0001" as a setting signal PMU.

[0048] 另外,设定部118也可以在第I信息表示高速缓存命中并且第2信息表示激活状态时,设定通常模式。 When [0048] Further, the setting unit 118 may represent the first cache hit information I and the second information indicates the active state, to set the normal mode. 例如,假定CPU101、CPU102均高速缓存命中而DMA控制器103、DMA控制器104任意一方正在使用的状态2的情况。 For example, suppose CPU 101, the CPU 102 are a cache hit and the state of the DMA controller 103, DMA controller 104 is being used in either of the case 2. 此时,设定部118自控制寄存器117处读取“0001”,设定通常模式。 In this case, the setting unit 118 is read from the control register 117, "0001", the normal mode is set. 其中,与状态2相关的信息处理系统100的详细动作结合图4后述。 Wherein the detailed operation of the information related to the status 2 processing system 100 described below in conjunction with FIG. 4.

[0049] 下面,说明表201的第I行第2项。 [0049] Next, item 2 in Table I, line 201. 生成部123也可以在第I信息表示高速缓存缺失并且第2信息表示非激活状态时,生成使PMU107设定成通常模式的PMU设定信号。 Generating unit 123 may be represented in the cache miss information I, and the second information indicates an inactive state, generates a setting signal PMU PMU107 set to the normal mode. 其中,将第I信息是高速缓存缺失并且第2信息是非激活状态的信息处理系统100的状态称为“状态3”。 Wherein the first cache miss information I and the information processing system of the second state information 100 is non-active state is called "state 3." 另外,生成部123在信息处理系统100处于状态3的情况下,不生成DMA设定信号。 Further, generating unit 123 in the information processing system 100 in the case of state 3, the DMA setting signal is not generated. 具体地,在信息处理系统100处于状态3的情况下,生成部123生成第O位是“O”、第I位是“O”、第2位是“I”、第3位是“O”的“0100”作为PMU设定信号。 Specifically, in the information processing system 100 in the case of state 3, the generation unit 123 generates a first O bit is a "O", bit I is "O", the second bit is a "I", bit 3 is "O" the "0100" as a setting signal PMU.

[0050] 另外,设定部118也可以在第I信息表示高速缓存缺失并且第2信息表示非激活状态时,设定通常模式。 [0050] Further, the setting unit 118 may represent a cache miss and the second information indicates an inactive state, the normal mode is set in the first information I. 例如,假定CPU101、CPU102中的任一方高速缓存缺失而DMA控制器103、DMA控制器104均未使用的状态3的情况。 For example, suppose CPU 101, CPU102 in either cache miss and the DMA controller 103, DMA controller 104 the status of the case 3 is not used. 此时,设定部118自控制寄存器117处读取“0100”,设定通常模式。 In this case, the setting unit 118 is read from the control register 117, "0100", the normal mode is set.

[0051] 另外,设定部118在信息处理系统100是存在存储器访问延迟(latency)的电路的情况下,变更CPU /存储器的时钟比率。 [0051] Further, the setting unit 118 in the information processing system 100 is the presence of a memory access delay circuit (Latency), alterations clock ratios CPU / memory. 其中,具有存储器访问延迟的电路是指从存储器访问的指令发行到存储器访问花费2个周期以上的电路。 Wherein the memory access circuitry having a delay from the instruction issue means a memory access to two or more memory access cycles spent circuits. 其中,关于状态3所涉及的信息处理系统100的详细动作,结合图5后述。 Wherein the detailed operation of the information processing system 100 according to the state of 3, described later in conjunction with Figure 5.

[0052] 下面对表201的第2行第2项进行说明。 [0052] Next, the second entry in Table 2, line 201 will be described. 在高速缓存缺失检测部119和高速I/O检测部120选中第2行第2项的情况下,生成部123、设定部118遵从表202的条件。 In the case of the two cache miss detecting unit 119 and high-speed I / O unit 120 detects the selected row 2, 123, 118 to comply with the condition setting portion 202 of the table generation unit. 首先说明表202的第I行。 First, a row of Table I 202. 生成部123也可以在第I信息表示高速缓存缺失并且第2信息表示激活状态,并且第3信息表示访问非冲突状态时,生成使PMU107设定为通常模式的PMU设定信号。 Generating unit 123 may be represented in the cache miss information I, and the second information indicates an active state, and the third non-conflicting access information indicates the state, generates a PMU107 the PMU to the normal mode setting signal. 其中,将第I信息是高速缓存缺失、并且第2信息是激活状态并且第3信息是访问非冲突状态的信息处理系统100的状态称为“状态4”。 Wherein the first information is a cache miss I, and the second information is active and the third non-conflicting state information to access the information processing system 100 in a state referred to as "State 4." 另外,生成部123在信息处理系统100处于状态4的情况下,生成表示高密度传输的“I”作为DMA设定信号。 Further, generating unit 123 in the information processing system 100 is a case where the state 4, generates a high density transfer "I" is set as the DMA signal.

[0053] 具体地,在信息处理系统100处于状态4的情况,生成部123生成第0位是“ I ”、第I位是“0”、第2位是“ I”、第3位是“0”的“0101”作为PMU设定信号。 [0053] Specifically, in the information processing system 100 is in the case of state 4, the generating unit 123 generates the 0th bit is "I", bit I is "0", bit 2 is "I", bit 3 is " 0 "and" 0101 "as a setting signal PMU.

[0054] 另外,设定部118也可以在第I信息表示高速缓存缺失、并且第2信息表示激活状态,并且第3信息表示访问非冲突状态时,设定通常模式。 [0054] Further, the setting unit 118 may be represented at the I cache miss information and second information indicates an active state, and the third access information indicates non-conflicting state, the normal mode is set. 例如,假定CPU101、CPU102中的至少任一方发生高速缓存缺失而DMA控制器103、DMA控制器104中的至少任一方正在使用,存储器控制器105是非冲突状态的情况。 For example, suppose CPU 101, the CPU 102, at least either one of a cache miss occurs and the DMA controller 103, DMA controller 104 is being used at least either one, non-conflicted state 105 where a memory controller. 此时,设定部118自控制寄存器117处读取“0101”,设定通常模式。 In this case, the setting unit 118 is read from the control register 117, "0101", the normal mode is set. 其中,与状态4所涉及的信息处理系统100的详细动作结合图6后述。 The information processing system in which, according to state 4 in conjunction with a detailed operation 100 of Figure 6 described later.

[0055] 下面,说明表202的第2行第I项。 [0055] Next, the second row in Table 2202 to item I. 生成部123也可以在第3信息表示访问冲突状态并且第4信息表示有实时限制时,生成使PMU107设定成超频时钟模式的PMU设定信号。 Generating unit 123 may also be expressed in state access violation third information and fourth information indicates when real-time constraints, generates a clock PMU107 set to overclock PMU mode setting signal. 其中,将第I信息是高速缓存缺失、并且第2信息是激活状态、并且第3信息是访问非冲突状态,并且第4信息是有实时限制的状态的信息处理系统100的状态称为“状态5 -1”。 Wherein the first information is a cache miss I, and the second information is an active state, and the third non-conflicting state access information, and fourth information is real-time constraints state in the information processing system 100 in a state referred to as "state 5-1. " 另外,生成部123在信息处理系统100处于状态5 -1的情况下生成表示高密度传输的“I”作为DMA设定信号。 Further, generating unit 123 in a case where the information processing system 100 is in state 5-1 generates a high density transfer "I" is set as the DMA signal.

[0056] 具体地,在信息处理系统100处于状态5 -1的情况下,生成部123生成第0位是“ I”、第I位是“ I”、第2位是“ I”、第3位是“ I”的“ 1111”作为PMU设定信号。 [0056] Specifically, in the case where the information processing system 100 is in state 5-1, the generating unit 123 generates the 0th bit is "I", the first bit I is "I", the second bit is a "I", 3 bit is a "I" to "1111" as a setting signal PMU.

[0057] 另外,设定部118也可以在第I信息表示高速缓存缺失,并且第2信息表示激活状态、并且第3信息表示访问冲突状态,并且第4信息表示有实时限制时,设定超频时钟模式。 [0057] Further, the setting unit 118 may be represented at the I cache miss information and second information indicates an active state, and the third state information indicates the access violation, and the fourth information indicates when real-time constraints, set overclocking clock mode. 例如,CPU101、CPU102中的至少任一方发生高速缓存缺失而DMA控制器103、DMA控制器104中的至少任一方正在使用。 For example, CPU101, CPU102 at least either one of a cache miss occurs and the DMA controller 103, DMA controller 104 is being used at least either one. 并且,假定共享资源106是冲突状态,存在实时限制的情况。 And, assuming that the shared resource 106 is a state of conflict, the presence of real-time constraints. 此时,设定部118自控制寄存器117处读取“1111”,设定超频时钟模式。 In this case, the setting unit 118 is read from the control register 117, "1111", the clock mode is set overclocking. 其中,与状态5 — I所涉及的信息处理系统100的详细动作结合图7后述。 Wherein the state 5 - detailed operation of the information processing system 100 according to I of Figure 7 described later.

[0058] 最后,说明表202的第2行第2项。 [0058] Finally, described in Table 2, line 2 Item 202. 生成部123也可以在第3信息表示访问冲突状态并且第4信息表示没有实时限制时,生成使PMU107设定为通常模式的PMU设定信号。 Generating unit 123 may also be expressed in state access violation third information and fourth information indicates the absence of real-time constraints, it generates a setting signal to set PMU107 PMU normal mode. 其中,将第I信息是高速缓存缺失、并且第2信息是激活状态、并且第3信息是访问冲突状态,并且第4信息是没有实时限制的状态的信息处理系统100的状态称为“状态5 — 2”。 Wherein the first information is a cache miss I, and the second information is an active state, and the third state information is an access violation, and the fourth information is no real-time constraints state of the information processing system 100 is referred to as the state of "state 5 - 2". 另夕卜,生成部123在信息处理系统100处于状态5 — 2的情况下,生成表示低密度传输的“0”作为DMA设定信号。 Another Bu Xi generating unit 123 in the information processing system 100 is in state 5 - case 2, generates a "0" density setting signal transmitted as the DMA.

[0059] 具体地,在信息处理系统100处于状态5 - 2的情况下,生成部123生成第0位是“ I”、第I位是“ I ”、第2位是“ I”、第3位是“ 0 ”的“ 0111”作为PMU设定信号。 [0059] Specifically, in the information processing system 100 is in state 5 - case 2, the generating unit 123 generates the 0th bit is "I", bit I is "I", the second bit is a "I", 3 bit is "0" and "0111" as a setting signal PMU.

[0060] 另外,设定部118也可以在第I信息表示高速缓存缺失、并且第2信息表示激活状态、并且第3信息表示访问冲突状态,并且第4信息表示没有实时限制时,设定通常模式。 [0060] Further, the setting unit 118 may be represented at the I cache miss information and second information indicates an active state, and the third state information indicates the access violation, and the fourth information indicates no real-time constraints, usually set mode. 例如,CPUlOl、CPU102中的至少任一方发生高速缓存缺失而DMA控制器103、DMA控制器104中的至少任一方正在使用。 For example, CPUlOl, CPU102 at least either one of a cache miss occurs and the DMA controller 103, DMA controller 104 is being used at least either one. 并且,假定共享资源106是冲突状态,没有实时限制的情况。 And, assuming that the shared resource 106 is a state of conflict situations, there is no real-time constraints. 此时,设定部118自控制寄存器117处读取“0111”,设定通常模式。 In this case, the setting unit 118 is read from the control register 117, "0111", the normal mode is set. 其中,与状态5 — 2所涉及的信息处理系统100的详细动作结合图8后述。 Wherein the state 5 - 2 detailed operation of the information processing system 100 according to the FIG. 8 described later.

[0061] 针对结合图2进行了说明的状态I〜状态5 — 2,结合图3〜图8叙述具体例。 [0061] in FIG. 2 for binding to a state in the state illustrated I~ 5--2, FIG. 8 described in conjunction with FIG. 3 ~ specific examples. 其中,图3〜图8中的信息处理系统100的性能如下所述。 Wherein the performance of FIG 3 ~ FIG. 8 the information processing system 100 is as follows. 总线109在总线宽度为64[位]、时钟频率为作为规定值的500 [MHz]下进行动作。 Bus 109 in the bus width is 64 [bit], the clock frequency of a predetermined value of 500 [MHz] to operate under. 在CPU101、CPU102的总线宽度是32 [位]、时钟频率是l[GHz]下进行动作。 In the CPU 101, CPU102 bus width is 32 [bit], operates at a clock frequency l [GHz]. 关于作为共享资源106之一的存储器,假设可以进行如下2种设定。 As a shared resource on one of the memory 106, the following assumptions can be two kinds of settings. 第I个设定是以总线宽度为64 [位],时钟频率为I [GHz]进行动作的CPU和存储器的时钟比为1:1的设定。 I-th bus width is set to 64 [bit], the clock frequency is I [GHz] clock than the CPU and a memory operation is 1: 1 is set. 第2个设定是以总线宽度为64 [位]、时钟频率为500 [MHz]下进行动作的CPU和存储器的时钟比是2:1的设定。 The second set bus width is 64 [bit], the clock frequency is 500 [MHz] clock than the CPU and a memory is operated at 2: 1 is set.

[0062] 另外,DMA控制器103、DMA控制器104以传输单位是字传输,或者双字传输这样的2种传输方法中的任一种进行动作。 [0062] Further, any one of 103, DMA controller 104 is a digital transmission unit to transmit the DMA controller, or two or doubleword transfer such a transmission method operates. 尤其是在没有设定变更的情况下,DMA控制器103、DMA控制器104进行双字传输。 Especially in the absence of the setting change, DMA controller 103, DMA controller 104 performs double word transfer. 另外,本实施方式中,假定I字是32位。 In the present embodiment, assumed is a 32-bit I word. 因此,在字传输中,I个时钟传输32 [位]的数据量,在双字传输中I时钟传输64 [位]的数据量。 Thus the amount of data size in the word transmission, the transmission I clock 32 [bit], and the double word transmission clock propagation I 64 [bit] of. 另外,作为信息处理系统100所执行的处理之一的通信收信,作为成为实时限制的QoS (Quality ofService)时间,要求10 [毫秒]以内的响应。 Further, as one of the communication process performed by the information processing system 100 in receiving, as a real-time constraints become QoS (Quality ofService) the time required to respond within 10 [msec].

[0063] 其中,为了简化说明,在图3〜图8中假定高速缓存缺失产生的CPU是CPU101。 [0063] wherein, to simplify the description, the CPU of the deletion generated in FIG 3 ~ FIG. 8 is assumed that the cache CPU101. 同样地,假定正在使用的DMA控制器是DMA控制器103。 Similarly, the DMA controller is assumed that the DMA controller 103 is used.

[0064] 图3是表不信息处理系统100处于状态I时的动作的说明图。 [0064] FIG. 3 is a table 100 in an operation explanatory diagram when the state I is not an information processing system. 图3所不的信息处理系统100处于CPUlOl、CPU102均是高速缓存命中而DMA控制器103、DMA控制器104均是未使用的状态I的情况。 FIG 3 is not in the information processing system 100 CPUlOl, CPU102 are a cache hit and the state of the DMA controller 103, DMA controller 104 are not used in the case where I. 其中,作为信息处理系统100处于状态I的具体例是,在用户未操作信息处理系统100的状态下,内核进程等周期性地进行动作,并且总是在高速缓存命中的状态下进行动作的情况。 Specific examples wherein, as the information processing system 100 is in state I is, in a state where the user does not operate the information processing system 100, and other kernel process is operated cyclically, and always operates in the state of the cache hit case .

[0065] 此时,总线控制器108生成“0000”= OH这样的PMU设定信号,发送给PMU107。 [0065] At this time, the bus controller 108 generates a "0000" = OH PMU this setting signal is transmitted to PMU107. 其中,即使在设定寄存器122设定为存在实时限制,如果第O位〜第2位都不是“1”,则作为第3位的第4信息也不被用作判断基准。 Wherein, even in a setting register 122 is set to present real-time constraints, if the first bit to O 2 is not "1", as the three of the fourth information it is not used as the determination reference. 因此,总线控制器108设定表示没有实时限制的“O”。 Thus, the bus controller 108 that there is no real-time constraints set "O". 或者,总线控制器108生成“1000”这样的PMU设定信号,由于第O位〜第2位都不是“1”,因此设定部118也可以将第3位作为无效来进行处理。 Alternatively, the bus controller 108 generates a "1000" signal is set such PMU, since the first bit to O 2 is not "1", the setting unit 118 may be a 3 bit valid for processing. 该动作针对状态2〜状态4也同样。 The operation state for state 2 ~ 4 also.

[0066] 被设定了PMU设定信号的PMU107停止共享资源106中与DRAM相关的刷新时钟以外的总线109的时钟的供给,作为低消耗电力模式。 [0066] The PMU is set PMU107 setting signal other than the clock supply stopping shared resource 106 associated with DRAM refresh clock bus 109, a low power consumption mode. 这样,在状态I的信息处理系统100中,总线109未被使用,因此能够停止时钟的供给,能够削减消耗电力。 Thus, in state I the information processing system 100, bus 109 is not used, it is possible to stop supplying the clock, the power consumption can be reduced.

[0067] 图4是表示信息处理系统100处于状态2时的动作的说明图。 [0067] FIG. 4 is an explanatory diagram 100 is in the operation state 2 of the information processing system. 图4所示的信息处理系统100是CPUlOl、CPU102均为高速缓存命中而DMA控制器103正在使用的状态2的情况。 The information processing system 100 is shown in FIG CPUlOl, CPU102 it is a cache hit and DMA controller 103 are in the state of the case 2. 其中,作为信息处理系统100处于状态2的具体例,是进行使用了DMA控制器103的下载处理,用户不操作信息处理系统100,内核进程总是在高速缓存命中的状态下进行动作的情况。 Wherein the information processing system 100 is a specific example of state 2, the download process is performed using the DMA controller 103, the user does not operate the information processing system 100, the kernel process is always in a state of operation of the cache hit.

[0068] 此时,总线控制器108生成“0001”= IH这样的PMU设定信号,发送给PMU107。 [0068] At this time, the bus controller 108 generates a "0001" = IH PMU this setting signal is transmitted to PMU107. 被设定了PMU设定信号的PMU107将针对总线109的时钟的供给设定成500 [MHz],作为通常模式。 PMU is set PMU107 setting signal for setting the clock supplied to the bus 109 to 500 [MHz], as the normal mode. 另外,总线控制器108生成表示高密度传输的“I”这样的DMA设定信号,发送给DMA控制器103、DMA控制器104。 Further, the bus controller 108 generates a high-density transfer "I" such DMA setting signal sent to the DMA controller 103, DMA controller 104. 被设定了DMA设定信号的DMA控制器103、DMA控制器104进行成为高密度传输的双字传输。 DMA set is the DMA controller setting signal 103, DMA controller 104 for transmission of high-density becomes double word transfer.

[0069] 图5表不信息处理系统100处于状态3时的动作的说明图。 [0069] FIG. 5 table is not the information processing system 100 is an explanatory view of an operation state of 3. 图5所不的信息处理系统100是CPUlOl发生高速缓存缺失而DMA控制器103、DMA控制器104均未使用的状态3的情况。 FIG 5 is not the information processing system 100 is a cache miss occurs CPUlOl state and the DMA controller 103, DMA controller 104 is not used in the case 3. 其中,作为信息处理系统100处于状态3的具体例,是正在检索信息处理系统100内的数据的情况。 Wherein the information processing system 100 is a specific example of the state 3, the information processing system is being retrieved in the case where data 100.

[0070] 此时,总线控制器108生成“0100”= 4H这样的PMU设定信号,发送给PMU107。 [0070] At this time, the bus controller 108 generates a "0100" = 4H PMU this setting signal is transmitted to PMU107. 被设定了PMU设定信号的PMU107将针对总线109的时钟的供给设定成500 [MHz],作为通常模式。 PMU is set PMU107 setting signal for setting the clock supplied to the bus 109 to 500 [MHz], as the normal mode. 另外,假定信息处理系统100是具有存储器访问延迟的电路,因此将CPU /存储器的时钟比率设定成2:1。 It is assumed that the information processing system 100 is a circuit having a memory access latency, thus setting the clock rate CPU / memory to 2: 1. 在图5的例子中,将存储器的时钟数降低至500 [MHz]。 In the example of FIG. 5, will reduce the number of clocks to the memory 500 [MHz].

[0071] 其中,作为将时钟比率设定成2:1的理由,在信息处理系统100处于状态3中,不存在从DMA控制器103、DMA控制器104对共享资源106的存储器的访问。 [0071] wherein, as the clock rate set to 2: 1 reason, the information processing system 100 is in state 3, absent from the DMA controller 103, DMA controller 104 accesses the shared memory resource 106. 因此,关于时钟比率的设定,考虑来自CPU101、CPU102的访问即可。 Therefore, regarding the setting of the clock rate, to consider the access from the CPU 101, the CPU 102 a. CPU101、CPU102的总线宽度是32 [位],是存储器总线宽度64 [位]的值的一半,因此即使将存储器的时钟数设定成CPU101、CPU102的一半,也能够应对来自CPU101、CPU102的访问。 CPU 101, CPU102 bus width is 32 [bit] is half the value of the memory bus width of 64 [bit] Therefore, even if the clock count memory is set to CPU 101, CPU102 half, it is possible to deal with access from the CPU 101 CPU102, .

[0072] 这样,状态3中的信息处理系统100对共享资源106的存储器限定来自CPUlOl、CPU102的访问,由此能够降低存储器的时钟数,能够降低消耗电力。 [0072] Thus, the memory state of the information processing system 3100 to the shared resource 106 is defined from CPUlOl, CPU102 access memory thereby possible to reduce the number of clocks, power consumption can be reduced.

[0073] 图6是表不信息处理系统100处于状态4时的动作的说明图。 [0073] FIG. 6 is an explanatory diagram 100 is in an operation state in table 4 are not an information processing system. 图6所不的信息处理系统100是CPUlOl发生高速缓存缺失而DMA控制器103正在使用的状态4的情况。 FIG 6 is not the information processing system 100 is a cache miss occurs CPUlOl DMA controller 103 and the state of being used four. 其中,作为信息处理系统100处于状态4的具体例,是在后台进行下载处理,接受到基于用户的菜单操作的事件接收的情况。 Wherein the information processing system 100 is a specific example of state 4, the download processing is performed in the background, when receiving an event based on the user's menu operations received.

[0074] 此时,在通过菜单操作最初读入层级菜单时,CPUlOl对高速缓存111检索是否存在新的层级菜单的数据。 [0074] In this case, during the initial read operation menu hierarchical menu, CPUlOl retrieval data cache 111 whether the presence of the new hierarchical menu. 由于层级菜单被首次读入,因此在高速缓存111中不存在,CPUlOl访问共享资源106。 Since the hierarchical menu is first read, and therefore does not exist in the cache 111, CPUlOl access to shared resources 106. 在层级菜单被读入后,CPUlOl以在高速缓存111中保存的数据为基础,进行与菜单操作对应的数据处理。 After being read into the hierarchical menu, CPUlOl to stored in the cache data base 111, performs data processing corresponding to the operation menu. 这样,图6中具体例的信息处理系统100尽管在CPUlOl中产生高速缓存缺失,但是由于不产生连续的P10,因此是不产生针对共享资源106的访问冲突的状态。 Thus, a specific example of the information processing system 6100 of FIG Although CPUlOl generated in cache miss, but it is not generated continuous P10, and therefore the state is not generated for the shared resource access conflicts 106.

[0075] 此时,总线控制器108生成“0101”= 5H这样的PMU设定信号,发送给PMU107。 [0075] At this time, the bus controller 108 generates a "0101" = 5H PMU this setting signal is transmitted to PMU107. 被设定了PMU设定信号的PMU107将针对总线109的时钟的供给设定成500 [MHz],作为通常模式。 PMU is set PMU107 setting signal for setting the clock supplied to the bus 109 to 500 [MHz], as the normal mode. 另外,总线控制器108生成表示高密度传输的“I”这样的DMA设定信号,发送给DMA控制器103、DMA控制器104。 Further, the bus controller 108 generates a high-density transfer "I" such DMA setting signal sent to the DMA controller 103, DMA controller 104. 被设定了DMA设定信号的DMA控制器103、DMA控制器104进行成为高密度传输的双字传输。 DMA set is the DMA controller setting signal 103, DMA controller 104 for transmission of high-density becomes double word transfer.

[0076] 图1是表不信息处理系统100处于状态5 — I时的动作的说明图。 [0076] Table 1 is not in the state of the information processing system 100 5 - explanatory view of an operation when I. 图7所不的信息处理系统100是CPUlOl发生高速缓存缺失而DMA控制器103正在使用,正在检测针对共享资源106的访问冲突,存在实时限制的状态5 — I的情况。 FIG 7 is not the information processing system 100 is a cache miss occurs CPUlOl state and the DMA controller 103 is being used, an access violation is detected for the shared resource 106, there is a real-time constraints 5 - I situation. 其中,作为信息处理系统100处于状态5 -1的具体例,是信息处理系统100进行数据下载,并且检索信息处理系统100内的数据,并且发生通信收信这样的情况。 Wherein the information processing system 100 is in a state of specific embodiments 5-1, the information processing system 100 is downloading data, and retrieves data within the information processing system 100, and a case receiving the communication occurs. 由于通信收信存在实时限制,因此要求在一定时间以内进行响应。 A communication receiver due to real-time constraints, and therefore requires a response within a certain time.

[0077] 此时,总线控制器108生成“1111”= fH这样的PMU设定信号,发送给PMU107。 [0077] At this time, the bus controller 108 generates a "1111" = fH such PMU setting signal is transmitted to PMU107. 被设定了PMU设定信号的PMU107将总线的时钟的供给设定成I [GHz],将存储器的时钟频率设定成1.5 [GHz],作为超频时钟模式。 PMU is set PMU107 setting signal supplied bus clock is set to I [GHz], the clock frequency of the memory is set to 1.5 [GHz], as overclock clock mode. 通过提高信息处理系统100的性能,信息处理系统100能够在作为实时限制的QoS时间10 [毫秒]以内响应通信收信。 By improving the performance of the information processing system 100, the information processing system can respond to the communication receiver 100 within the QoS time as the real-time constraints 10 [msec]. 这样,状态5 -1的信息处理系统100即使为访问冲突状态,也能够消除访问冲突并在实时限制的时间内执行处理。 Thus, the state of the information processing system 5-1 100 even in a state of access conflict, it is possible to eliminate the access violation and performs processing in real time limit.

[0078] 另外,总线控制器108生成表示高密度传输的“I”这样的DMA设定信号,发送给DMA控制器103、DMA控制器104。 [0078] Further, the bus controller 108 to transfer high density "I" such DMA setting signal sent to the DMA controller 103, DMA controller 104 generates. 被设定了DMA设定信号的DMA控制器103、DMA控制器104进行成为高密度传输的双字传输。 DMA set is the DMA controller setting signal 103, DMA controller 104 for transmission of high-density becomes double word transfer.

[0079] 图8是表示信息处理系统100处于状态5 — 2时的动作的说明图。 [0079] FIG. 8 is a diagram showing an information processing system 100 is in the state 5 - 2:00 explanatory view of the operation. 图8所示的信息处理系统100是CPUlOl发生高速缓存缺失而DMA控制器103正在使用,正在检测针对共享资源106的访问冲突,不存在实时限制的状态5 — 2的情况。 The information processing system shown in FIG. 8 for state 100 is a shared resource access conflicts 106, real-time constraints do not exist 5 CPUlOl cache miss occurs and the DMA controller 103 is being used, is being detected - the case 2. 其中,作为信息处理系统100为状态5 -1的具体例,是信息处理系统100进行数据下载,并且正在检索信息处理系统100内的数据的情况。 Wherein the information processing system 100 is a specific example of the state 5-1, the information processing system 100 for data downloading, and Retrieving the information processing system in the case where data 100.

[0080] 此时,总线控制器108生成“0111”= 7H这样的PMU设定信号,发送给PMU107。 [0080] At this time, the bus controller 108 generates a "0111" = 7H such PMU setting signal is transmitted to PMU107. 被设定了PMU设定信号的PMU107将对总线109的时钟的供给设定成500 [MHz],作为通常模式。 Is set to the setting signal supplied PMU PMU107 clock bus 109 will be set to 500 [MHz], as the normal mode. 另外,总线控制器108生成表示低密度传输的“O”这样的DMA设定信号,发送给DMA控制器103、DMA控制器104。 Further, the bus controller 108 generates a "O" signal is set low density of such DMA transfer, the DMA controller 103 to the transmission, the DMA controller 104. 被设定了DMA设定信号的DMA控制器103、DMA控制器104进行成为低密度传输的字传输。 DMA set is the DMA controller setting signal 103, DMA controller 104 performs transmission density became word transfers.

[0081] 由此,对于总线109的总线宽度64 [位]中从双字传输切换成字传输而未被使用的32 [位]量的数据,基于CPUlOl的PIO传输易于进入。 [0081] Accordingly, the amount of 32 [bit] of the bus width of the bus 109 64 [bit] from the double word transfer is switched to the unused word transmission data, based on the PIO transfer CPUlOl easy access. 由此,状态5 — 2的信息处理系统100在产生了针对存储器的访问冲突时,能够不增大消耗电力地进行DMA传输,并且还能够进行基于CPUlOl、CPU102的PIO传输。 Thus, state 5 - 2 of the information processing system 100 for generating a memory access conflict can be performed without increasing power consumption DMA transfer, and also capable of PIO transfer CPUlOl, CPU102 based.

[0082] 如以上说明了的那样,根据信息处理系统,根据基于CPU的第I信息即是高速缓存命中还是高速缓存缺失这样的信息、和第2信息即DMA是否正在使用这样的信息,由PMU变更时钟。 [0082] As described above, according to the information processing system according to the basis I of information of the CPU that is a cache hit or a cache miss such information, and second information (DMA) is using such information, the PMU change clock. 由此,信息处理系统在存储器访问冲突时设定成超频时钟来消除冲突,在没有访问时停止时钟供给从而能够削减消耗电力。 Accordingly, the information processing system is set in the memory access violation to overclock clock to eliminate the conflict stopped when no access is possible to supply the clock to reduce power consumption. 另外,本实施方式所涉及的信息处理系统不对DMA控制器、存储器控制器进行改造,因此能够降低对应所花费的成本。 Further, the information processing system according to the present embodiment is not a DMA controller, a memory controller transform, the cost can be reduced corresponding to the spent.

[0083] 另外,作为消除访问冲突的方法,通过模拟来判断冲突是否产生,通过操作软件的调度,能够消除访问冲突。 [0083] Further, as a method of eliminating an access violation by simulation to determine whether a conflict generated by the operation of scheduling software, access violation can be eliminated. 但是,软件调度的操作方法是指通过置换软件的访问顺序来解決访问冲突,还存在即使置换访问顺序也无法消除访问冲突的情况。 However, the method of operation scheduling software is meant to resolve the conflict by accessing the access order replacement software, even if there are replacement access order can not eliminate access conflicts. 在本实施方式的信息处理系统中,即使在即使置换了访问顺序也无法消除访问冲突的情况下,也能够消除访问冲突。 In the information processing system of the present embodiment, even in the case even if the replacement of the access order can not eliminate access violation, it is possible to eliminate an access violation. 另外,本实施方式的信息处理系统也不进行针对软件的改造,因此对应所花费的成本小,另外也可以不进行基于OS版本升级等的应对。 In addition, the information processing system of the present embodiment is not to transform for the software, so it takes little cost corresponding to the other may not be based on OS version upgrades of coping.

[0084] 另外,信息处理系统也可以在第I信息表示高速缓存命中并且第2信息表示未使用的状态I的情况下,由PMU将总线的时钟设定成低消耗电力模式。 [0084] In addition, information handling systems may also be expressed in the first cache hit information I and the second information indicates unused state I of the case, the PMU bus clock is set to a low power consumption mode. 由此,信息处理系统能够削减消耗电力。 Accordingly, the information processing system can reduce power consumption.

[0085] 另外,信息处理系统也可以在第I信息表示高速缓存命中并且第2信息表示正在使用的状态2的情况下,由PMU将总线的时钟设定成通常模式。 [0085] In addition, information handling systems may also be expressed in the first cache hit information I and the second information indicates that the state 2 is being used by the PMU to the bus clock is set to the normal mode. 由此,信息处理系统例如在基于CPU和DMA控制器的访问冲突状态消除,仅DMA控制器访问的情况下,通过使总线的时钟恢复到通常,能够削减消耗电力。 Thus, for example, an information processing system based on a state of conflict in the access to the CPU and the DMA controller to eliminate the case where only the DMA controller accesses and returns to generally by the bus clock, the power consumption can be reduced.

[0086] 另外,信息处理系统也可以在表示状态2的情况下,将DMA控制器设定成高密度传输。 [0086] In addition, information handling systems may also be expressed in the case of state 2, the DMA controller is set to a high-density transmission. 在信息处理系统处于状态2时,不产生PIO传输,因此通过将DMA控制器设定成高密度传输,能够进行高效的数据传输。 In the information processing system is in state 2, PIO transfer does not occur, so by the DMA controller is set to the high-density transmission, data transmission can be executed efficiently. [0087] 另外,信息处理系统也可以在第I信息表示高速缓存缺失并且第2信息表示未使用的状态3的情况下,由PMU将总线的时钟设定成通常模式。 [0087] In addition, information handling systems may also be expressed in the cache miss information I, and the second information indicates the unused state 3, the PMU bus clock set to the normal mode. 由此,信息处理系统例如在基于CPU和DMA控制器的访问冲突状态消除,仅CPU访问的情况下,通过使总线的时钟恢复到通常,能够削减消耗电力。 Thus, for example, an information processing system based on a state of conflict in the access to the CPU and the DMA controller to eliminate, when only accessed by the CPU, to recover generally by the bus clock, the power consumption can be reduced.

[0088] 另外,信息处理系统也可以在第I信息表示高速缓存缺失并且第2信息未使用的情况下,基于表示是否是访问冲突状态的第3信息,设定消耗电力模式。 [0088] In addition, information handling systems may also refer to a case where a cache miss and the second information is not used, based on the first information indicating whether I access conflict situations third information, the power consumption mode is set. 由此,信息处理系统在存储器访问冲突时设定成超频时钟,能够消除访问冲突。 Accordingly, the information processing system is set to overclock clock memory access conflict, access violation can be eliminated.

[0089] 另外,信息处理系统也可以在第3信息表示访问非冲突状态的状态4下,由PMU将总线的时钟设定成通常模式,在第3信息表示访问冲突状态时,由PMU将总线的时钟设定成超频时钟模式。 When [0089] Further, the information processing system 4 may also represent a state where non-conflicting state access by the PMU to the bus clock is set to the normal mode, the third information indicates an access violation information in the third state, the bus PMU overclock clock set to the clock mode. 由此,信息处理系统由于仅在访问冲突的产生中设定成超频时钟,因此能够仅增加最低限的消耗电力就完成处理。 Accordingly, since only the information processing system is set to overclock clock generation access conflict, it is possible to increase only the minimum power consumption of the processing is completed.

[0090] 另外,信息处理系统也可以在表示状态4的情况下,将DMA控制器设定成高密度传输。 [0090] In addition, information handling systems may also be expressed in a case where the state 4, the DMA controller is set to a high-density transmission. 在信息处理系统处于状态4时,是PIO传输单发地产生的状态,为PIO传输的产生频度低的状态,因此通过将DMA控制器设定成高密度传输,能够进行高效的数据传输。 In the information processing system is in state 4, the state is the single PIO transfer is generated, the frequency of occurrence of a low state of PIO transfer. Therefore, by setting the DMA controller to transfer a high density, efficient data transmission can be performed.

[0091] 另外,信息处理系统也可以在第3信息表示访问冲突状态时,基于表示在由CPU执行的处理是否存在时间限制的第4信息,来设定消耗电力模式。 [0091] In addition, information handling systems may also be represented in the third state information access violation, based on the fourth information indicating whether the time limit is present in the processing performed by a CPU, sets the power consumption mode. 由此,信息处理系统仅在存在时间限制的实时响应时,才设定成超频时钟,能够消除访问冲突。 Accordingly, the information processing system only when there is a time limit in real-time response, it is set to overclock clock, access violation can be eliminated.

[0092] 另外,信息处理系统也可以在第4信息表示存在时间限制的状态5 — I时,由PMU将总线的时钟设定成超频时钟模式,在第4信息表示没有时间限制的状态5 — 2时,设定成通常模式。 [0092] Further, the information processing system may also indicate the presence of the time limit the fourth information State 5 - I, the PMU by the bus clock set to the clock mode overclock, the fourth information indicates no time limit state 5 - 2, is set to the normal mode. 由此,由于信息处理系统仅在访问冲突产生过程中且存在实时限制时才设定成超频时钟,因此能够仅增加最低限的消耗电力就完成处理。 Thereby, since when the information processing system in real time and there is only limited access conflicts during clock is set to overclock, it is possible to increase only the minimum power consumption of the process is completed.

[0093] 另外,信息处理系统也可以在表示状态5 -1的情况下,将DMA控制器设定成高密度传输,在表不状态5 — 2的情况下,将DMA控制器设定成低密度传输。 [0093] In addition, information handling systems may also be expressed in a case where the state of the 5-1, the DMA controller will be set to a high-density transmission, in the state table is not 5 - case 2, the DMA controller is set to a low density transfer. 由此,信息处理系统在处于状态5 — I时,由于存在实时限制因此可进行高效的数据传输,能够遵守实时限制。 Thus, the information processing system is in state 5 - I, due to the presence of real-time constraint resulting in efficient data transmission, it is possible to comply with real-time constraints. 另外,信息处理系统处于状态5 —2时,进行低密度传输,从而由于易于进行PIO传输,因此能够消除访问冲突。 Further, the information processing system in the state -2 5, low-density transmission, thereby easily performed since the PIO transfer, access violation can be eliminated.

[0094] 另外,在本实施方式中说明了的总线控制器108可以由标准单元(Standardcell)或结构化的ASIC (Application Specific Integrated Circuit)等面向特定用途的IC (以下,仅称为“ASIC”。)或FPGA 等PLD (Programmable Logic Device)来实现。 [0094] Further, in the present embodiment described embodiment the bus controller 108 may be made of standard cells (Standardcell) or structured ASIC (Application Specific Integrated Circuit) and the like for a particular purpose IC (hereinafter, simply referred to as "ASIC" etc.) or FPGA PLD (Programmable Logic Device) is achieved. 具体地,例如利用HDL语言来功能性地定义上述总线控制器108的功能(高速缓存缺失检测部119〜生成部123),通过逻辑合成该HDL语言并赋予ASIC、PLD,能够制造总线控制器108。 Specifically, for example, define the function (cache miss detecting unit generation unit 119~ 123) using said bus controller 108 functionally HDL language, by the logic synthesis HDL language and impart ASIC, PLD, the bus controller 108 can be manufactured .

[0095] 附图标记说明 [0095] REFERENCE NUMERALS

[0096] 100…信息处理系统;101、102…CPU ;103、104…DMA控制器;105…存储器控制器;106…共享资源;107…PMU ;108…总线控制器;109…总线;110、112、116…状态寄存器;111、113…高速缓存;114、115、117…控制寄存器;118…设定部;119…高速缓存缺失检测部;120…高速I/O检测部;121…访问冲突检测部;122…设定寄存器;123…生成部。 [0096] The information processing system 100 ...; 101,102 ... CPU; 103,104 ... DMA controller; memory controller 105 ...; 106 ... shared resource; 107 ... PMU; 108 ... bus controller; bus ... 109; 110, status registers 112, 116 ...; 111, 113, ... cache; control registers 114, 115 ...; 118 ... setting unit; ... 119 cache miss detecting unit; 120 ... High-speed I / O unit detector; 121 ... access Violation detecting unit; setting register 122 ...; 123 ... generating unit.

Claims (16)

  1. 1.一种信息处理系统,其特征在于,包含: 与总线连接的CPU ; 与总线连接的设备; 被所述CPU或者所述设备访问的存储器;以及设定消耗电力模式的电源模式控制电路, 所述电源模式控制电路基于表示所述CPU内的高速缓存的高速缓存命中或者高速缓存缺失的第I信息、和表示所述设备的激活状态或者非激活状态的第2信息,来设定所述消耗电力模式。 1. An information processing system comprising: a CPU connected to a bus; connected to the bus apparatus; by the CPU or a memory of the access device; and a power supply mode is set to the power consumption mode control circuit, the power mode control circuit I, based on the information representing the cache in the CPU cache hit or a cache miss, and second information indicating the activation state of the device or the non-active state, sets the power consumption mode.
  2. 2.根据权利要求1所述的信息处理系统,其特征在于, 当所述第I信息表示高速缓存的高速缓存命中并且所述第2信息表示非激活状态时,所述电源模式控制电路设定低消耗电力模式。 The information processing system according to claim 1, wherein, when the I-cache information indicating a cache hit and the second information indicates an inactive state, said power supply mode setting control circuit low power consumption mode.
  3. 3.根据权利要求1或者权利要求2所述的信息处理系统,其特征在于, 当所述第I信息表示高速缓存的高速缓存命中并且所述第2信息表示激活状态时,所述电源模式控制电路设定通常模式。 The information processing system according to claim 1 or claim 2, characterized in that, when the I-cache information indicating a cache hit and the second information indicates the active state, said power supply mode control circuit sets the normal mode.
  4. 4.根据权利要求1至权利要求3中任一项所述的信息处理系统,其特征在于, 当所述第I信息表示高速缓存的高速缓存缺失并且所述第2信息表示非激活状态时,设定通常模式。 1 to 4. The information processing system as claimed in claim any one of claim 3, wherein, when the I-cache miss information indicates a cache and the second information indicates an inactive state, setting the normal mode.
  5. 5.根据权利要求1至权利要求4中任一`项所述的信息处理系统,其特征在于, 当所述第I信息表示高速缓存的高速缓存缺失并且所述第2信息表示激活状态时,所述电源模式控制电路基于表示所述总线的访问冲突状态或者非冲突状态的第3信息,来设定所述消耗电力模式。 4 according to any one `item information processing system according to claims 1, wherein, when the I-cache miss information indicates a cache and the second information indicates the active state, the power mode control circuit showing the third information based on a state or a non-conflict access violation status of the bus, sets the power consumption mode.
  6. 6.根据权利要求1至权利要求5中任一项所述的信息处理系统,其特征在于, 当所述第3信息表示所述总线的访问非冲突状态时,所述电源模式控制电路设定成通常模式,当所述第3信息表示所述总线的访问冲突状态时,所述电源模式控制电路设定成超频时钟模式。 6. The information processing system according to any of claims 1, wherein, when the third information indicating the state of non-conflicting bus access, said control circuit sets the power mode to the normal mode, when the third information indicates a state of the bus access conflicts, the power mode control circuit is set to the clock mode overclocking.
  7. 7.根据权利要求3或者权利要求5所述的信息处理系统,其特征在于, 所述设备包含DMA控制器,并被设定DMA传输模式。 7. The information processing system of claim 5 according to claim 3 or claim, characterized in that said apparatus comprises a DMA controller, and is set DMA transfer mode.
  8. 8.根据权利要求5所述的信息处理系统,其特征在于, 当所述第3信息表示所述总线的访问冲突状态时,所述电源模式控制电路基于表示针对由所述CPU执行的处理是否存在时间限制的第4信息,来设定所述消耗电力模式。 The information processing system according to claim 5, wherein, when the third information indicating the state of the bus when an access violation, whether the power mode control circuit for the processing executed by the CPU based representation 4 there is a time limit information, sets the power consumption mode.
  9. 9.根据权利要求8所述的信息处理系统,其特征在于, 当所述第4信息表示存在时间限制时,所述电源模式控制电路设定成超频时钟模式,当所述第4信息表示不存在时间限制时,所述电源模式控制电路设定成通常模式。 9. The information processing system according to claim 8, wherein, when the fourth information indicating the presence of a time limit, the power mode control circuit is set to overclock clock mode, when the fourth information indicating no when there is a time limit, the control circuit sets the power mode to the normal mode.
  10. 10.根据权利要求8所述的信息处理系统,其特征在于, 所述设备包含DMA控制器,当所述第4信息表示存在时间限制时,所述DMA控制器的传输单位被设定成所述总线的总线宽度,当所述第4信息表示不存在时间限制时,所述传输单位被设定成比所述总线的总线宽度小的值。 The information processing system according to claim 8, characterized in that said apparatus comprises a DMA controller, when the fourth information indicating the presence of a time limit, a transmission unit of the DMA controller is set by said bus width of the bus, when the fourth information indicating the time limit does not exist, the transmission unit is set to a value smaller than the width of the bus to the bus.
  11. 11.一种信息处理系统,其特征在于,包含: 与总线连接的CPU ;与总线连接的设备; 借助所述总线与所述CPU以及所述设备连接的存储器; 监视所述总线的访问的总线控制器;以及基于来自所述总线控制器的设定信号来设定消耗电力模式的电源模式控制电路, 所述总线控制器包含: 检测表示所述CPU内的高速缓存的高速缓存命中或者高速缓存缺失的第I信息的第I电路;和检测表示所述设备的激活状态或者非激活状态的第2信息的第2电路。 11. An information processing system comprising: a CPU connected to a bus; devices connected to the bus; said bus means and said CPU and a memory connected to the device; monitoring said bus access to the bus a controller; power mode and sets the power consumption mode based on the setting signal from the control circuit of the bus controller, said bus controller comprising: detecting a cache within the CPU cache hit or a cache I, I, circuit information is missing; and detecting a state of activation of the device or the inactive state of the second circuit of the second information.
  12. 12.根据权利要求11所述的信息处理系统,其特征在于, 所述总线控制器包含检测所述CPU是否连续访问所述存储器的第3信息的第3电路。 12. The information processing system according to claim 11, wherein said bus controller comprises a third circuit detects the third information whether or not said CPU continuously accesses the memory.
  13. 13.根据权利要求11所述的信息处理系统,其特征在于, 所述总线控制器包含储存第4信息的第4电路,其中,所述第4信息表示针对所述CPU执行的处理是否存在时间限制。 13. The information processing system according to claim 11, wherein said fourth circuit comprises a bus controller 4 to store information, wherein the fourth information indicating processes performed for the presence or absence of CPU time limit.
  14. 14.根据权利要求11或者权利要求12所述的信息处理系统,其特征在于, 包含基于从所述第I电路输出的第I信息和从所述第2电路输出的第2信息来生成所述设定信号的第5电路。 14. An information processing system as claimed in claim 12 or claim 11, characterized in that it comprises based on the information from the I-I circuit generates and outputs the second information outputted from the second circuit the 5 sets the first signal circuit.
  15. 15.根据权利要求11至权利要求14中任一项所述的信息处理系统,其特征在于, 所述第I电路基于所述CPU内的状态寄存器的输出来检测所述第I信息, 所述第2电路基于所述设备内的控制寄存器的输出来检测所述第2信息。 According to claim 11 to claim 14 in the information processing system according to any preceding claim, wherein said first circuit detects the second I I based on the output information of said status register in the CPU, the a control circuit based on an output of the second register in the device to detect the second information.
  16. 16.根据权利要求12所述的信息处理系统,其特征在于, 所述第3电路基于控制所述存储器的存储器控制器内的状态寄存器的输出来检测所述第3信息。 16. The information processing system according to claim 12, wherein said third circuit output state register in the memory controller controlling the memory based on detecting the third information.
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6128833B2 (en) * 2012-12-25 2017-05-17 キヤノン株式会社 Processing equipment
KR20150083558A (en) * 2014-01-10 2015-07-20 삼성전자주식회사 Method for processing data on storage device and storage device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832280A (en) * 1995-10-05 1998-11-03 International Business Machines Corporation Method and system in a data processing system for interfacing an operating system with a power management controller.
JPH11134077A (en) * 1997-10-30 1999-05-21 Hitachi Ltd Processor and system for data processing
JP2003242104A (en) * 2002-02-19 2003-08-29 Nec Microsystems Ltd Bus control method, and information processing device
CN1503142A (en) * 2002-11-19 2004-06-09 株式会社瑞萨科技 Cache system and cache memory control device controlling cache memory having two access modes
CN101135928A (en) * 2006-08-29 2008-03-05 松下电器产业株式会社 Processor system
JP2008269365A (en) * 2007-04-20 2008-11-06 Matsushita Electric Ind Co Ltd Information processor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11110363A (en) * 1997-09-30 1999-04-23 Sharp Corp Multiprocessor system
JP4860104B2 (en) * 2003-10-09 2012-01-25 日本電気株式会社 The information processing apparatus
US7822911B2 (en) * 2007-08-15 2010-10-26 Micron Technology, Inc. Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same
US7945764B2 (en) * 2008-01-11 2011-05-17 International Business Machines Corporation Processing unit incorporating multirate execution unit
JP4871921B2 (en) 2008-07-02 2012-02-08 ルネサスエレクトロニクス株式会社 Data processing system and program development system
US8762644B2 (en) * 2010-10-15 2014-06-24 Qualcomm Incorporated Low-power audio decoding and playback using cached images

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832280A (en) * 1995-10-05 1998-11-03 International Business Machines Corporation Method and system in a data processing system for interfacing an operating system with a power management controller.
JPH11134077A (en) * 1997-10-30 1999-05-21 Hitachi Ltd Processor and system for data processing
JP2003242104A (en) * 2002-02-19 2003-08-29 Nec Microsystems Ltd Bus control method, and information processing device
CN1503142A (en) * 2002-11-19 2004-06-09 株式会社瑞萨科技 Cache system and cache memory control device controlling cache memory having two access modes
CN101135928A (en) * 2006-08-29 2008-03-05 松下电器产业株式会社 Processor system
JP2008269365A (en) * 2007-04-20 2008-11-06 Matsushita Electric Ind Co Ltd Information processor

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