CN105068951B - A kind of system-on-chip bus with non-isochronous transfers structure - Google Patents
A kind of system-on-chip bus with non-isochronous transfers structure Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F13/404—Coupling between buses using bus bridges with address mapping
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Abstract
The invention discloses a kind of system-on-chip bus, including Request Priority queue, moderator group, address and control signal selector, internet and address decoder；Main equipment sends bus request signal to address decoder；Address decoder sends application signal according to bus request signal to Request Priority queue；Request Priority queue will apply for signal latch, generate chip selection signal, and chip selection signal is sent to internet, meanwhile, application signal is sent to moderator group；Moderator group sends arbitration result signal to internet, and according to the data and handshake of arbitration result signal behavior main equipment to slave device direction, internet controls slave device to the data and handshake in main equipment direction always according to chip selection signal for internet.There is different transmission times between the system-on-chip bus master-slave equipment different in large-area chips of the present invention, realizes high speed, parallel, real-time communication between devices.
Description
Technical Field
The invention belongs to the field of on-chip communication, and particularly relates to a system-on-chip bus with a non-isochronous transmission structure.
Background
With the development of integrated circuit technology, systems on chip require more processor cores, coprocessor cores and more peripherals on chip. Moreover, the rapid development of multimedia, communication and other technologies requires high-speed, parallel and real-time communication among the devices on the chip.
In pursuit of higher transmission rate, the frequency of system bus is continuously increased, but because of the more functional requirements of multi-core, multi-peripheral and so on, the area of chip is continuously expanded even under the support of more precise process, which results in the contradiction between the transmission time of on-chip device and the bus frequency. When various existing bus systems are used in a high-frequency high-bandwidth system in a large-area chip, if data are transmitted in a pipeline manner, more pipeline registers are used, and a large amount of resources are consumed; otherwise, the bus clock frequency can only be reduced, which affects the overall performance of the bus.
If there is only one data bus, when two devices are communicating data, the other device may only wait, or allow a higher priority device to interrupt the current communication, if it wishes to access the other device, although there is no conflict between the devices. The single data bus limits the data throughput of the whole system, and a system with high data throughput requirements needs to communicate among multiple groups of devices at the same time: as long as the correlation is not due to devices (e.g., two masters accessing one slave at a time), the communication can be done in parallel.
Fig. 1 is a schematic diagram of connection of devices on chip in a certain system in the prior art, in which a slave device 0 (slave 0) can only be accessed by a master device 0 and a master device 1, and a slave device 1 and a slave device group 2 can be accessed by all master devices. Slave 0, slave 1 and slave group 2 may be accessed in parallel by three different masters. A simple illustration of the architecture 10, i.e. the bus, is shown. The arbitration mechanism of the bus may cause high priority devices to preferentially use the bus and lower priority devices to wait. Without proper means, when a higher priority device continues to issue bus requests, a lower priority device may not receive bus access for a long time. For systems with higher real-time requirements, such as communication systems, the bus needs to have the ability to ensure that a device gains access to the bus within a given bus cycle.
Disclosure of Invention
Technical problem to be solved
The invention aims to provide a system-on-chip bus, which has different transmission time (clock period) between different master devices and different slave devices on a large-area chip and realizes high-speed, parallel and real-time communication between the devices.
(II) technical scheme
The invention provides a system-on-chip bus, which is used for communication between a master device and a slave device and comprises a request priority queue, an arbiter group, an address and control signal selector, an internet and an address decoder; wherein,
the master device sends a bus request signal to an address decoder and sends a corresponding address signal and a corresponding control signal to an address and control signal selector;
the address decoder sends an instant application vector to an arbiter group according to the bus request signal, and simultaneously sends the instant application vector to a request priority queue;
the request priority queue latches the instant application vector to generate a chip selection signal, and sends the chip selection signal to the internet, and simultaneously generates a queue application vector to send to the arbiter group;
the arbiter group sends out an arbitration result signal to the address and control signal selector according to the application signal, and the address and control signal selector selects an address signal and a control signal of the master device according to the arbitration result signal and transmits the address signal and the control signal to the slave device;
the arbiter group further sends an arbitration result signal to the internet, the internet selects data and handshake signals in the direction from the master device to the slave device according to the arbitration result signal, and the internet also controls the data and handshake signals in the direction from the slave device to the master device according to the chip selection signal.
(III) advantageous effects
1. The invention provides a system-on-chip bus, in which transmission cycles among devices are allowed to be different, the bus frequency is determined by the device with shorter transmission time, and paths among devices with transmission distances more than one bus cycle are restricted by multi-cycle paths, so that the contradiction between the bus frequency and the transmission time among the devices on a large-area chip is solved in a uniform bus form by the minimum hardware overhead, and the bus frequency can be higher according to the design requirement; high-speed data transmission can be carried out between devices with short transmission time in a bus cycle; the devices with longer transmission time do not need to use a pipeline register and a bus agent, so that the resource consumption is reduced.
2. The system-on-chip bus provided by the invention provides a corresponding bus protocol, the protocol is a single-edge pipeline bus protocol, the protocol divides the transmission of bus application, address and control signals and the transmission of data into two pipeline levels for operation, the key is that no extra bus application operation is needed, the address and control signals are provided when the bus is applied, and the data is transmitted and received according to handshake signals in the next beat, so that the single-edge operation ensures high bus frequency, pipeline operation and no extra bus application time, and the bus efficiency even when the bus is handed over is ensured; in particular, the master device of the multi-cycle path does not affect the response efficiency of the bus and the slave devices when the transmission is not burst.
3. The system-on-chip bus provided by the invention has the request priority queue to determine the priority of the request according to the priority of the request entering the queue, thereby ensuring the real-time property of the request response of the equipment.
Drawings
FIG. 1 is a simplified diagram of prior art system-on-chip device connections.
Fig. 2 is a block diagram of a system-on-chip bus according to an embodiment of the present invention.
Fig. 3 is a block diagram of an arbiter bank in an embodiment of the invention.
Fig. 4 is a schematic diagram of 3-to-3 full interconnection between a master device and a slave device in the embodiment of the present invention.
Fig. 5 is a structural diagram of a priority queue for application in the embodiment of the present invention.
Fig. 6 is a block diagram of interfaces of a master device and a slave device in an embodiment of the present invention.
FIG. 7 is a timing diagram of one-to-one transmission between a master device and a slave device according to an embodiment of the present invention.
FIG. 8 is a timing diagram illustrating a main line handover in an embodiment of the present invention.
FIG. 9 is a timing diagram illustrating the bus transactions between masters in a two-cycle path and a one-cycle path according to an embodiment of the present invention.
FIG. 10 is a timing diagram illustrating a burst write sequence and bus handoff in an embodiment of the invention.
FIG. 11 is a timing diagram of a burst transfer for a two-cycle path according to an embodiment of the present invention.
FIG. 12 is a timing diagram of multiple masters contending for a bus simultaneously according to an embodiment of the invention.
Detailed Description
The invention provides a system-on-chip bus, which comprises a request priority queue, an arbiter group, an address and control signal selector, an internet and an address decoder, wherein the arbiter group is used for receiving a request priority queue; the master device sends a bus request signal to an address decoder and sends a corresponding address signal and a corresponding control signal to an address and control signal selector; the address decoder sends an instant application vector to the arbiter group and the request priority queue according to the bus request signal; the request priority queue latches the application signal to generate a chip selection signal, the chip selection signal is sent to the Internet, meanwhile, an application vector of each slave device group is given according to a first-in first-out principle, and the result of directly selecting an address decoder when the queue is empty is sent to an arbiter group as the application signal of the current period; the arbiter group sends an arbitration result signal to the address and control signal selector according to the application signal, the address and control signal selector selects an address signal and a control signal of the master device according to the arbitration result signal, transmits the address signal and the control signal to the slave device arbiter group and sends the arbitration result signal to the internet, the internet selects data and handshake signals in the direction from the master device to the slave device according to the arbitration result signal, and the internet controls the data and handshake signals in the direction from the slave device to the master device according to the chip selection signal.
In one embodiment, the system-on-chip bus further comprises an address and control signal memory, and the arbiter group further returns a grant signal to the request priority queue, and causes the bus request signal of the master device to enter the request priority queue according to the grant signal, and causes the address signal and the control signal of the master device to enter the address and control signal memory.
In one embodiment, the system-on-chip bus further includes a first selector, when the request priority queue is empty, the request priority queue sends a queue empty signal to a control terminal of the first selector, and the first selector directly selects the address signal and the control signal sent by the master device to the address and control signal selector, otherwise, the first selector selects the address signal and the control signal in the address and control signal memory to the address and control signal selector.
In one embodiment, the system-on-chip bus further includes a second selector, when the request priority queue is empty, the request priority queue sends a queue empty signal to a control terminal of the second selector, and the second selector directly selects the application signal sent by the address decoder to the arbiter group, otherwise, the second selector selects the application signal sent by the request priority queue to the arbiter group.
In one embodiment, the arbiter bank includes one or more arbiters, the number of arbiters being the same as the number of slave devices.
In one embodiment, the arbitration logic in the arbiter is a priority encoder.
In one embodiment, the system-on-chip bus further includes an arbitration result register, and the arbiter group first sends the arbitration result signal to the arbitration result register, and then sends the arbitration result signal to the internet through the arbitration result register.
In one embodiment, after the master device finishes sending the signal in the present cycle, the master device directly sends write data to the slave device in the next cycle without waiting for an authorization signal, and listens for a handshake signal sent by the slave device.
In one embodiment, the system-on-chip bus transfers signals sent by the master device to the slave device over one or more clock cycles.
In one embodiment, the control signal sent by the master device carries master device timing information, and the response period of the slave device is controlled by the master device timing information so as to match the transmission rate between the master device and the slave device. The system-on-chip bus has different transmission time (clock period) between different master and slave devices on a large-area chip, and realizes high-speed, parallel and real-time communication between the devices.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
Fig. 2 is a block diagram of a system-on-chip bus according to the present invention, and as shown in fig. 2, the bus 10 includes a request priority queue 201, an arbiter bank 202, an address and control signal memory 203, an address and control signal selector 204, an arbitration result register 205, an interconnection network 206, an address decoder 207, a first selector 208, and a second selector 209 (in the lower left corner of the block diagram, a clock input triangle mark indicates that the structure is sequential logic or that sequential logic exists, and the mark is applicable to other figures herein). Each master device can send out a bus request signal at any time and simultaneously give out an address and a control signal of the request; the address decoder 207 gives an instant application vector to the corresponding slave device (group) according to the address given by the master device, sends the instant application vector to the request priority queue 201, controls the data selection from the slave device end to the master device end as a chip selection signal after latching, and gives a queue application vector according to the first-in first-out principle by the request priority queue; for each slave device (group), according to a 'queue empty' signal corresponding to a slave device queue in the request priority queue 201, selecting an immediate application vector if the request priority queue is empty, selecting a queue application vector if the request priority queue is not empty, and taking a selection result as an input of an arbiter group 202, namely a bus request signal; after arbitration, the result of each arbiter returns a response signal to the request priority queue 201, so that the requests which are not granted to the bus instantly enter the request priority queue 201, and simultaneously, the related address/control signals enter the address and control signal memory 203, and the address and control signals of the master device granted to the bus are selectively transmitted to each slave device port by the arbitration result control address and control signal selector 204 and are latched by the slave devices, so that the data can be read and written in the next period conveniently; while the arbitration result will also be latched in the arbitration result register 205 for the interconnect network 206 to select data (write data) and handshake signals in the master-to-slave direction, the chip select signals latched in the request priority queue 201 will control data (read data) and handshake signals in the interconnect network 206 slave-to-master direction. The master may give a write data or read data from the slave in the next operating cycle of sending out the request signal, while giving the next bus request. The number of arbiters in the arbiter group 202 is the same as the number of current slave devices (groups), and the corresponding relationship between the arbiters and the slave devices (groups) is as shown in fig. 1.
Fig. 3 is an internal structural diagram of the arbiter 202 in the present embodiment. First, the input of each arbiter is an application vector with the same bit width as the number of masters that can access the slave (group), a value of "high" in the vector indicates that the corresponding master needs to apply for access to the slave (group), and the arbitration logic selects a master from these applications to give to the bus. Because the bus application priority queue 201 is present, the main role of the arbitration logic is to select one from the masters that are simultaneously applying for the bus, so the arbitration logic can be a simpler fixed priority arbitration logic, such as a priority encoder. Each arbiter output is a vector with the same bit width as the input, and the output corresponding to the valid input is 'one hot', i.e. only one master is granted to the bus; invalid inputs (0 vectors) correspond to invalid outputs (0 vectors). The output of each arbiter will control the selection of the corresponding slave device(s) input, and the data/control signals of the granted master device may drive the data/control bus of that slave device(s). For the same master device, each arbiter gives a grant signal, and performs an or operation on all grant bits of the corresponding master device, that is, the grant signal of the master device, where the grant signal is mainly used to control the storage logic on the bus: a request priority queue 201, an address and control signal memory 203.
Fig. 4 is a diagram of a 3-to-3 full interconnect example of the interconnect network 206 in this embodiment. The value of the arbitration result register 205 is used to select the selector in the master-to-slave direction, and the chip select signal in the request priority queue 201 is used to select the selector in the slave-to-master direction. The address and control signal selector 204 is similar to the right column selector in fig. 4, but the difference is that the selection signal of the address and control signal selector 204 is not the arbitration result after being registered, but the arbitration result currently generated by the arbiter.
Fig. 5 is a structural diagram of the request priority queue 201 in the present embodiment. The memory comprises a first memory 501, a second memory 502 and a third memory 503, wherein the first memory 201 is used for storing effective address decoding values, and the storage size is m × n bits (m represents the number of master devices, n represents the number of slave device groups, the same applies below); the second memory 502 is for storing the maximum priority value of the slave device group and has a storage size of n × log2m, i.e. eachEach slave device group corresponding to a width log2m of memory; the third memory 503 is used for storing the master priority value and has a size of m × log2m, i.e. one log for each master2m, of the memory. The initial value of the memory 502 is 0, indicating that the application queue corresponding to the slave device group is empty, and the queue empty signal generated thereby is used to control the first selector 208 and the second selector 209. The third memory 503 is the priority of each master device, and when a request is not immediately authorized and needs to be enqueued, the "increment 1" value of the second memory 502 of the application object is selected as the priority value of the master device, and the second memory 502 also needs to be "increment 1". When the queue is output, only the request of the master device with the priority value equal to 1 is selected as output. When a request for a slave device group in the output is one-hot and the slave device group gives a valid "SValid" signal, then a "self-subtract 1" is required corresponding to the second memory 502, the "self-subtract 1" signal is selected by the chip select signal, enabling the master priority value "self-subtract 1". For the second memory 502, when the "increase 1" signal is the same as the "decrease 1" signal ("XNOR"), the original value is maintained.
The following describes the method of use of the bus, i.e. its bus protocol.
Two stages are divided from the initiation of a bus request by a master device to the transmission of data by using the bus, wherein the first stage is the initiation of the request by the master device, and the second stage is the data transmission between the master device and the slave device. Stage one and stage two are two pipeline stages in the bus operation, i.e. when the first request is in stage two, the master device can signal stage one of the second request (for the same slave device group) at the same time.
S1, the master device sends request, address and control signals, and simultaneously judges that the slave device is valid, which belongs to the first stage;
s2, after the slave device is active high, in the next clock cycle, if it is write operation, the master device sends write data and gives a master device active signal, if it is read operation, the master device latches the read data when the slave device active signal is high, which belongs to stage two;
s3 while S2 is ongoing, the master may concurrently proceed with S1 of the next bus request;
s4, at the same time of S1, the slave device latches the address and control signal sent by the master device, which belongs to stage one;
s5, while proceeding with S2, according to the address and the control signal, if the write operation is performed, the slave writes the write data into the corresponding address when the master valid signal is high, and if the read operation is performed, the data of the corresponding address and the slave valid signal are transmitted, which belongs to stage two;
while S6 proceeds at S5, the slave device may proceed at S4 according to the next S1 performed by the master device.
The bus on chip is different from other bus protocols on chip in that other buses on chip need a separate bus application link, and after the bus is authorized, the device occupies the bus, and sends address signals, control signals and reads and writes data; in the invention, the bus application, the address and the control signal are sent out simultaneously as the first stage, as long as the application vector corresponding to the master device does not exist in the current application priority queue, the second stage is automatically entered, the write data is sent or the read data is received, and if the handshake signals of the two parties are effective, the request is ended (except burst operation).
The operation period of each device is different, and the specific operation time is determined by the transmission time between the master device and the bus control and selection logic. The time required for the master device's signal to travel to a particular structure exceeds the period required by the current bus frequency, the device will automatically down-convert to the corresponding frequency to sample the data and handshaking signals from the bus. When one slave receives the burst request of the multi-cycle path master, the slave also automatically reduces the frequency to the corresponding frequency for data and handshake signal sampling.
Fig. 6 is a block diagram of interfaces of a master device and a slave device in the present invention. The data bit width is determined according to the actual bit width requirement of the equipment, and the general bit width is 16/32/64/128 bits. The control signal (Ctrl) includes at least control information such as read/write, burst, and master timing information. The chip select signal (Sel) of a slave device is used in the group of slave devices, which is not required if an arbiter corresponds to a single slave device.
Table 1 is a detailed description of the master-slave device interface signals.
TABLE 1
Fig. 7 is a timing chart showing access to a slave (group) by a master when the slave (group) is empty and the corresponding request queue is empty. The master device continuously issues four non-burst read/write requests, wherein the SValid signal is a handshake signal issued by the slave device, and the bus and the master device determine whether the current data ends the current operation or maintains the data of the previous period by reading the signal. Where the Req signal indicates that the master is currently making a valid bus request, and is primarily one of the enqueue enable signals for the application priority queue 201, and will be entered into the request queue if the request is not granted. Since the request for address C cannot respond in time, the master device also needs to maintain its request for address D while maintaining the write data output because the current request cannot enter the queue when the SValid signal is low.
Fig. 8 is a timing diagram illustrating the bus handover between two masters when a request queue is empty for a slave (group). In the figure, two masters respectively issue bus requests in two consecutive cycles, and smoothly and without waiting, the use right of the bus is obtained.
FIG. 9 is a timing diagram of master devices of a two cycle path and a one cycle path reading from and writing to each other using a bus. Where a signal with the suffix "_ p 1" indicates a value of the signal near the output and "_ p 2" indicates a value near the input. "WData #1_ p 1" represents a write data line near the master 1 that, after entering the second cycle, drives the "WData" bus through the arbiter's selector; "RData #1_ p 2" represents a read data line near master 1, which is an extension of the "RData" bus on only master 1 segment. As can be seen from the figure, the master device of the double-cycle path occupies the same time for the slave device and the bus when initiating the non-burst request as the master device of the single-cycle path. But the multi-cycle path master needs four bus cycles to acknowledge the end of the bus access and then proceed to the next bus application.
FIG. 10 is a schematic diagram of burst write timing and bus interfacing. In the figure, the master 1 initiating a burst write request is responded to ending the burst with the master giving an end of burst signal "BLast". During burst transmission, both the master device and the slave device need to give handshake signals, i.e. the "MValid" and "SValid" signals in the figure, as long as one of the signals is low, it indicates that the currently transmitted data is invalid, and the current data needs to be transmitted again. The figure also illustrates simple bus contention, when the master device 1 performs burst transmission, the master device 2 applies for a bus, and since the bus is busy and the handshake signal from the bus to the master device 2 is low, the master device needs to maintain data until the handshake signal is high. While master 1 gives the end-of-burst signal, the master may simultaneously issue another request for that slave, in the present invention, the bus will prioritize the request of the corresponding master 2 and then the second request of the corresponding master 1 due to the request priority queue 201.
Fig. 11 is a timing diagram of a burst transfer for a two cycle path. It can be seen from the figure that basically no two bus cycles transmit a data, but the application signal, the handshake signal and the burst complete signal are all given in the form of a single cycle, so that after a data is sent out, the handshake signal is sampled from the second clock cycle (inclusive), and if valid, a new data is sent out in the next cycle. The transmission time of one data is equal to or greater than 2 cycles instead of a positive integer multiple of 2. It is worth mentioning that if the slave device in the two devices of the multi-cycle path transmission is a high-speed device, the burst transmission mode is not advocated for transmission, and the non-burst bus access mode is advised, so that the operation efficiency of the slave device is not affected.
Fig. 12 is a timing diagram of multiple masters contending for a bus at the same time. The figure illustrates the contention of three masters for the same slave group. For the simultaneous application of masters 1, 2, and 3, the bus first responds to the request of master 1, and then the requests of masters 2 and 3 enter the request priority queue 201. Although the master device 1 issues a request again in the second operation cycle, the second request of the master device 1 enters the request queue because the request of the master devices 2 and 3 is still in the request queue. The right to use for the second cycle of the bus is granted to master 2 via request arbitration to masters 2, 3. In the case where the master waits for a bus grant, if a write operation, the master is required to maintain data at the write data port until a valid handshake signal from the bus is sampled.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A system-on-chip bus (10) for communication between a master device and a slave device, comprising a request priority queue (201), an arbiter bank (202), an address and control signal selector (204), an interconnect network (206), and an address decoder (207); wherein,
the master device sending a bus request signal to the address decoder (207) and sending corresponding address signals and control signals to the address and control signal selector (204);
the address decoder (207) sends an instant application vector to an arbiter group according to the bus request signal, and simultaneously sends the instant application vector to a request priority queue (201);
the request priority queue (201) latches the instant application vector to generate a chip selection signal, and sends the chip selection signal to the internet (206), and simultaneously generates a queue application vector to send to the arbiter group (202);
the arbiter group (202) sends an arbitration result signal to the address and control signal selector (204) and the internet according to an application signal, wherein the application signal comprises the instant application vector and the queue application vector;
the address and control signal selector (204) selects an address signal and a control signal of the master device according to the arbitration result signal and transmits the address signal and the control signal to the slave device;
the interconnection network (206) selects data and handshake signals in the direction from the master device to the slave device according to the arbitration result signal, and controls the data and handshake signals in the direction from the slave device to the master device according to the chip selection signal.
2. The system-on-chip bus (10) as recited in claim 1 further comprising an address and control signal memory (203), wherein the arbiter bank (202) further returns a grant signal to the request priority queue (201), and wherein the bus request signal from the master is entered into the request priority queue (201) in response to the grant signal, and wherein the address signal and the control signal from the master are entered into the address and control signal memory (203).
3. The system-on-chip bus (10) as claimed in claim 2 further comprising a first selector (208), wherein when the request priority queue (201) is empty, the request priority queue (201) sends a queue empty signal to a control terminal of the first selector, the first selector directly selects the address signals and control signals sent by the master device to the address and control signal selector (204), otherwise, the first selector selects the address signals and control signals in the address and control signal memory (203) to the address and control signal selector (204).
4. The system-on-chip bus (10) as claimed in claim 1, further comprising a second selector, wherein when the request priority queue (201) is empty, the request priority queue (201) sends a queue empty signal to a control terminal of the second selector, the second selector directly selects the immediate application vector sent by the address decoder (207) to the arbiter bank (202), otherwise, the second selector selects the queue application vector sent by the request priority queue (201) to the arbiter bank (202).
5. The system-on-chip bus (10) according to claim 1, wherein the arbiter bank (202) comprises at least one arbiter, the number of arbiters being the same as the number of slave devices.
6. The system-on-chip bus (10) as recited in claim 5, wherein the arbitration logic in the arbiter is a priority encoder.
7. The system-on-chip bus (10) according to claim 1, further comprising an arbitration result register (205), wherein the arbiter bank (202) first sends the arbitration result signal to the arbitration result register (205) and then sends the arbitration result signal to the interconnect network (206) through the arbitration result register (205).
8. The system-on-chip bus (10) according to claim 1, wherein the request priority queue (201) comprises: the device comprises a first memory (501), a second memory (502) and a third memory (503), wherein the first memory (501) is used for storing effective address decoding values, the second memory (502) is used for storing a slave device group maximum priority value, and the third memory (503) is used for storing a master device priority value.
9. System-on-chip bus (10) according to claim 1, characterized in that it signals according to the following protocol:
after the master device finishes sending the signals in the period, the master device does not need to wait for an authorization signal, directly sends write data to the slave device in the next period, and monitors handshake signals sent by the slave device.
10. The system-on-chip bus (10) according to claim 1, characterized in that it transmits the signal sent by the master device to the slave device by one or more clock cycles.
11. The system-on-chip bus (10) as recited in claim 1, wherein the master device sends control signals with master timing information, and wherein the master timing information controls the slave device's response period to match the transmission rate between the master device and the slave device.
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| TWI567561B (en) * | 2015-11-26 | 2017-01-21 | 新唐科技股份有限公司 | Bus system |
| CN111625377B (en) * | 2017-04-01 | 2023-11-28 | 北京忆芯科技有限公司 | Agent and method for adding items to queue |
| CN110765053B (en) * | 2019-10-23 | 2023-03-10 | 山东华芯半导体有限公司 | N-M AXI bus controller and configurable arbitration mechanism implementation method thereof |
| CN111666239A (en) * | 2020-07-10 | 2020-09-15 | 深圳开立生物医疗科技股份有限公司 | Master-slave equipment interconnection system and master-slave equipment access request processing method |
| CN112506821B (en) * | 2020-09-27 | 2023-02-28 | 山东云海国创云计算装备产业创新中心有限公司 | System bus interface request arbitration method and related components |
| CN112949247B (en) * | 2021-02-01 | 2022-05-20 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN112929252B (en) * | 2021-05-11 | 2021-07-09 | 上海擎昆信息科技有限公司 | Parallel data transmission system and method suitable for bus port |
| CN115017093B (en) * | 2022-05-06 | 2023-03-24 | 北京中科昊芯科技有限公司 | Method and device for on-chip external bus communication |
| CN114968890A (en) * | 2022-05-27 | 2022-08-30 | 中国第一汽车股份有限公司 | Synchronous communication control method, device, system and storage medium |
| CN114968865B (en) * | 2022-07-22 | 2022-09-27 | 中科声龙科技发展（北京）有限公司 | Bus transmission structure and method and chip |
| CN117725005A (en) * | 2023-12-05 | 2024-03-19 | 北京智联安科技有限公司 | Data transmission method, master device, slave device and electronic device |
| CN117435518B (en) * | 2023-12-21 | 2024-03-22 | 沐曦集成电路(上海)有限公司 | Protection method for master-slave read-write data |
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