CN105068951B - A kind of system-on-chip bus with non-isochronous transfers structure - Google Patents
A kind of system-on-chip bus with non-isochronous transfers structure Download PDFInfo
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- CN105068951B CN105068951B CN201510446036.7A CN201510446036A CN105068951B CN 105068951 B CN105068951 B CN 105068951B CN 201510446036 A CN201510446036 A CN 201510446036A CN 105068951 B CN105068951 B CN 105068951B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4031—Coupling between buses using bus bridges with arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
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Abstract
The invention discloses a kind of system-on-chip bus, including Request Priority queue, moderator group, address and control signal selector, internet and address decoder；Main equipment sends bus request signal to address decoder；Address decoder sends application signal according to bus request signal to Request Priority queue；Request Priority queue will apply for signal latch, generate chip selection signal, and chip selection signal is sent to internet, meanwhile, application signal is sent to moderator group；Moderator group sends arbitration result signal to internet, and according to the data and handshake of arbitration result signal behavior main equipment to slave device direction, internet controls slave device to the data and handshake in main equipment direction always according to chip selection signal for internet.There is different transmission times between the system-on-chip bus master-slave equipment different in large-area chips of the present invention, realizes high speed, parallel, real-time communication between devices.
Description
Technical field
The invention belongs to chip-on communication field, more particularly to a kind of system-on-chip bus with non-isochronous transfers structure.
Background technology
With the development of integrated circuit technique, the more processor cores of system-on-chip demand, coprocessor core and more
On-Chip peripheral.And the fast development of the technology such as multimedia, communication, it is desirable to possess between each equipment of on piece at a high speed, it is parallel,
Real-time communication mode.
In order to pursue the transmission rate of higher, the frequency of system bus is being continuously improved, but because multinuclear, more peripheral hardwares etc.
More functional requirements, under the support of more precision process, the area of chip is also constantly expanding, this causes on piece to set
Standby contradiction between transmission time and bus frequency.The a variety of bus systems that there is currently, use the height in large-area chips
When on frequency high bandwidth system communication, if data to be carried out to the transmission of continuous-flow type, person will cause to use more pipeline register, consume
Vast resources；Otherwise Bus Clock Rate can only be reduced, thus influences the performance of bus entirety.
If only a data bus, when two equipment are into row data communication, other equipment is if it is desired to another
A equipment accesses, although not conflicting between equipment and equipment, which can only wait, or allows higher preferential
The equipment of level interrupts current communication.Forms data bus limits the data throughout of whole system, to data throughput requirement
Higher system needs to be carried out at the same time communication between multigroup equipment：So long as not because equipment produces, related (such as two masters set
It is standby to access a slave device at the same time), it is possible to parallel communicate.
Fig. 1 be the prior art some system on piece equipment connection diagram, wherein slave device 0 (from 0) can only be by
Main equipment 0 and main equipment 1 access, and slave device 1, slave device group 2 can be accessed by all main equipments.Slave device 0,1 and of slave device
Slave device group 2 parallel can be obtained and accessed by three different main equipments.Structure 10 is the simple signal of bus in figure.Bus it is secondary
Sanction mechanism can make the equipment of high priority preferentially use bus, and then the equipment of lower priority just needs to wait.If no
Appropriate mode, when the higher equipment of priority constantly sends bus request, low priority equipment can cannot get bus for a long time
The right to use.For the higher system of requirement of real-time, such as communication system is, it is necessary to which bus has the ability to ensure that an equipment is referring to
Within the fixed bus cycles, the right to use of bus is obtained.
The content of the invention
(1) technical problems to be solved
It is an object of the present invention to provide a kind of system-on-chip bus, the different master particularly in large-area chips
There is different transmission times (clock cycle) between slave device, realize at a high speed, parallel, real-time communication between devices.
(2) technical solution
The present invention provides a kind of system-on-chip bus, preferential for the communication between main equipment and slave device, including request
Level queue, moderator group, address and control signal selector, internet and address decoder；Wherein,
Main equipment sends bus request signal to address decoder, and sends corresponding address signal and control signal to ground
Location and control signal selector；
Described address decoder sends application vector immediately to moderator group, at the same time will according to the bus request signal
Immediately the application vector is sent to Request Priority queue；
The vector of application immediately is latched in the Request Priority queue, generates chip selection signal, and described choosing is believed
Number send to the internet, meanwhile, generation queue application vector is sent to the moderator group；
Moderator group sends arbitration result signal to address and control signal selector according to application signal, and address is with controlling
Signal selector is transmitted to slave device according to the address signal and control signal of arbitration result signal behavior main equipment；
Moderator group also sends arbitration result signal to internet, internet and is set according to arbitration result signal behavior master
The data and handshake in slave device direction to the utmost, internet control slave device to main equipment direction always according to chip selection signal
Data and handshake.
(3) beneficial effect
1st, the present invention provides a kind of system-on-chip bus, allows the transmission cycle between equipment different in the bus, and
Bus frequency is determined that the equipment room path of transmission range more than one bus cycles is by more by the shorter equipment of wherein transmission time
Periodic path is constrained so that with unified bus form, minimum hardware spending solves the bus in large-area chips
The contradiction of frequency and equipment room transmission time, bus frequency therefore can according to design requirement higher；Transmission time is short to be set
The data transfer of high speed can be carried out between standby with the bus cycles；Being posted without using flowing water between the longer equipment of transmission time
Storage and bus agent, reduce resource consumption.
2nd, system-on-chip bus provided by the invention, gives respective bus agreement, which is the continuous-flow type on unilateral edge
Bus protocol, which is divided to the transmission of bus application, address and control signal and the transmission of data carries out in two pipelining-stages
Operation, it is important to be not required extra bus application to operate, provide address and control signal when applying for bus, next bat according to
Handshake sending and receiving data so that unilateral to ensure that high bus frequency along operation, continuous-flow type operates and without extra bus
Application time, ensure that bus efficiency when bus-handover；Particularly, in non-burst transmission, multi-cycle path
Main equipment does not interfere with the response efficiency of bus and slave device.
3rd, system-on-chip bus provided by the invention, has Request Priority queue, to determine to ask into the priority of enqueue
The priority asked, ensure that the real-time of device request response.
Brief description of the drawings
Fig. 1 is the rough schematic of system-on-chip apparatus connection in the prior art.
Fig. 2 is the structure chart of system-on-chip bus provided in an embodiment of the present invention.
Fig. 3 is the structure chart of moderator group in the embodiment of the present invention.
Fig. 4 is 3 pair of 3 full interconnection schematic diagram between master-slave equipment in the embodiment of the present invention.
Fig. 5 is the structure chart of request priority queue in the embodiment of the present invention.
Fig. 6 is main equipment and the interface framework of slave device in the embodiment of the present invention.
Fig. 7 is man-to-man transmission time sequence figure between master-slave equipment in the embodiment of the present invention.
Fig. 8 is that main line joins sequence diagram in the embodiment of the present invention.
Fig. 9 be in the embodiment of the present invention binary cycle path and one the monocycle path main equipment mutually use bus
The sequence diagram being written and read.
It is that sequential and bus-handover timing diagram are write in a burst in Figure 10 embodiment of the present invention.
It is the burst transfer sequence diagram of two periodic paths in Figure 11 embodiment of the present invention.
In Figure 12 embodiment of the present invention it is multiple main equipments while competes the sequence diagram of a bus.
Embodiment
The present invention provides a kind of system-on-chip bus, including Request Priority queue, moderator group, address and control signal
Selector, internet and address decoder；Main equipment sends bus request signal to address decoder, and sends correspondingly
Location signal and control signal are to address and control signal selector；Address decoder is according to bus request signal, to moderator group
Application vector immediately is sent with Request Priority queue；Request Priority queue will apply for signal latch, generate chip selection signal, and
Chip selection signal is sent to internet, meanwhile, according to first in first out provide each slave device group application vector, queue
The result that sky directly selects address decoder is sent to moderator group as the application signal of current period；Moderator group is according to Shen
Please signal send arbitration result signal to address and control signal selector, address is with control signal selector according to arbitration result
The address signal and control signal of signal behavior main equipment, and be transmitted to slave device moderator group and also send arbitration result signal extremely
Internet, internet is according to the data and handshake of arbitration result signal behavior main equipment to slave device direction, interconnection
Network controls slave device to the data and handshake in main equipment direction always according to chip selection signal.
In one embodiment, which further includes an address and control signal memory, described secondary
Device group is cut out also to return to an authorization signal and give Request Priority queue, according to authorization signal make the bus request signal of main equipment into
Enter Request Priority queue, while the address signal of main equipment and control signal is entered address and control signal memory.
In one embodiment, which further includes a first selector, when Request Priority queue
For sky when, the control terminal of Request Priority queue transmit queue spacing wave to first selector, first selector directly selects master
The address signal and control signal that equipment is sent are to address and control signal selector, otherwise, first selector selection address and
Address signal and control signal in control signal memory are to address and control signal selector.
In one embodiment, which further includes a second selector, when Request Priority queue
For sky when, the control terminal of Request Priority queue transmit queue spacing wave to second selector, second selector directly selects ground
The application signal that location decoder is sent is to moderator group, and otherwise, second selector selects the application that Request Priority queue is sent
Signal is to moderator group.
In one embodiment, moderator group includes one or more moderators, the quantity of moderator and slave device
Quantity is identical.
In one embodiment, the arbitrated logic in moderator is priority encoder.
In one embodiment, which further includes arbitration result register, and moderator group first sends institute
Arbitration result signal is stated to send arbitration result signal to the arbitration result register, then by the arbitration result register
To the internet.
In one embodiment, main equipment is after this cycle has sent signal, without waiting for authorization signal, next
Cycle, which directly transmits, writes data to slave device, and monitors the handshake that the slave device is sent.
In one embodiment, system-on-chip bus makes the signal of main equipment transmission by one or more clock cycle
It is transmitted to slave device.
In one embodiment, main equipment timing information is carried in the control signal that main equipment is sent, passes through main equipment
Timing information controls the response cycle of the slave device, to match the transmission rate between main equipment and slave device.The present invention's
There is different transmission times (clock cycle) between system-on-chip bus master-slave equipment different in large-area chips, realize
At a high speed, parallel, real-time communication between devices.
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
Fig. 2 is the structure chart of system-on-chip bus provided by the invention, as shown in Fig. 2, bus 10 includes Request Priority
Queue 201, moderator group 202, address and control signal memory 203, address and control signal selector 204, arbitration result
Register 205, internet 206, address decoder 207, first selector 208 and second selector 209 (structure diagram in figure
The lower left corner expression structure that has clock input warning triangle be sequential logic or wherein there are sequential logic, the mark to be applicable in
Other figures in this article).Each main equipment can send bus request signal at any time, while provide the ground of the request
Location and control signal；Address decoder 207 provides instant application according to the address that main equipment provides to corresponding slave device (group)
Vector, and will apply for that vector is sent to Request Priority queue 201 immediately, after latch slave device end is controlled as chip selection signal extremely
The data selection of main equipment extreme direction, while Request Priority queue gives dequeue application vector according to the principle of first in, first out；
For each slave device (group), according to " queue empty " signal that slave device queue is corresponded in Request Priority queue 201, if empty
Then application is vectorial immediately for selection, selects queue application vectorial if non-NULL, selection result is as the input of moderator group 202
Bus request signal；After arbitration, the result of each moderator returns to answer signal to Request Priority queue 201, enables
The request for not authorized bus immediately enters Request Priority queue 201, while relevant address/control signal enters address
With in control signal memory 203, and the address of the main equipment of bus being awarded and control signal controls address by arbitration result
Each slave device port is transmitted to the selection of control signal selector 204, is latched by slave device, is read and write easy to next cycle
Data；Arbitration result will also be latched in arbitration result register 205 at the same time, and main equipment is selected to from setting for internet 206
The data (writing data) and handshake in standby direction, the chip selection signal being latched in Request Priority queue 201 will be controlled and interconnected
206 slave device of network to main equipment direction data (reading data) and handshake.Main equipment is sending out the next of request signal
A operation cycle, it is possible to provide and write data or read the data from slave device, while provide next bus request.Its
In, the moderator quantity in moderator group 202 is identical with the quantity of current slave device (group), in both correspondence such as Fig. 1
The correspondence of moderator and slave device (group).
Fig. 3 is the cut-away view of moderator 202 in the present embodiment.The input of moderator each first be a bit wide with
An identical application vector of the main equipment quantity of the slave device (group) can be accessed, vectorial intermediate value represents that corresponding master sets for " height "
It is standby to need to apply for the access to the slave device (group), and arbitrated logic is exactly to select a main equipment to give always from these applications
Line.Because the presence of bus request priority queue 201, the main function of arbitrated logic herein is exactly to apply for bus from the same time
Main equipment in select one, so arbitrated logic can be the arbitrated logic of a relatively simple fixed priority, such as
Priority encoder.Each moderator output is the vector with inputting same bit wide, and it is " solely heat " effectively to input corresponding output,
Only have a main equipment that bus is awarded；The invalid corresponding invalid output (0 vector) of input (0 vector).Each moderator is defeated
The input selection of corresponding slave device (group) will be controlled by going out, this can be driven from setting by being authorized to the data/control signals of main equipment
Data/the controlling bus of standby (group).For same main equipment, each moderator can provide authorization signal, by all correspondences
The mandate position of main equipment carries out OR operation, is exactly the authorization signal of the main equipment, which is mainly used in controlling bus
Store logic：Request Priority queue 201, address and control signal memory 203.
Fig. 4 is one 3 pairs 3 full interconnection exemplary plots of internet 206 in the present embodiment.Wherein, arbitration result register
For selecting main equipment, to the selector in slave device direction, the chip selection signal in Request Priority queue 201 is used to select 205 value
Slave device is selected to the selector in main equipment direction.Wherein address and the selection of the row of right side one in control signal selector 204 and Fig. 4
Device is similar, and difference is, the selection signal of address and control signal selector 204 is not the arbitration result after deposit,
But the arbitration result currently produced by moderator.
Fig. 5 is the structure chart of Request Priority queue 201 in the present embodiment.It includes the storage of first memory 501, second
502 and the 3rd memory 503 of device, wherein, first memory 201 is used to store effective address decoding value, storage size for m ×
N (m represents main equipment number, and n represents slave device group number, similarly hereinafter)；Second memory 502 is used to store slave device group maximum preferentially
Value, storage size is n × log2M, i.e., it is log that each slave device group, which corresponds to a width,2The memory of m；3rd memory 503
For storing main equipment preferred value, storage size is m × log2M, i.e., each main equipment correspond to a log2The memory of m.Storage
The initial value of device 502 is 0, represents the application queue of corresponding slave device group as sky, the queue spacing wave produced with this is used to control
First selector 208 and second selector 209.3rd memory 503 is the priority of each main equipment, when have request not by
Immediately needs are authorized to fall in lines, the second memory 502 of selection application object " increase preferred value of the 1 " value as the main equipment certainly,
The second memory 502 is also required to " from increasing 1 " at the same time.Queue only selects preferred value equal to the request of the main equipment of " 1 " when exporting
As output.When the request that some slave device group is directed in output is solely heat, and the slave device group provides effective " SValid "
Signal, then corresponding to second memory 502 needs " subtracting 1 certainly ", is somebody's turn to do " subtracting 1 certainly " signal and is selected by chip selection signal, enables main equipment
Preferred value " subtracts 1 " certainly.For second memory 502, when " 1 " signal of increasing and " subtracting 1 certainly " signal are identical (inclusive OR) certainly, then keep
Initial value.
The application method of the bus is described below, i.e. its bus protocol.
Bus request is initiated from main equipment and is divided into two stages to using bus transfer data, and the stage one is that main equipment is initiated
Request, the stage two is data transfer between master-slave equipment.Stage one and stage two are two pipelining-stages in bus operation, i.e.,
During one request progress stage two, main equipment can provide the stage one of second request (being directed to same slave device group) at the same time
Signal.
S1 main equipments send request, address and control signal, while judge to input slave device useful signal, this belongs to the stage
One；
S2 is after slave device is effectively for height, and in next clock cycle, if write operation, main equipment sends and writes data, and
Main equipment useful signal is provided, if read operation, main equipment latches when slave device useful signal is high and reads data, this belongs to rank
Section two；
For S3 while S2 is carried out, main equipment can be carried out at the same time the S1 of next bus request；
For S4 while S1 is carried out, slave device will receive address and the control signal latch that main equipment is sent, this belongs to
Stage one；
S5 while S2 is carried out, according to address and control signal, if write operation, then in main equipment effectively believe by slave device
Number for it is high when will write data write corresponding address, if read operation, then send corresponding address data and slave device useful signal,
This belongs to the stage two；
For S6 while S5 is carried out, slave device can carry out S4 according to next S1 that main equipment carries out.
It is with other on-chip bus agreement differences, other on-chip bus need a single bus application link,
Equipment occupies bus after bus grant, sends address signal, control signal and read-write data；And in the present invention, by bus
Application is simultaneously emitted by as the stage one with address, control signal, as long as without corresponding main equipment in present application priority query
Application vector, then automatically into the stage two, transmission, which is write data or received, reads data, if both sides' handshake effectively if terminate this
Secondary request is (except burst operation).
The operation cycle of each equipment simultaneously differs, the concrete operations time by main equipment and bus marco, selection logic it
Between transmission time determine.Time needed for the signal transmission of main equipment to some specific structure will more than Current bus frequency
The cycle asked, then the equipment will be downconverted to data and handshake of the corresponding frequency sampling from bus automatically.When one from
Equipment receives the burst request of multi-cycle path main equipment, and slave device is also downconverted to corresponding frequency and carries out data and hold automatically
Hand signal sampling.
Fig. 6 is main equipment and the interface framework of slave device in the present invention.Wherein data bit width is according to the actual bit wide need of equipment
Ask and determine, general bit wide is 16/32/64/128.When read/write, burst, main equipment are included at least in control signal (Ctrl)
The control information such as sequence information.The chip selection signal (Sel) of slave device is used in slave device group, if certain moderator correspond to it is single from setting
Standby, then the slave device is without the signal.
Table 1 is the specific descriptions to master-slave equipment interface signal.
Table 1
Sequence diagram shown in Fig. 7, be for some slave device (group) and corresponding requests queue for it is empty when, some main equipment pair
The accessing time sequence figure of the slave device (group).Main equipment continuously have issued four non-burst read/write requests, wherein SValid letters in figure
Number handshake sent by slave device, bus and main equipment determine whether current data terminates currently by reading the signal
Operation, or maintained the data in a upper cycle.Wherein Req signals represent that the current main equipment proposes once effective bus Shen
Please, the signal mainly as request priority queue 201 one of enable signal of joining the team, if the request is not authorized to,
It can enter in request queue.Since the request for address C can not timely respond in figure, main equipment is maintaining to write data output
At the same time, it is also desirable to its request to address D is maintained, because current request cannot be introduced into queue when SValid signals are low.
Be shown in Fig. 8 for some slave device (group) and corresponding requests queue for it is empty when, two main equipments handing-over buses
Time diagram.Two main equipments send bus request, and smoothly N-free diet method respectively in continuous two cycles in figure
The right to use for obtaining bus.
Fig. 9 be a binary cycle path and one the monocycle path the sequential that is mutually written and read using bus of main equipment
Figure.Wherein suffix is that " signal of _ p1 " represents value of the bars close to output terminal, and " _ p2 " represents the value close to input terminal.
After " WData#1_p1 " represents that the write data line close to main equipment 1, the data enter second round, by the selector of moderator
Drive " WData " bus；The read data line of the close main equipment 1 of " RData#1_p2 " expression is " RData " bus in only main equipment
1 section of extended line.It can be seen from the figure that the main equipment in binary cycle path is when initiating non-burst request, to slave device and total
The holding time of line is identical with the main equipment in monocycle path.But the multi-cycle path main equipment needs to use four bus weeks
Phase, which just can confirm that, terminates this bus access, then carries out next bus application.
Figure 10 is that sequential and bus-handover schematic diagram are write in a burst.In figure, main equipment 1 is initiated burst write request and is rung
Should, burst end signal " BLast " is provided with main equipment and terminates burst.In burst transfer, main equipment and slave device are required for
Handshake is provided, i.e., " MValid " " SValid " signal in figure, as long as one of signal is low, means that current transmission
Data invalid, it is necessary to transmit current data again.The competition of simple bus is further illustrated in figure, is dashed forward in main equipment 1
To send out in transmitting procedure, main equipment 2 proposes bus application, and since bus is hurried, bus is low to the handshake of main equipment 2, so
Main equipment needs to maintain data, until handshake is height.While main equipment 1 provides burst end signal, main equipment can
To be simultaneously emitted by another request for the slave device, in the present invention, due to Request Priority queue 201, bus can be excellent
The first request of corresponding main equipment 2, then second request of corresponding main equipment 1 again.
Figure 11 is the burst transfer sequence diagram of two periodic paths.It can be seen from the figure that do not have two bus cycles substantially
A data are transmitted, but apply for that signal, handshake, burst end signal are provided in the form of monocyclic, so one
After a data are sent, handshake is sampled since the second clock cycle (containing), effectively then next cycle sends new data.
So the transmission time of a data is the positive integer times more than or equal to 2 cycles, rather than 2.It is if it is noted that more all
Slave device is high-speed equipment in two equipment of phase path transmission, does not advocate and is transmitted using the mode of burst transfer, is built
The non-burst bus access mode of view, will not so have an impact the operational efficiency of slave device.
Figure 12 is multiple main equipments while competes the sequence diagram of a bus.Illustrate that three main equipments to same in figure
The competition of a slave device group.For applying while main equipment 1,2,3, bus responds the request of main equipment 1 first, and then master sets
Standby 2,3 request will enter Request Priority queue 201.Although second operation cycle main equipment 1 have issued a Shen again
Please, but due to there is the application of main equipment 2,3 in application queue, so second application of main equipment 1 will enter request
Queue.The right to use of the second period of bus, arbitrates by the request to main equipment 2,3, authorizes main equipment 2.In main equipment
In the case of waiting bus grant, if write operation, demand main equipment maintains to write the data of data port, it is known that samples and
From the effective handshake of bus.
Specific embodiment above, has carried out further specifically the purpose of the present invention, technical solution and beneficial effect
It is bright, it should be understood that these are only the specific embodiment of the present invention, it is not intended to limit the invention, it is all in the present invention
Spirit and principle within, any modification, equivalent substitution, improvement and etc. done, should be included in protection scope of the present invention it
It is interior.
Claims (11)
1. a kind of system-on-chip bus (10), for the communication between main equipment and slave device, it is characterised in that excellent including asking
First level queue (201), moderator group (202), address and control signal selector (204), internet (206) and address decoding
Device (207)；Wherein,
The main equipment sends bus request signal to described address decoder (207), and sends corresponding address signal and control
Signal processed is to described address and control signal selector (204)；
Described address decoder (207) sends application vector immediately to moderator group, at the same time will according to the bus request signal
Immediately the application vector is sent to Request Priority queue (201)；
The Request Priority queue (201) latches the vector of application immediately, generates chip selection signal, and described choosing is believed
Number send to the internet (206), meanwhile, generation queue application vector is sent to the moderator group (202)；
The moderator group (202) sends arbitration result signal to described address and control signal selector according to application signal
(204) and the internet, wherein, the application signal includes queue application vector described in the vector sum of application immediately；
Described address and the address signal of control signal selector (204) main equipment according to the arbitration result signal behavior
With control signal, and the slave device is transmitted to；
Data and shake hands letter of the internet (206) according to the arbitration result signal behavior main equipment to slave device direction
Number, and slave device is controlled to the data and handshake in main equipment direction according to the chip selection signal.
2. system-on-chip bus (10) according to claim 1, it is characterised in that further include an address and control signal
Memory (203), the moderator group (202) also returns to an authorization signal and gives Request Priority queue (201), according to described
Authorization signal makes the bus request signal of the main equipment enter the Request Priority queue (201), while makes described
The address signal of main equipment and the control signal enter address and control signal memory (203).
3. system-on-chip bus (10) according to claim 2, it is characterised in that further include a first selector
(208), when the Request Priority queue (201) is empty, Request Priority queue (201) the transmit queue spacing wave is extremely
The control terminal of the first selector, the first selector directly select the address signal and control letter that the main equipment is sent
Number to described address and control signal selector (204), otherwise, the first selector selection described address is deposited with control signal
Address signal and control signal in reservoir (203) are to described address and control signal selector (204).
4. system-on-chip bus (10) according to claim 1, it is characterised in that a second selector is further included, when
When the Request Priority queue (201) is empty, Request Priority queue (201) the transmit queue spacing wave to described second
The control terminal of selector, the instant application that the second selector directly selects address decoder (207) transmission are vectorial to described
Moderator group (202), otherwise, the second selector select the queue application that the Request Priority queue (201) sends to
Measure to the moderator group (202).
5. system-on-chip bus (10) according to claim 1, it is characterised in that the moderator group (202) is included extremely
A few moderator, the quantity of the moderator are identical with the quantity of the slave device.
6. system-on-chip bus (10) according to claim 5, it is characterised in that the arbitrated logic in the moderator is
Priority encoder.
7. system-on-chip bus (10) according to claim 1, it is characterised in that further include arbitration result register
(205), the moderator group (202) first sends the arbitration result signal to the arbitration result register (205), then passes through
The arbitration result register (205) sends arbitration result signal to the internet (206).
8. system-on-chip bus (10) according to claim 1, it is characterised in that the Request Priority queue (201)
Including：First memory (501), second memory (502) and the 3rd memory (503), wherein, the first memory
(501) it is used to store effective address decoding value, the second memory (502) is used to store slave device group maximum preferred value,
3rd memory (503) is used to store main equipment preferred value.
9. system-on-chip bus (10) according to claim 1, it is characterised in that it carries out signal biography by following agreement
It is defeated：
The main equipment, without waiting for authorization signal, directly transmits in next cycle after this cycle has sent signal and writes number
According to the extremely slave device, and monitor the handshake that the slave device is sent.
10. system-on-chip bus (10) according to claim 1, it is characterised in that it passes through one or more clocks week
Phase makes the signal transmission that the main equipment is sent to the slave device.
11. system-on-chip bus (10) according to claim 1, it is characterised in that the control letter that the main equipment is sent
Main equipment timing information is carried in number, the response cycle of the slave device is controlled by the main equipment timing information, with matching
Transmission rate between the main equipment and the slave device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI567561B (en) * | 2015-11-26 | 2017-01-21 | 新唐科技股份有限公司 | Bus system |
| CN108664335B (en) * | 2017-04-01 | 2020-06-30 | 北京忆芯科技有限公司 | Method and device for queue communication through proxy |
| CN110765053B (en) * | 2019-10-23 | 2023-03-10 | 山东华芯半导体有限公司 | N-M AXI bus controller and configurable arbitration mechanism implementation method thereof |
| CN112506821B (en) * | 2020-09-27 | 2023-02-28 | 山东云海国创云计算装备产业创新中心有限公司 | System bus interface request arbitration method and related components |
| CN112949247B (en) * | 2021-02-01 | 2022-05-20 | 上海天数智芯半导体有限公司 | Phase-based on-chip bus scheduling device and method |
| CN112929252B (en) * | 2021-05-11 | 2021-07-09 | 上海擎昆信息科技有限公司 | Parallel data transmission system and method suitable for bus port |
| CN115017093B (en) * | 2022-05-06 | 2023-03-24 | 北京中科昊芯科技有限公司 | Method and device for on-chip external bus communication |
| CN114968890A (en) * | 2022-05-27 | 2022-08-30 | 中国第一汽车股份有限公司 | Synchronous communication control method, device, system and storage medium |
| CN114968865B (en) * | 2022-07-22 | 2022-09-27 | 中科声龙科技发展（北京）有限公司 | Bus transmission structure and method and chip |
| CN117435518B (en) * | 2023-12-21 | 2024-03-22 | 沐曦集成电路(上海)有限公司 | Protection method for master-slave read-write data |
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