CN115017093B - Method and device for on-chip external bus communication - Google Patents
Method and device for on-chip external bus communication Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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Abstract
The embodiment of the application provides a method and a device for on-chip external bus communication, wherein the method comprises the following steps: receiving a data transmission instruction from an on-chip target device, wherein the data transmission instruction is used for accessing an external storage device; configuring a target read-write time sequence for an external bus, and sending the data transmission instruction to the external storage device through the external bus. On one hand, the external bus communication protocol in some embodiments of the application supports multiple data communication protocols, and the data communication requirements under different scenes are met by supporting the multiple protocols, and on the other hand, the external bus read-write time sequence which can be dynamically configured can be used in some embodiments of the application to optimize and solve the technical problem that the data transmission needs different establishment and retention times due to the difference of different circuit boards in the practical application of a chip.
Description
Technical Field
The present application relates to the field of on-chip external buses, and in particular, embodiments of the present application relate to a method and an apparatus for on-chip external bus communication.
Background
As shown in fig. 1, the diagram is a block diagram of an on-chip internal bus, an external bus interface, and an external storage device provided in the related art.
The SOC bus (as an example of an internal bus) of fig. 1 is mainly a bus used inside a chip, and standard buses generally used include AHB, AXI, APB, and the like. The SOC bus performs read-write access to the peripheral device, and the read-write access requests (or called data transmission instructions) mainly come from the kernel, the DMA, and other related instructions for accessing the peripheral device sent by the master device, and the instructions at least include: data (data to be written to the external storage device by another on-chip device or data read from the external storage device by another on-chip device), an access address (i.e., address information sent by the SOC bus to the external bus interface in fig. 1), an access data bit width, and whether it is a write operation or a read operation (i.e., read-write instructions sent by the SOC bus to the external bus interface in fig. 1).
The external bus interface shown in fig. 1 mainly receives a read-write operation command from the SOC bus, and related information such as write operation data, and configures an access protocol of the external bus interface according to the actual situation of the peripheral device, so as to perform read-write operation on the external storage device. In fig. 1, the external bus interface includes: the external bus interface sends read-write instructions, address signals or data to the external storage device.
The external storage device in fig. 1 stores write data in a corresponding storage unit according to a read/write command, or returns read data to an external bus interface according to an access address, and then returns the read data to the SOC bus.
The prior art at least has the following technical problems: most external bus interfaces only support a single protocol (for example, only one read/write protocol module is included on the external bus interface module in fig. 1), so that different rates required by data transmission cannot be met, and a fixed data transmission protocol cannot meet the requirements of some application scenarios.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method and an apparatus for on-chip external bus communication, where on one hand, an external bus communication protocol in some embodiments of the present application supports multiple data communication protocols, and meets requirements of data communication in different scenarios by supporting multiple protocols, and on the other hand, some embodiments of the present application can optimize and solve technical problems of different establishment and retention times of data transmission requirements due to differences of different circuit boards in practical applications of a chip by using a dynamically configurable external bus read-write timing sequence.
In a first aspect, an embodiment of the present application provides a method for on-chip external bus communication, where the method includes: receiving a data transmission instruction from an on-chip target device, wherein the data transmission instruction is used for accessing an external storage device; configuring a target read-write time sequence for an external bus, and sending the data transmission instruction to the external storage device through the external bus, wherein the external bus supports multiple external bus protocols.
On one hand, in practical application of a chip, due to differences of different circuit boards, establishment and holding time of data transmission needs are different, a fixed data transmission protocol may not meet the needs of some application scenarios, and the problem can be solved by adopting the configurable time sequence of the embodiment of the application. On the other hand, some embodiments of the present application satisfy the needs of data communication in different scenarios by supporting multiple protocols.
In some embodiments, prior to receiving the data transfer instruction from the on-chip target device, the method further comprises: receiving data transmission instructions of a plurality of devices on the chip, wherein one device corresponds to one data transmission instruction; assigning usage rights of the external bus to the target device of the plurality of devices according to an arbitration policy.
Some embodiments of the present application ensure that multiple devices can use the same external bus in a time-sharing manner through an arbitration policy, thereby improving the use efficiency of the external bus.
In some embodiments, before said assigning the usage right of the external bus to the target device of the plurality of devices according to an arbitration policy, the method comprises: caching the data transmission instruction of each device to obtain caching information; wherein the receiving a data transmission instruction from an on-chip target device includes: and reading a data transmission instruction corresponding to the target equipment from the cache information.
Some embodiments of the present application need to cache data transmission instructions from multiple on-chip devices first, which caches data and instructions first, and does not block the execution of other instructions of subsequent cores and DMA devices, so that the program execution is more efficient.
In some embodiments, the types of devices include at least: an external host, a kernel, a DMA, and other devices, wherein the arbitration policy comprises: the data transmission instruction from the external host belongs to a first priority, the data transmission instruction from the kernel belongs to a second priority, the data transmission instruction from the DMA belongs to a third priority, and the data transmission instruction from the other equipment belongs to a fourth priority.
Some embodiments of the present application may ensure that important devices can preferentially use the external bus by setting different priorities for different kinds of devices.
In some embodiments, the arbitration policy further comprises: performing data transmission on a plurality of data transmission instructions under the same priority by adopting a polling mechanism; if there are several devices with the same priority applying bus, the maximum data transmission quantity of the device obtaining the bus use right is controlled by the maximum data transmission quantity value.
Some embodiments of the present application guarantee that devices of the same priority have an opportunity to use the external bus by setting the value Bmax of the maximum amount of data transfer and the setting of the polling function.
In some embodiments, when the target device is a kernel or a DMA, the sending the data transfer instruction to the external storage device through an external bus includes: the external bus is used by locking the external bus.
According to some embodiments of the application, when the kernel and the DMA adopt the external bus for data transmission, the use right of the external bus is occupied for a long time in a bus locking mode, and the design is mainly used for solving the problem of atomic operation and ensuring the consistency of required data.
In some embodiments, the plurality of external bus protocols includes a first external bus protocol, and the control signals corresponding to the first external bus protocol include: the effective chip selection information comprises setup, active and hold, wherein the continuous cycle time of any parameter of the setup, the active and the hold can be dynamically configured.
In the external bus of some embodiments of the present application, setup, active, and hold supported by the first external bus protocol (i.e., the slow protocol) are dynamically configurable, and the requirements of chip setup and hold times in different scenarios can be met by setting different setup and hold times.
In some embodiments, the control signals corresponding to the first external bus protocol further include: preparing information, wherein the preparing information is a signal from the external storage device, the preparing information for extending a cycle time corresponding to the active.
Some embodiments of the present application use the configurable ready information ready signal as an input signal to the external bus interface of the external memory device, the data transmission period of active can be prolonged, and the problem that data cannot be processed in time during data transmission is solved.
In some embodiments, the plurality of external bus protocols includes a second external bus protocol, and the control signal corresponding to the second external bus protocol further includes a delay signal, wherein a value of the delay signal delay is configured to control a delay between the output control address signal and the data signal.
Some embodiments of the present application support the control and data period delay configurable by the second external bus protocol (i.e., the fast protocol), and by configuring the value of delay, the delay between the output control address signal and the output data signal can be controlled.
In a second aspect, some embodiments of the present application provide an apparatus for on-chip external bus communication, the apparatus comprising: the external bus interface comprises a first external bus protocol module and a second external bus protocol module, wherein the first external bus protocol module can complete the dynamic configuration of setup, active and hold included by the effective chip selection information, and the second external bus protocol can complete the dynamic configuration of time delay between the control address signal and the data signal.
In some embodiments, the apparatus further comprises: an arbiter connected to an input of the external bus interface, the arbiter configured to determine a target device from among a plurality of on-chip devices that may use an external bus.
In some embodiments, the arbiter is provided with: the device comprises an input interface for receiving external bus use requests of various devices, a kernel access locking signal input interface, a DMA access locking signal input interface and a maximum transferable data quantity input interface, and is used for outputting external bus use request response signals aiming at various devices.
In a third aspect, some embodiments of the present application provide a chip, the chip comprising: a plurality of external hosts, a plurality of kernels, and a plurality of DMAs; the apparatus as in any embodiment of the first aspect, wherein the plurality of external hosts, the plurality of cores, and the plurality of DMAs are coupled to an input of an arbiter included with the apparatus.
In a fourth aspect, some embodiments of the present application provide a system comprising: a plurality of external hosts, a plurality of kernels, and a plurality of DMAs; the apparatus of any embodiment of the first aspect, wherein the plurality of external hosts, the plurality of cores, and the plurality of DMAs are coupled to an input of an arbiter of the apparatus; and the external storage equipment is connected with the output end of the external bus interface included by the device.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a schematic diagram illustrating a communication process between an external bus interface and an external storage unit according to the related art;
FIG. 2 is a block diagram of an apparatus for on-chip external bus communication according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of input and output signals of an arbiter according to an embodiment of the present application;
FIG. 4 is a timing diagram illustrating an embodiment of the present invention when an external host requests a bus to interrupt a kernel data transmission when the external bus is not locked;
FIG. 5 is a schematic diagram of polling priorities provided by an embodiment of the present application;
FIG. 6 is a schematic diagram of bus arbitration for different priority applications according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a slow protocol provided in an embodiment of the present application;
FIG. 8 is a diagram illustrating a fast protocol provided by an embodiment of the present application;
fig. 9 is a flowchart of a method for communicating over an external bus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As described in the background section, most of the prior art external bus interfaces support only a single protocol for communicating with the external storage device, while the external bus communication protocol of some embodiments of the present application supports multiple data communication protocols (for example, these data communication protocols include a slow protocol and a fast protocol), and by supporting multiple protocols, the technical solution of the present application can meet the needs of data communication in different scenarios. In practical application of the related art chip, due to differences of different circuit boards, establishment and holding time required for data transmission are different, a fixed data transmission protocol may not meet the requirements of some application scenarios, and in some embodiments of the present application, the problem may be optimized and solved by using a dynamically configurable external bus read-write timing sequence.
Referring to fig. 2, fig. 2 is a block diagram of a system, which at least includes the apparatus 10 for on-chip external bus communication, an external memory device 300 and an external host 400 according to an embodiment of the present application.
As shown in fig. 2, some embodiments of the present application provide an apparatus 10 for on-chip external bus communication, comprising: an external bus interface 200.
The external bus interface 200 includes a first external bus protocol module (corresponding to the slow protocol module of fig. 2) and a second external bus protocol module (corresponding to the fast protocol module of fig. 2), wherein the first external bus protocol module can complete the dynamic configuration of setup, active, and hold included in the valid chip select information, and the second external bus protocol module can complete the dynamic configuration of controlling the delay between the address signal and the data signal.
The slow protocol module and the fast protocol module are exemplarily set forth below.
Compared with the prior art, some embodiments of the present application add a multifunctional external bus protocol (i.e. a slow protocol and a fast protocol) to the external bus interface module, support device accesses with different rates, and improve the external bus protocol accordingly in order to solve the needs of different chip setup and hold times in different applications.
The slow protocol is illustratively described below in conjunction with the timing diagram of fig. 3.
The slow protocol of the embodiment of the application supports setup active and hold cycle time dynamics are available. By configuring the setting of the three parameters, the requirements of different establishing and maintaining time of required data transmission under different application scenes can be solved.
As shown in fig. 3, when data transfer is performed, the active chip select signal MS _ n is first set and address and data signals are issued. According to the configuration parameter of setup, as setup =1 in fig. 3, the read/write control signal is valid after 1 cycle. Active =3 in fig. 3, when the active period lasts 3 clock cycles, by judging the ready signal ready, if it is 1, data can be normally written and read back. In fig. 3, the ready signal is low, which indicates that the current active needs to continue, otherwise the data cannot be written out or read back normally; when data can be written out normally or read back, ready is changed into high level, at this time, the data active period is ended, and the read-write control signal is pulled up to be in an invalid state. Entering a hold period, for example, according to the hold value, in fig. 3, hold =1, the data and the address last for one period, and the whole data transmission can be ended.
The meaning of each signal related to fig. 3 is as follows:
clk characterizes the data transfer clock.
MS _ n characterizes the memory cell chip select signal, e.g., active low.
WR _ n characterizes the write operation signal, e.g., active low.
RD _ n indicates a read operation signal, e.g. active low
ADDR represents the access address.
DATA characterizes the DATA signal.
READY characterizes the data transfer handshake signal.
The difference between the protocol in fig. 3 and the existing protocol is that a ready signal is added to the slow protocol in fig. 3, and handshaking between the master device and the slave device is realized through the ready signal, so that reliability of data transmission is ensured.
It can be understood that, the ready signal ready of some embodiments of the present application is an input signal (an input signal sent by an external storage device to an external bus interface), which may extend a data transmission period of an active, and solve a problem that data cannot be processed in time during data transmission. Such as: when reading data, when reading address reading data and cannot return in time, the period of data access is prolonged through a ready signal, the ready signal is effectively pulled up after the data is prepared, and the main equipment reads the data back through judging that the ready signal is effective.
The fast protocol is exemplarily described below in connection with the timing diagram of fig. 4. It should be noted that the specific meanings of the signals in fig. 4 are the same as those of the signals in fig. 3, and are not described herein for avoiding redundancy. The difference from the existing protocol is that in the fast protocol in fig. 4, a ready signal is added, and handshaking between master and slave devices is realized through the ready signal, so that reliability of data transmission is ensured.
The fast protocol of some embodiments of the present application supports control and data period delay provisioning. By configuring the value of delay, the delay between the output control address signal and the data signal can be controlled. The function can solve the problems of event establishment and insufficient holding time in rapid data transmission. Meanwhile, the function of data ready is supported, the use of different devices is met, the rapid protocol can continuously send out addresses, and the data continuously return to the function.
In fig. 4, delay =2 in the fast protocol, i.e., the delay between the control signal (MS _ n, WR _ n/RD _ n) and the address signal (ADDR), and the DATA signal (DATA) is set to 2 periods. The fast data is transmitted by a plurality of data, when a ready signal is pulled down (namely, the address is addr3/data 1) in the transmission process, the address and the data need to be kept, and the next address and data operation can be carried out after the ready signal is pulled up.
It will be appreciated that in some embodiments of the present application, an arbiter may be required if there are multiple devices sharing the same external bus. The arbiter provided by some embodiments of the present application is illustratively set forth below.
As shown in fig. 2, in some embodiments of the present application, the apparatus 10 for on-chip external bus communication further comprises: an arbiter 100, the arbiter 100 being connected to an input of the external bus interface 200, the arbiter 100 being configured to determine a target device from the plurality of on-chip devices that may use the external bus.
For example, in some embodiments of the present application, an arbiter is provided with: an input interface for receiving external bus use requests of various devices, a kernel access lock signal input interface, a DMA access lock signal input interface and a maximum transmittable data amount input interface for outputting external bus use request response signals for various devices, wherein data transmission instructions from the target device can be screened out by the request response signals.
That is, some embodiments of the present application provide an arbiter for an on-chip external bus, as compared to the prior art.
As shown in fig. 5, the input and output signals of the arbiter 100 are as follows.
core _ lock, each core can lock the external bus by accessing a lock signal, the core which obtains the external bus can enable the lock function, and the core which does not obtain the external bus right can not be locked.
cbr the kernel applies for external bus signals and requests for external bus usage.
cbg the kernel obtains the answer signal of the external bus right of use.
DMA lock signals, each DMA channel can lock the external bus, the DMA obtaining the external bus can enable the lock function, and the external bus right is not obtained and cannot be locked.
dbr, DMA applies for external bus signal and applies for external bus use request.
dbg, DMA obtains the answer signal of the external bus use right.
br: the common device applies for an external bus permission signal.
bg, the common device obtains the external bus using right response signal.
And the hbr is used for applying an external bus right signal by the external host.
hbg the external host obtains the external bus usage right signal.
bmax is the maximum data quantity which can be transmitted by the external bus right-using equipment when a plurality of same priority equipment applies for the external bus.
The arbitration process of the arbiter is exemplarily set forth below.
The specific implementation process of the arbiter is as follows: when there are multiple processor cores, multiple DMA host channels, and multiple master devices in the system that can initiate access to external devices. The usage rights of the external bus are assigned using the following arbitration mechanism.
As shown in fig. 6, when the host applies for the external bus, if the external bus is not locked (core _ Lock or dma _ Lock), trans _ finish is given to the external host when the current data transmission is completed, and the external bus is not released when the external bus Lock.
And the kernel access is used as a second priority, and when no external bus applies and a plurality of kernels access the external bus, the authority of bus access is distributed in a polling mode, and the kernels are polled from the kernel 1 to the kernel n in sequence. The core access can interrupt normal DMA accesses and cannot interrupt DMA locked data accesses of the external bus DMA lock.
DMA access as a third priority, the same DMA uses a polling mechanism (as shown in fig. 7) for data transfer, and the DMA can interrupt the normal data transfer.
Other accesses serve as a fourth priority, and a polling mechanism is also used for data transmission under the same priority.
The maximum external bus data transfer bmax defines the maximum number of data that can be transferred by the bus that each master obtains with the same priority. When the maximum number of transmissions is reached, bus permission needs to be given to the next master with the same priority.
When the kernel and the DMA carry out data transmission, the external bus usage right can be occupied for a long time in a mode of external bus locking. The design is mainly used for solving the problem of atomic operation and ensuring the consistency of required data. For example, when a kernel calculates, data is stored in an external device, and the data needs to be used in the next calculation, so that when the data which is not expected to be stored is changed before the next calculation, the core _ lock needs to be enabled, the external bus is locked, and other devices and the external host are not allowed to use the external bus. After the data is read back from the external memory unit when the next calculation is performed, the core _ lock is released and normal bus arbitration is performed. The DMA lock bus also has the same function. Whereas a normal external bus does not have this function.
A host bus application mechanism is added to the external bus, and the purpose that the external host uses the common storage device can be met. The external host obtains the use right of the external bus by applying for using the external bus, and can access the external storage device.
Fig. 7 shows the sequential decision of the same priority arbitration.
Arbitration of the same priority is performed by round robin arbitration. Br1 in fig. 7 is a bus application of the processor, br2 is a bus application of the processor 2, br3 is a bus application of the processor 3, and the processor ID = X indicates that the bus application signal is brX.
At system power-up start, default processor ID =0 has the highest priority. The priority order polls sequentially from low to high.
As shown in fig. 7, three processor devices with ID =1/2/3 at the same time apply for a bus through br1, br2, br 3. br1 has the highest priority, and br2 can only obtain the bus when br1 relinquishes the bus, and br3 can only obtain the bus usage right when br2 relinquishes the bus.
FIG. 8 shows the arbitration mechanism for the core, DMA, and general access request bus.
When br applies for the bus at the time of normal access, the normal access acquires the bus use right bg as high.
The dbr and cbr bus request signals are generated when DMA and core accesses occur. cbr has a higher priority than dbr than normal access and therefore disrupts normal data transmission. When the current data is transmitted in the ordinary transmission, the bus is abandoned to be used for the kernel, namely cbg is pulled high, bg is lowered.
When the kernel finishes accessing and abandons the bus cbr =0, the bus usage right is given to the DMA, namely dbg is pulled high, because the DMA is applying the bus with higher priority than the ordinary transmission. After the DMA data transfer bus relinquishes the bus, the bus usage right is again given high to the normal transfer bg.
The following exemplifies a method of on-chip external bus communication implemented based on the above-described apparatus for on-chip external bus communication.
As shown in fig. 9, an embodiment of the present application provides a method for on-chip external bus communication, where the method includes: s101, receiving a data transmission instruction from a target device on a chip, wherein the data transmission instruction is used for accessing an external storage device; s102, configuring a target read-write time sequence for an external bus, and sending the data transmission instruction to the external storage device through the external bus.
It can be understood that, on one hand, in practical application of a chip, due to differences of different circuit boards, establishment and retention times of data transmission needs are different, a fixed data transmission protocol may not meet needs of some application scenarios, and the problem can be solved by adopting the configurable timing sequence of the embodiment of the present application. On the other hand, some embodiments of the present application satisfy the needs of data communication in different scenarios by supporting multiple protocols.
In some embodiments of the present application, before performing S101, the method of on-chip external bus communication further comprises: receiving data transmission instructions of a plurality of devices on the chip, wherein one device corresponds to one data transmission instruction; assigning usage rights of the external bus to the target device of the plurality of devices according to an arbitration policy. Some embodiments of the present application ensure that multiple devices can use the same external bus in a time-sharing manner through an arbitration policy, thereby improving the use efficiency of the external bus.
In some embodiments of the present application, prior to the assigning the usage right of the external bus to the target device of the plurality of devices according to an arbitration policy, the method of on-chip external bus communication further comprises: caching the data transmission instruction of each device to obtain caching information; wherein the receiving a data transmission instruction from an on-chip target device includes: and reading a data transmission instruction corresponding to the target equipment from the cache information.
Some embodiments of the present application need to cache data transmission instructions from multiple on-chip devices first, which caches data and instructions first, and does not block the execution of other instructions of subsequent cores and DMA devices, so that the program execution is more efficient.
In some embodiments of the present application, the types of devices include at least: an external host, a kernel, a DMA, and other devices, wherein the arbitration policy comprises: the data transfer instruction from the external host belongs to a first priority, the data transfer instruction from the kernel belongs to a second priority, the data transfer instruction from the DMA belongs to a third priority, and the data transfer instruction from the other device belongs to a fourth priority. Some embodiments of the present application may ensure that important devices can preferentially use the external bus by setting different priorities for different kinds of devices.
In some embodiments of the present application, the arbitration policy further comprises: performing data transmission on a plurality of data transmission instructions under the same priority by adopting a polling mechanism; if there are several devices with the same priority applying bus, the maximum data transmission quantity of the device obtaining the bus use right is controlled by the maximum data transmission quantity value. Some embodiments of the present application guarantee that devices of the same priority class have an opportunity to use the external bus by setting the value Bmax of the maximum data transfer amount and the setting of the polling function.
In some embodiments of the present application, when the target device is a kernel or a DMA, the sending the data transfer instruction to the external storage device through an external bus includes: the external bus is used by locking the external bus. According to some embodiments of the application, when the kernel and the DMA adopt the external bus for data transmission, the use right of the external bus is occupied for a long time in a bus locking mode, and the design is mainly used for solving the problem of atomic operation and ensuring the consistency of required data.
In some embodiments of the present application, the plurality of external bus protocols includes a first external bus protocol, and the control signal corresponding to the first external bus protocol includes: the effective chip selection information comprises setup, active and hold, wherein the continuous cycle time of any parameter of the setup, the active and the hold can be dynamically configured. In the external bus of some embodiments of the present application, setup, active, and hold supported by the first external bus protocol (i.e., the slow protocol) are dynamically configurable, and the requirements of chip setup and hold times in different scenarios can be met by setting different setup and hold times.
In some embodiments of the present application, the control signal corresponding to the first external bus protocol further comprises: preparing information, wherein the preparing information is a signal from the external storage device, the preparing information for extending a cycle time corresponding to the active. Some embodiments of the application use the configurable ready information ready signal as an input signal of the external storage device to the external bus interface, which can prolong the active data transmission period and solve the problem that data cannot be processed in time during data transmission.
In some embodiments of the present application, the plurality of external bus protocols include a second external bus protocol, and the control signal corresponding to the second external bus protocol further includes a delay signal, where a value of the delay signal delay is configured to control a delay between the output control address signal and the output data signal. Some embodiments of the present application support the control and data period delay configurable by the second external bus protocol (i.e., the fast protocol), and by configuring the value of delay, the delay between the output control address signal and the output data signal can be controlled.
Some embodiments of the present application provide a chip, comprising: a plurality of external hosts, a plurality of kernels, and a plurality of DMAs; the apparatus for communicating over an on-chip external bus, wherein the plurality of external hosts, the plurality of cores, and the plurality of DMAs are coupled to an input of an arbiter included in the apparatus.
Some embodiments of the present application provide a system comprising: a plurality of external hosts, a plurality of kernels, and a plurality of DMAs; the apparatus communicating as an on-chip external bus, wherein the plurality of external hosts, the plurality of cores, and the plurality of DMAs are connected with an input of an arbiter of the apparatus; and the external storage equipment is connected with the output end of the external bus interface included by the device.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
Claims (11)
1. A method of on-chip external bus communication, the method comprising:
receiving a data transmission instruction from an on-chip target device, wherein the data transmission instruction is used for accessing an external storage device;
configuring a target read-write time sequence for an external bus, and sending the data transmission instruction to the external storage device through the external bus, wherein the external bus supports various external bus protocols;
the target device belongs to devices in an external host, a kernel, a DMA and other devices, a data transmission instruction from the external host belongs to a first priority, a data transmission instruction from the kernel belongs to a second priority, a data transmission instruction from the DMA belongs to a third priority, a polling mechanism is adopted for a plurality of data transmission instructions under the same priority to carry out data transmission, and if a plurality of devices with the same priority apply for a bus, the maximum data transmission quantity of the device obtaining the bus use right is controlled through the value of the maximum data transmission quantity.
2. The method of claim 1, wherein prior to receiving a data transfer instruction from an on-chip target device, the method further comprises:
receiving data transmission instructions of a plurality of devices on the chip, wherein one device corresponds to one data transmission instruction;
assigning usage rights of the external bus to the target device of the plurality of devices according to an arbitration policy.
3. The method of claim 2, wherein prior to said assigning usage rights of the external bus to the target device of the plurality of devices according to an arbitration policy, the method comprises: caching the data transmission instruction of each device to obtain caching information; wherein the content of the first and second substances,
the receiving of the data transmission instruction from the target device on the chip includes:
and reading a data transmission instruction corresponding to the target equipment from the cache information.
4. The method of claim 1, wherein the target device is a kernel or DMA, wherein,
the sending the data transmission instruction to the external storage device through the external bus includes: the external bus is used by locking the external bus.
5. The method of claim 4, wherein the plurality of external bus protocols includes a first external bus protocol, the control signals corresponding to the first external bus protocol comprising: valid chip select information comprising a setup time period setup, a valid transmission period active, and a hold time period hold, wherein,
the period time lasting by any parameter of setup, active and hold can be dynamically configured.
6. The method of claim 5, wherein the control signals corresponding to the first external bus protocol further comprise: preparing information, wherein the preparing information is a signal from the external storage device, the preparing information for extending a cycle time corresponding to the active.
7. The method of any of claims 1-3 and 5, wherein the plurality of external bus protocols includes a second external bus protocol, the control signals corresponding to the second external bus protocol further including a delay signal, wherein a value of the delay signal delay is configured to control a delay between the output control address signal and the data signal.
8. An apparatus for on-chip external bus communication, the apparatus comprising:
the external bus interface comprises a first external bus protocol module and a second external bus protocol module, wherein the first external bus protocol module can complete the dynamic configuration of setup, active and hold included in the effective chip selection information, and the second external bus protocol can complete the dynamic configuration of delay between the control address signal and the data signal;
an arbiter connected to an input of the external bus interface, the arbiter configured to determine a target device that may use an external bus from among a plurality of on-chip devices, wherein the target device belongs to one of an external host, a kernel, a DMA, or other devices;
the arbiter is further configured to control the maximum amount of data that can be transmitted by the device that obtains the bus usage right through the maximum amount of data transmission when there are a plurality of devices with the same priority applying for the bus, and the arbiter is further configured to control the amount of data that can be transmitted by the device that obtains the bus usage right through the maximum amount of data transmission when the data transmission command from the external host belongs to the first priority, the data transmission command from the kernel belongs to the second priority, the data transmission command from the DMA belongs to the third priority, and the data transmission is performed by using a polling mechanism for a plurality of data transmission commands with the same priority.
9. The apparatus of claim 8, wherein the arbiter is provided with: the device comprises an input interface for receiving external bus use requests of various devices, a kernel access locking signal input interface, a DMA access locking signal input interface and a maximum transferable data quantity input interface, and is used for outputting external bus use request response signals aiming at various devices.
10. A chip, wherein the chip comprises: a plurality of external hosts, a plurality of kernels, and a plurality of DMAs;
the apparatus of any of claims 8-9, wherein the plurality of external hosts, the plurality of cores, and the plurality of DMAs are coupled to an input of an arbiter included with the apparatus.
11. A system, characterized in that the system comprises:
a plurality of external hosts, a plurality of kernels, and a plurality of DMAs;
the apparatus of any of claims 8-9, wherein the plurality of external hosts, the plurality of cores, and the plurality of DMAs are connected to an input of an arbiter of the apparatus;
and the external storage equipment is connected with the output end of the external bus interface included by the device.
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