CN105260331B - A kind of dual bus Memory Controller Hub - Google Patents
A kind of dual bus Memory Controller Hub Download PDFInfo
- Publication number
- CN105260331B CN105260331B CN201510647939.1A CN201510647939A CN105260331B CN 105260331 B CN105260331 B CN 105260331B CN 201510647939 A CN201510647939 A CN 201510647939A CN 105260331 B CN105260331 B CN 105260331B
- Authority
- CN
- China
- Prior art keywords
- axi
- dfi
- bus
- request
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The present invention provides a kind of dual bus Memory Controller Hub, including PLB bus bridge circuits, AXI bus bridge circuits, DFI bus arbitrating circuits and Memory Controller Hub kernel, the PLB bus bridge circuits receive the access request of PLB buses, and convert the request into the request of DFI bus standards；The AXI bus bridge circuits receive the access request of AXI buses, and convert the request into the request of DFI bus standards；The DFI bus arbitrating circuits receive the DFI bus standards request of PLB bus bridge circuits and the output of AXI bus bridge circuits, and after arbitrated logic, the request of DFI bus standards is sent to Memory Controller Hub kernel MCP.Two kinds of bus standards of the present invention couple separately design bus bridge logic, i.e., outside access request are converted to Memory Controller Hub inter access request；The expense at least reducing the conversion of a bus protocol, to obtain higher internal storage access efficiency；And Memory Controller Hub core logic need not then make any modification.
Description
Technical field
The invention belongs to computer chip design fields, more particularly, to a kind of dual bus Memory Controller Hub.
Background technology
In modem computer systems, memory has been essential CPU peripheral equipments, has high exterior data
Defeated rate and advanced address/command and controlling bus topological structure.Memory Controller Hub is also widely used in various electronics productions therewith
In the acp chip of product, Memory Controller Hub be inside computer system control memory and by Memory Controller Hub make memory with
The important component of the swapping data of CPU.Memory Controller Hub determines the internal memory performance of computer system..
The Memory Controller Hub of mainstream usually only supports a kind of standard bus interface at present, and is passed through in current high speed information system
It often has the IP of different bus interface while needing access memory, IP kernel especially with AMBA AXI buses and with PLB
The IP kernel of bus is widely used in the system.
In order to meet requirements for access of this complication system to memory, a kind of simple way is outside Memory Controller Hub
Using various bus protocol Bridges, i.e., a variety of different buses are transformed into Memory Controller Hub support by bridging logic
External Bus Interface standards.This design needs bus standard conversion at least twice, and conversion is by a certain bus mark for the first time
Standard is converted into the external bus standard of Memory Controller Hub support；Second of conversion is the visit for receiving outside inside Memory Controller Hub
Ask that request is converted into internal access request.Excessive bus standard conversion can seriously reduce internal storage access efficiency, lead to bus
Congestion.
Invention content
In view of this, the present invention is directed to propose a kind of dual bus Memory Controller Hub, supports PLB4 bus interface and AMBA
The IP of AXI bus interface accesses memory simultaneously, improves internal storage access efficiency.
In order to achieve the above objectives, the technical proposal of the invention is realized in this way：
A kind of dual bus Memory Controller Hub further includes in addition to including Memory Controller Hub kernel：
PLB bus bridge circuits, the access request for receiving PLB buses, and convert the request into DFI bus standards and ask
It asks；
AXI bus bridge circuits, the access request for receiving AXI buses, and convert the request into DFI bus standards and ask
It asks；
DFI bus arbitrating circuits, the DFI buses for receiving PLB bus bridge circuits and the output of AXI bus bridge circuits
The request of DFI bus standards is sent to Memory Controller Hub kernel by standard request after arbitrated logic.
Further, the PLB bus bridge circuits include：
Command decoder logic, the order from PLB buses for being used for receive and address are into row decoding；
Request queue is transmitted, for caching the read-write requests for meeting PLB bus protocols after decoding；
PLB reads data Buffer and PLB and writes data Buffer, buffers and transmits between PLB buses and DFI interfaces respectively
Read and write data；
Write control logic and reading control logic are respectively used to management PLB according to the information in transmission request queue and write data
Buffer and PLB reads data Buffer；
DFI primary modules one will write the request queue of data Buffer respectively from transmission request queue and PLB and write data
It is sent to DFI interfaces according to the timing requirements of DFI bus standards；The reading data that DFI primary modules one also return to DFI interfaces are sent into
PLB is read in data Buffer.
Further, the AXI bus bridge circuits include：
Read/write requests queue, for caching the read-write requests for meeting AXI bus protocols；
Queue management logic handles the response of DFI interfaces for managing load and the uninstall process of read/write requests queue
And handshake；
AXI write address control logics are responsible for AXI bus standard write requests being converted to DFI standard write requests, and are added to
Read/write requests queue, while being also responsible for carrying out address decoding and generating AXI write addresses channel handshake；
AXI reads address control logic, is responsible for AXI bus standard read requests being converted to DFI standard read requests, and be added to
Read/write requests queue, while being also responsible for carrying out address decoding and generating AXI reading address tunnel handshake；
AXI reads data Buffer and AXI and writes data Buffer, buffers and transmits between AXI buses and DFI interfaces respectively
Read and write data；
AXI writes data control logic, and data Buffer is write for managing AXI, is responsible for generating AXI write data channels and shake hands letter
Number, merging data transmits width and is less than the data of 128Bit, and is interleaved write operation according to AWID signals；
AXI reads data control logic, reads data Buffer for managing AXI, generates AXI and read data channel handshake,
When the data transfer width of AXI read requests is less than 128Bit, the 128Bit data from DFI interfaces are split；
Exclusive monitoring logics, for monitor AXI write addresses control logic and AXI read address control logic AXI it is total
Monitoring information is transmitted to AXI write address control logics, generates answer signal by the Exclusive access address of line；When
When Exclusive accesses failure, write request is prevented to enter DFI interfaces.
DFI primary modules two write number by what data Buffer was write in the request queue of the read/write requests queue received and AXI
It is sent to DFI interfaces according to according to the timing requirements of DFI bus standards；The reading data of return are sent into AXI and read data by DFI primary modules two
Buffer。
Further, the DFI bus arbitrating circuits include DFI orders FIFO and arbitrated logic, and the arbitrated logic makes
The request of which DFI interface is selected to enter Memory Controller Hub kernel with the mode of robin scheduling algorithm or fixed priority.
Compared with the existing technology, the present invention has the advantage that：
Bus bridge logic is separately designed to two kinds of bus standards, PLB bus protocols and AXI bus protocols are converted respectively
For Memory Controller Hub bus protocol, i.e., outside access request is converted into Memory Controller Hub inter access request；It at least reduces
The expense of bus protocol conversion, to obtain higher internal storage access efficiency；And Memory Controller Hub core logic is then not required to
Any modification is made, the compatibility of original Memory Controller Hub is remained；
The control to internal storage location is obtained by arbitrated logic again, the arbitrated logic of optimization will can be chosen without delay
DFI interface standards request be sent into Memory Controller Hub, access efficiency is almost without loss；
The design has flexibility, scalability and durability, has wide practical use in high speed information system.
Description of the drawings
The attached drawing for constituting the part of the present invention is used to provide further understanding of the present invention, schematic reality of the invention
Example and its explanation are applied for explaining the present invention, is not constituted improper limitations of the present invention.In the accompanying drawings：
Fig. 1 is the overall structure functional block diagram of dual bus Memory Controller Hub described in the embodiment of the present invention；
Fig. 2 is the schematic diagram of PLB bus bridge circuits described in the embodiment of the present invention；
Fig. 3 is the schematic diagram of AXI bus bridge circuits described in the embodiment of the present invention；
Fig. 4 is the schematic diagram of bus arbitrating circuit described in the embodiment of the present invention.
Specific implementation mode
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The DFI being previously mentioned in the present invention refers to DDR PHY Interface.
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
A kind of dual bus Memory Controller Hub, as shown in Figure 1, including PLB bus bridge circuits 101, AXI bus bridge circuits
102, DFI bus arbitrating circuits 103 and Memory Controller Hub kernel MCP, the PLB bus bridge circuits 101 receive PLB buses
Access request, and convert the request into the request of DFI bus standards；The AXI bus bridge circuits 102 receive the visit of AXI buses
It asks request, and converts the request into the request of DFI bus standards；The DFI bus arbitrating circuits 103 receive PLB bus bridge electricity
The DFI bus standards request that road 101 and AXI bus bridge circuits 102 export, after arbitrated logic, DFI bus standards are asked
It asks and is sent to Memory Controller Hub kernel MCP.Suitable for having the SoC systems of PLB buses and AMBAAXI buses simultaneously.
As shown in Fig. 2, the PLB bus bridge circuits 101 include command decoder logic 201, request queue 202 is transmitted,
PLB writes data Buffer203, write control logic 204, and PLB reads data Buffer206, reads control logic 205 and DFI primary modules
One 207；
Order from PLB buses that the command decoder logic 201 is used for receive and address are into row decoding；The biography
Defeated request queue 202 is used to cache the read-write requests for meeting PLB bus protocols after decoding, realizes that delay is write, read request sorts
With the functions such as read-after-write；The write control logic 204 and reading control logic 205, according to the information point in transmission request queue 202
PLB Yong Yu not managed and write data Buffer203 and PLB reading data Buffer206；PLB reads data Buffer206 and PLB and writes number
Read-write data are buffered and transmitted respectively between PLB buses and DFI interfaces according to Buffer203, use independent read/write Buffer
Simultaneous read-write can be supported to transmit, to improve transmission bandwidth.The DFI primary modules 1 come respectively by what is received
The request queue of data Buffer203 is write from transmission request queue 202 and PLB and writes sequential of the data according to DFI bus standards
It is required that being sent to DFI interfaces；The reading data that DFI primary modules 1 return to DFI interfaces are sent into PLB and are read in data Buffer206.
Wherein, for the address decoding range of the command decoder logic 201 by software configuration, the address beyond decoding range will
Order decoding logic 201 can be made to generate wrong responses signal O_S_ERR in PLB buses.Asking within the scope of address decoding
It asks, command decoder logic 201 will generate effectively O_S_PVAL signals in PLB buses.If the bus request from PLB goes out
Parity error (Parity Error) is showed, command decoder logic 201 will not generate effective O_S_PVAL signals.Such as
Fruit transmits request queue 202 or PLB readings data Buffer206 or PLB write data Buffer203 and expired, then command decoder logic
201 generate O_S_PRETRY signals.
Each corresponding read request, PLB read that in data Buffer206 128 bytes can be distributed.PLB bus read requests according to
Sequence into PLB bus bridge circuits 101 appears on DFI interfaces.Each corresponding write request, PLB write data
128 bytes can be distributed in Buffer203.To appear in DFI total according to the sequence for entering PLB bus bridge circuits 101 for PLB write requests
On line.Software can configure a threshold value, when the write request quantity in Pending states be more than the threshold value, afterwards enter PLB it is total
The read request of line bridgt circuit 101 can preferentially appear in DFI interfaces, precondition be read request address without and Pending shapes
The write request address of state clashes.
As shown in figure 3, the AXI bus bridge circuits 102 include queue management logic 301, AXI writes data control logic
302, AXI write data Buffer303, AXI write address control logic 304, Exclusive monitoring logics 305, and AXI reads address control
Logic 306 processed, AXI read data control logic 307, and AXI reads data Buffer308, read/write requests queue 309 and DFI primary modules
2 310；
The read/write requests queue 309 is used to cache the read-write requests for meeting AXI bus protocols.The queue pipe
Reason logic 301 is used for managing load (transmission request) and unloading (end of transmission) process of read/write requests queue 309, handles DFI
The response of interface and handshake；The addresses DFI/control logic is also contained in queue management logic 301 simultaneously, it is responsible for monitoring
Quene state.
The AXI write addresses control logic 304 is responsible for AXI bus standard write requests being converted to DFI standard write requests,
And it is added to read/write requests queue 309, while being also responsible for carrying out address decoding and generating AXI write addresses channel handshake；Institute
State AXI and read address control logic 306, be responsible for AXI bus standard read requests being converted to DFI standard read requests, and be added to reading/
Write request queue 309, while being also responsible for carrying out address decoding and generating AXI reading address tunnel handshake；
The AXI reads data Buffer308 and AXI and writes data Buffer303, respectively between AXI buses and DFI interfaces
Buffering and transmission read-write data.The AXI writes data control logic 302, and data Buffer303 is write for managing AXI, is responsible for production
Raw AXI write data channel handshake, merging data transmits width and is less than the data of 128Bit, and is handed over according to AWID signals
Knit write operation.The AXI reads data control logic 307, and data Buffer308 is read for managing AXI, and it is logical to generate AXI reading data
Road handshake splits the 128Bit data from DFI interfaces when the data transfer width of AXI read requests is less than 128Bit.
The Exclusive monitoring logics 305 read address control for monitoring AXI write addresses control logic 304 and AXI
Monitoring information is transmitted to AXI write addresses control logic (304) by the Exclusive access address of the AXI buses of logic 306, production
Raw answer signal；When Exclusive accesses failure, write request is prevented to enter DFI interfaces.
The request queue of the read/write requests queue 309 received and AXI are write data by the DFI primary modules 2 310
The data of writing of Buffer303 are sent to DFI interfaces according to the timing requirements of DFI bus standards；DFI primary modules 2 310 are by return
It reads data and is sent into AXI reading data Buffer308.
As shown in figure 4, the DFI bus arbitrating circuits 103 include DFI orders FIFO (401) and arbitrated logic 402, institute
State mode of the arbitrated logic 402 using robin scheduling algorithm (round-robin) or fixed priority (fixed-priority)
The request of which DFI interface is selected to enter Memory Controller Hub kernel MCP, wherein can be matched by software using any arbitration mode
It sets.
After DFI primary modules send out request all the way, if sending out request without other primary modules or there is no higher priority
DFI primary modules send out request, then the DFI primary modules are selected obtains the right for accessing memory.If multiple DFI primary modules are same
When send out request, for arbitrated logic 402 by according to the mode of priority, that road request of choosing then highest priority enters Memory control
Device kernel (MCP).
Normal DFI requests need operation to be performed to be divided into two stages：Command phase and data phase；If one
A order from DFI primary modules cannot get response, which cannot propagate into data phase.In order to support back-to-back
(back-to-back) transmission mode, to devise a DFI orders FIFO (401) per DFI interfaces primary module all the way, once
The outstanding requests of DFI orders FIFO (401) are more than its depth capacity, cannot receive new request again.
The arbitrated logic 402 selects that ask to enter Memory Controller Hub kernel all the way using MUX and De-MUX logics
Which road DFI interface primary module the data of MCP and Memory Controller Hub kernel MCP return to.
The present invention is realized the access request from PLB buses and the access request from AXI buses respectively using bridge joint
Logic becomes the DFI interface standards used inside Memory Controller Hub kernel MCP request, after DFI interface arbitration logics, enters
Memory Controller Hub kernel MCP；The expense that the conversion of a bus protocol can at least be reduced, to obtain higher internal storage access effect
Rate, and Memory Controller Hub core logic need not then make any modification.The design has flexibility, scalability and multiplexing
Property, have wide practical use in high speed information system.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention god.
Claims (3)
1. a kind of dual bus Memory Controller Hub, including Memory Controller Hub kernel, it is characterised in that further include：
PLB bus bridge circuits (101), the access request for receiving PLB buses, and convert the request into DFI bus standards
Request；
AXI bus bridge circuits (102), the access request for receiving AXI buses, and convert the request into DFI bus standards
Request；
DFI bus arbitrating circuits (103), it is defeated for receiving PLB bus bridge circuits (101) and AXI bus bridge circuits (102)
The request of DFI bus standards is sent to Memory Controller Hub kernel by the DFI bus standards request gone out after arbitrated logic；
The PLB bus bridge circuits (101) include：
Command decoder logic (201), the order from PLB buses for being used for receive and address are into row decoding；
Request queue (202) is transmitted, for caching the read-write requests for meeting PLB bus protocols after decoding；
PLB reads data Buffer (206) and PLB writes data Buffer (203), is buffered between PLB buses and DFI interfaces respectively
Data are read and write with transmission；
Write control logic (204) and reading control logic (205) are respectively used to pipe according to the information in transmission request queue (202)
Reason PLB writes data Buffer (203) and PLB and reads data Buffer (206)；
DFI primary modules one (207) will write the request of (203) data Buffer respectively from transmission request queue (202) and PLB
It queue and writes data and is sent to DFI interfaces according to the timing requirements of DFI bus standards；DFI primary modules one (207) are also by DFI interfaces
The reading data of return are sent into PLB and are read in data Buffer (206).
2. dual bus Memory Controller Hub according to claim 1, it is characterised in that the AXI bus bridge circuits (102)
Including：
Read/write requests queue (309), for caching the read-write requests for meeting AXI bus protocols；
Queue management logic (301) handles DFI interfaces for managing load and the uninstall process of read/write requests queue (309)
Response and handshake；
AXI write addresses control logic (304) is responsible for AXI bus standard write requests being converted to DFI standard write requests, and is added
To read/write requests queue (309), while being also responsible for carrying out address decoding and generating AXI write addresses channel handshake；
AXI reads address control logic (306), is responsible for AXI bus standard read requests being converted to DFI standard read requests, and be added
To read/write requests queue (309), while being also responsible for carrying out address decoding and generating AXI reading address tunnel handshake；
AXI reads data Buffer (308) and AXI writes data Buffer (303), is buffered between AXI buses and DFI interfaces respectively
Data are read and write with transmission；
AXI writes data control logic (302), and data Buffer (303) is write for managing AXI, is responsible for generating AXI write data channels
Handshake, merging data transmits width and is less than the data of 128Bit, and is interleaved write operation according to AWID signals；
AXI reads data control logic (307), and data Buffer (308) is read for managing AXI, generates AXI readings data channel and shakes hands
Signal splits the 128Bit data from DFI interfaces when the data transfer width of AXI read requests is less than 128Bit；
Exclusive monitoring logics (305) read address control logic for monitoring AXI write addresses control logic (304) and AXI
(306) monitoring information is transmitted to AXI write addresses control logic (304) by the Exclusive access address of AXI buses, is generated
Answer signal；When Exclusive accesses failure, write request is prevented to enter DFI interfaces；
The request queue of the read/write requests queue (309) received and AXI are write data Buffer by DFI primary modules two (310)
(303) data of writing are sent to DFI interfaces according to the timing requirements of DFI bus standards；DFI primary modules two (310) are by the reading of return
Data are sent into AXI and read data Buffer (308).
3. dual bus Memory Controller Hub according to claim 1, it is characterised in that：The DFI bus arbitrating circuits (103)
Including DFI orders FIFO (401) and arbitrated logic (402), the arbitrated logic (402) is excellent using robin scheduling algorithm or fixation
The mode of first grade selects the request of which DFI interface to enter Memory Controller Hub kernel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510647939.1A CN105260331B (en) | 2015-10-09 | 2015-10-09 | A kind of dual bus Memory Controller Hub |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510647939.1A CN105260331B (en) | 2015-10-09 | 2015-10-09 | A kind of dual bus Memory Controller Hub |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105260331A CN105260331A (en) | 2016-01-20 |
| CN105260331B true CN105260331B (en) | 2018-08-28 |
Family
ID=55100029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510647939.1A Active CN105260331B (en) | 2015-10-09 | 2015-10-09 | A kind of dual bus Memory Controller Hub |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105260331B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109690511B (en) * | 2016-08-31 | 2023-05-02 | 株式会社索思未来 | Bus control circuit, semiconductor integrated circuit, circuit board, information processing device, and bus control method |
| CN106484531B (en) * | 2016-09-18 | 2019-12-24 | 上海顺久电子科技有限公司 | Memory access arbitration method, circuit and device |
| CN109840225B (en) * | 2017-11-27 | 2023-06-09 | 中国航空工业集团公司西安航空计算技术研究所 | Control circuit for accessing eFPGA by heterogeneous dual-core processor |
| CN108255769B (en) * | 2017-12-06 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | AXI-PLB bridge |
| CN111402940B (en) * | 2020-03-12 | 2023-05-30 | 中国电子科技集团公司第三十八研究所 | SRAM storage device and method based on SRIO protocol |
| CN111475437A (en) * | 2020-04-14 | 2020-07-31 | 深圳忆联信息系统有限公司 | DDR (double data Rate) verification device and method for SOC (System on chip) chip FPGA prototype of solid state disk, computer equipment and storage medium |
| CN112035389B (en) * | 2020-08-28 | 2022-08-23 | 西安微电子技术研究所 | PLB-AXI bus conversion bridge and working method thereof |
| CN112650697B (en) * | 2020-12-24 | 2023-04-18 | 西安翔腾微电子科技有限公司 | Arbitration circuit of multiple main devices based on DDR3 storage controller interface |
| CN113033133B (en) * | 2021-03-17 | 2023-03-28 | 烽火通信科技股份有限公司 | Logic multiplexing circuit design method and circuit structure |
| CN114281722B (en) * | 2021-12-29 | 2024-04-05 | 合肥市芯海电子科技有限公司 | Embedded control circuit with double bus interfaces, chip and electronic equipment |
| CN114741341A (en) * | 2022-03-01 | 2022-07-12 | 西安电子科技大学 | Method, system and storage medium for realizing Crossbar structure arbitration |
| CN115017093B (en) * | 2022-05-06 | 2023-03-24 | 北京中科昊芯科技有限公司 | Method and device for on-chip external bus communication |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5265211A (en) * | 1992-01-02 | 1993-11-23 | International Business Machines Corporation | Arbitration control logic for computer system having dual bus architecture |
| CN1783044A (en) * | 2004-11-30 | 2006-06-07 | 中国科学院计算技术研究所 | On-chip system |
| CN101192208A (en) * | 2006-11-24 | 2008-06-04 | 无锡盈泰科技有限公司 | Dual bus circuit based on 8-bit processor |
| CN101196862A (en) * | 2006-12-08 | 2008-06-11 | 深圳艾科创新微电子有限公司 | Double-bus seamless self-switching method |
| CN102004709A (en) * | 2009-08-31 | 2011-04-06 | 国际商业机器公司 | Bus bridge between processor local bus (PLB) and advanced extensible interface (AXI) and mapping method |
| CN102122367A (en) * | 2010-01-07 | 2011-07-13 | 上海华虹集成电路有限责任公司 | High-capacity SIM card system architecture |
| CN102880143A (en) * | 2012-09-27 | 2013-01-16 | 中国船舶重工集团公司第七一九研究所 | Single control area network (CAN) controller hot-redundant CAN bus system and implementation method thereof |
| CN103440171A (en) * | 2013-08-25 | 2013-12-11 | 浙江大学 | Realization method of real-time operating system of component-based hardware |
| CN104699641A (en) * | 2015-03-20 | 2015-06-10 | 浪潮集团有限公司 | EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7475176B2 (en) * | 2006-01-31 | 2009-01-06 | Broadcom Corporation | High bandwidth split bus |
-
2015
- 2015-10-09 CN CN201510647939.1A patent/CN105260331B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5265211A (en) * | 1992-01-02 | 1993-11-23 | International Business Machines Corporation | Arbitration control logic for computer system having dual bus architecture |
| CN1783044A (en) * | 2004-11-30 | 2006-06-07 | 中国科学院计算技术研究所 | On-chip system |
| CN101192208A (en) * | 2006-11-24 | 2008-06-04 | 无锡盈泰科技有限公司 | Dual bus circuit based on 8-bit processor |
| CN101196862A (en) * | 2006-12-08 | 2008-06-11 | 深圳艾科创新微电子有限公司 | Double-bus seamless self-switching method |
| CN102004709A (en) * | 2009-08-31 | 2011-04-06 | 国际商业机器公司 | Bus bridge between processor local bus (PLB) and advanced extensible interface (AXI) and mapping method |
| CN102122367A (en) * | 2010-01-07 | 2011-07-13 | 上海华虹集成电路有限责任公司 | High-capacity SIM card system architecture |
| CN102880143A (en) * | 2012-09-27 | 2013-01-16 | 中国船舶重工集团公司第七一九研究所 | Single control area network (CAN) controller hot-redundant CAN bus system and implementation method thereof |
| CN103440171A (en) * | 2013-08-25 | 2013-12-11 | 浙江大学 | Realization method of real-time operating system of component-based hardware |
| CN104699641A (en) * | 2015-03-20 | 2015-06-10 | 浪潮集团有限公司 | EDMA (enhanced direct memory access) controller concurrent control method in multinuclear DSP (digital signal processor) system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105260331A (en) | 2016-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105260331B (en) | A kind of dual bus Memory Controller Hub | |
| US6119196A (en) | System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates | |
| JP4878185B2 (en) | Data communication circuit and arbitration method | |
| US6052738A (en) | Method and apparatus in a packet routing switch for controlling access at different data rates to a shared memory | |
| CN101504633B (en) | Multi-channel DMA controller | |
| US8924612B2 (en) | Apparatus and method for providing a bidirectional communications link between a master device and a slave device | |
| WO2011089660A1 (en) | Bus arbitration device | |
| US20050289268A1 (en) | Internal bus system | |
| KR20080069272A (en) | Memory system with both single and consolidated commands | |
| US6801971B1 (en) | Method and system for shared bus access | |
| CN115248796B (en) | Bus pipeline structure and chip for core-to-core interconnection | |
| KR20030084974A (en) | Buffer network for correcting fluctuations in a parallel/serial interface | |
| US10942878B1 (en) | Chunking for burst read transactions | |
| US20200117626A1 (en) | Split direct memory access (dma) | |
| CN107852423B (en) | Method and system for USB2.0 bandwidth reservation | |
| US6532511B1 (en) | Asochronous centralized multi-channel DMA controller | |
| US6202116B1 (en) | Write only bus with whole and half bus mode operation | |
| US20120117286A1 (en) | Interface Devices And Systems Including The Same | |
| US7185128B1 (en) | System and method for machine specific register addressing in external devices | |
| JP4777723B2 (en) | Information processing system, program, and data transfer method | |
| CN204515761U (en) | SOC (system on a chip) | |
| JP2006092286A (en) | Data transfer device and image forming system | |
| US7426596B2 (en) | Integrated circuit with a scalable high-bandwidth architecture | |
| KR100475438B1 (en) | Data bus system and method for performing cross-access between buses | |
| CN114641764A (en) | Bus system and method for operating a bus system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |