CN1783044A

CN1783044A - On-chip system

Info

Publication number: CN1783044A
Application number: CN 200410096178
Authority: CN
Inventors: 刘新春; 张佩珩; 江先阳; 李晓民; 孙凝晖
Original assignee: Institute of Computing Technology of CAS
Current assignee: Dawning Information Industry Co Ltd
Priority date: 2004-11-30
Filing date: 2004-11-30
Publication date: 2006-06-07
Anticipated expiration: 2024-11-30
Also published as: CN100485648C

Abstract

The on-chip system includes several functional modules connected with internal bus including two independent transmission channels, including one control/state channel for transmitting control/state information and one data channel for transmitting other data except control/state information. Each of the control/state channel and the data channel has separate data bus, address bus and control bus. The kernel of the present invention is to design on-chip system bus in the strategy of separate control/state channel and data channel, which have different topologic structures and communication protocols. The present invention has greatly simplified interface design of functional modules inside the system and increased total system communication bandwidth, and is especially suitable for on-chip system design with compact data interaction.

Description

System on chip

Technical Field

The present invention relates to the field of semiconductor chips, and more particularly to a system on a chip.

Background

With the development of the semiconductor technology towards deep submicron and the further improvement of EDA tools, more and more complex functional modules (usually IP modules) can be integrated inside the chip to form a complex System-on-a-chip (SoC). Generally, a large amount of data needs to be exchanged between the functional modules, and the data exchange is performed by using a communication link, so that the communication link often becomes a bottleneck of system performance. Communication links can be divided into a point-to-point mode and a bus mode depending on whether the functional modules share the communication link. The architecture of the system is based on a bus approach if the various functional modules within the system are connected using a shared communication link. Each functional module based on the bus connection mode has the same bus interface, and the formed system has a simple structure, is easy to expand and is convenient for design reuse of the functional modules. Because of these advantages of the bus architecture, current systems on chip basically employ a bus architecture.

When the system on chip of the existing bus structure is interconnected by a bus, a single-channel manner is usually adopted, that is, all functional modules use the same bus resources (including a control bus, an address bus, a data bus, and the like) to transfer various types of data.

In fact, data transferred between functional modules in the system on chip via the data bus can be divided into two categories: control \ status information and other data. The control \ status information refers to control information data and status information data for controlling the operation and status of the functional module, and is usually stored in the control register and status register inside the functional module. Therefore, the control \ state information is basically a register operation, which has low operation frequency and discontinuous addresses. The other data refers to data transmitted on a data bus except for control \ state information, the other data is transmitted very frequently, a burst transmission mode is mainly used, and the efficiency of data transmission directly influences the performance of the system.

As described above, in the system on chip adopting the single channel type bus structure, the control \ status information and other data are transmitted through the same data bus, and the same control bus and address bus are used. The bandwidth of the data bus is the maximum communication bandwidth of the whole system, if the control \ state information and other data are transmitted by using the same data bus, the data exchange between the functional modules in the system needs to be frequent, and when the maximum communication bandwidth required by the whole system exceeds the bandwidth of the data bus, the internal bus becomes a communication bottleneck. Particularly, when a plurality of functional modules compete for the same bus resource, the central arbiter only allows one functional module to use the resource each time, and other functional modules have to wait, some functional modules need to wait for a long time to obtain the right of using the bus, and the insertion of a large number of waiting cycles can prolong the running time of the system, thereby greatly reducing the performance of the system.

Therefore, there is a need for a new system-on-chip internal bus that can use different transmission channels for different types of data.

Disclosure of Invention

It is an object of the present invention to overcome the disadvantages and shortcomings of the prior art and to provide a new system on chip that employs different transmission channels for different types of data.

The system on chip provided by the invention comprises a plurality of functional modules, wherein the functional modules are connected by an internal bus, and the internal bus comprises two independent transmission channels, and comprises the following steps:

a control/status channel for transmitting control/status information; and

a data channel for transmitting data other than control/status information;

the control/status channel and the data channel each include data lines, address lines, and control lines.

The control/state channel of the system on chip is a master-slave device structure, one of the plurality of functional modules connected with the control/state channel is a master device, and the functional modules outside the master device are slave devices. The data lines of the control/status channel include: a write data line common to all slaves and a read data line between a slave and a master. The address line of the control/status channel is shared by all slave devices. The control lines of the control/status channel include: an interrupt request signal line from each slave to the master, a strobe signal line from the master to each slave, and a command signal line common to all slaves.

The data channel of the system on chip is of a master-slave device structure, and the plurality of functional modules connected with the data channel comprise at least one master device and at least one slave device; the address lines and the control lines are connected from the master device to the slave device; the data lines include separate write data lines and read data lines, the write data lines being connected from the master device to the slave device, the read data lines and slave devices being connected to the master device.

The data channel comprises a plurality of main devices, the data channel also comprises a first multiplexer and an arbiter which are associated with the main devices, the arbiter carries out arbitration operation according to address and control signals sent by the main devices and distributes the bus use rights of the main devices according to the arbitration result, and the arbiter is also connected with the first multiplexer and controls the first multiplexer to select signals from the main devices.

The data channel includes a plurality of slave devices, and a second multiplexer associated with a master device is included in the data channel, the second multiplexer selecting signals from the plurality of slave devices. The second multiplexer is connected with the arbiter, and is controlled by the arbiter to select the signals from the plurality of slave devices. The arbiter is an arbiter adopting a round robin scheduling algorithm.

The invention has the following beneficial effects:

1. the core of the invention is that the system-on-chip bus is designed by adopting a strategy of separating a control/state channel and a data channel, two channels designed according to different characteristics of two types of data in the system have different topological structures and communication protocols, the interface design of each functional module in the system can be greatly simplified, the total communication bandwidth of the system is increased, and the invention is very suitable for the design of a data interaction intensive system-on-chip.

2. The control/state channel and the data channel are separated, and the two channels use different address spaces and data lines, so that the design of an address decoding circuit can be simplified, and the compromise processing caused by the difference of two different data transmission protocols is avoided.

3. The control/state channel and the data channel of the invention adopt a master and slave handshake mode to exchange data. Because the control \ state register and other data are located in different address spaces, the control \ state register and other data can be respectively coded and decoded, and the design of the interface logic of each module is convenient to simplify.

4. The data channel of the invention uses the distributed slave device associated arbitrator, only the slave device end shared by a plurality of master devices needs to design the corresponding arbitrator, and the inside of the system allows a plurality of master device-slave device pairs to simultaneously communicate, thus the design can greatly improve the data communication bandwidth inside the system.

5. The data channel of the invention uses simple handshake protocol to complete data transmission, and allows the functional module with slow response speed to insert waiting period in the data transmission process. The design method is beneficial to the design reuse of the functional modules, and the functional modules with different performances can be conveniently integrated into one system chip.

Drawings

FIG. 1 is a schematic diagram of the overall architecture of the system-on-chip of the present invention;

FIG. 2 is a block diagram illustrating a control/status channel of the system-on-chip of the present invention;

FIG. 3 is a timing diagram illustrating a read operation of a control/status channel in the system-on-chip of the present invention;

FIG. 4 is a timing diagram illustrating write operations to a control/status channel in the system-on-chip of the present invention;

FIG. 5 is a block diagram illustrating a data path in the system-on-chip of the present invention;

FIG. 6 is a timing diagram illustrating a read operation of a data channel in the system on chip of the present invention;

FIG. 7 is a timing diagram illustrating a write operation of a data channel in the system on chip of the present invention;

FIG. 8 is a block diagram of an arbiter in a data channel of a system on a chip according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and the detailed description.

A system on chip usually includes a plurality of functional modules, each of which has a bus interface and is connected by an internal bus of the system on chip. In the embodiment of the invention shown in FIG. 1, the system on chip includes functional modules 0-5 (which can be expanded) and a console. The console is a special functional module of the system on chip, and is often served by an embedded RISC CPU or a functional module having the same or similar function as the RISC CPU. In other possible embodiments, the console may also be integrated into other functional modules. As will be appreciated from the description below, the console will act as the master in the control/status channel of the present invention.

As shown in fig. 1, in the present invention, the internal bus of the system on chip includes two independent channels: a control/status channel 10 and a data channel 20. The functional modules 0-5 and the console are connected by a control/status channel 10 and a data channel 20. The control/status channel 10 is used for transmitting control \ status information data in the system-on-chip, and the data channel 20 is used for transmitting other data besides the control \ status information data in the system-on-chip. Since the console is only used for the control/status channel 10, it is not connected to the data channel 20. For the control/status channel 10 and the data channel 20, each channel comprises data lines, address lines and control lines for transmitting respective data, which will be described in detail below.

Control/status channel

Fig. 2 shows the structure of the control/status channel of the present invention, which includes data lines, address lines and control lines of the control/status channel.

As shown in fig. 2, the control/status channel adopts a master-slave device structure, that is, data is exchanged between the functional modules in a master-slave device handshake manner. On the control/status channel, only one master device is arranged in a plurality of functional modules, and other functional modules are all slave devices. The main equipment is the console in fig. 1 and 2, and the auxiliary equipment is functional modules 0-5.

In fig. 2, address lines of the control/status channel are shown by CAddr, and are connected between the console and the functional modules 0 to 5 each serving as a slave device, and are shared by the functional modules 0 to 5 each serving as a slave device. Since the data transmitted by the control/status channel is control/status information, the operation targets are the status register and the control register inside each functional module 0-5, and therefore, an excessively wide address line is not needed. In one embodiment of the invention, the address lines CAddr of the control/status channel are 5 bits wide, and 32 registers of different addresses can be addressed. The narrow width of the address line can simplify the design difficulty of the decoding circuit and accelerate the response time of the circuit. It should be understood that the width of the address line CAddr may vary according to the actual needs of the user.

In fig. 2, the control lines of the control/status channels include: a command signal line or a read/write enable signal line CR/Wn, a gate signal line CSel, and an interrupt request signal line IRQ.

The direction of the interrupt request signal line IRQ is from each functional module 0-5 as a slave device to the console, and is used for transmitting an interrupt request signal sent from the slave device to the console. In one embodiment, the interrupt request signal is active high and is used to notify the console when a functional module 0-5 needs to perform data interaction with the console. The interrupt request signal lines between different slave devices and the console, such as IRQ _0 to IRQ _5, are distinguished in fig. 2 by underlining and the same number as the function block number added after the IRQ.

The direction of the gating signal line CSel is from the control console to each functional module 0-5 serving as the slave equipment, and the gating signal line CSel is used for transmitting the gating signal sent by the control console to the slave equipment. In one embodiment, the gating signal line CSel is active high. Similar to the interrupt request signal line IRQ, the gate signal lines of different slave devices are distinguished by CSel _0 to CSel _5 in fig. 2.

The command signal line or the read/write enable signal line CR/Wn is shared by the respective slave devices and is used for transmitting a read/write operation command transmitted from the console to the respective slave devices. In one embodiment, a high level of the read/write enable signal line CR/Wn represents a read operation command, and a low level represents a write operation command. When the signal is at a high level (logic 1), the console reads the internal register of the functional module that has been gated by the gating signal line CSel; when the signal is low (logic 0), the console writes data to the internal register of the functional block that has been gated via the gating signal line CSel.

As shown in fig. 2, similar to the data lines of the system on chip in the related art, the data lines of the control/status channel are also composed of separate write data lines CDadaOut and read data lines CDataIn. In FIG. 2, the write data lines CDadaOut are shared by the various slaves, in the direction from the console to functional modules 0-5 as slaves. The direction of the data reading line CDataIn is from each functional module 0-5 as slave equipment to the console; each of the function modules 0 to 5 as the slave devices has a read data line CDataIn connected to the console as the master device, and the read data lines of different slave devices and the console, such as CDataIn _0 to CDataIn _5, are distinguished in fig. 2 by adding an underline and a number identical to the function module number after the CDataIn. Since the control/status channel is only used to transfer control/status information of each functional module, too wide data lines are not required. In one embodiment of the present invention, the data line width of the control/status channel is 32 bits, but it should be understood that the data line width may be varied in other ways according to the actual needs of the user.

As can be seen from the foregoing description of the control/status channels and FIG. 2, the slave devices in each control/status channel, such as the functional modules 0-5 in FIG. 2, are connected to the data lines, address lines and control lines in the control/status channels in the same manner, so that each slave device can have the same bus interface, which is very convenient for the expansion of the functional modules of the system on chip. For example, in fig. 2, the system on chip may be extended to have a functional module N-1 and a functional module N (not shown in the figure) as the slave devices, where N may be any number of slave devices that meets the user's requirement. The functional modules N-1 and N have the same bus interfaces as the functional modules 0 to 5, and the bus interfaces are connected to the console through the gate signal lines CSel _ (N-1), CSel _ N and the interrupt request signal lines IRQ _ (N-1), IRQ _ N, respectively, in addition to the read/write enable signal line CR/Wn, the address line CAddr, and the write data line CDadaOut which are shared by the slave devices in the control/status channel, and are all identical to the functional modules 0 to 5.

The control/status channel usually has only read and write operations, and the console is responsible for initiating the operations. When the console selects the slave device to be operated, the console notifies the functional module by using a gating signal line CSel, and then sends out a read-write operation command CR/Wn to obtain required data from a read data line CDataIn of the control/status channel or send the data to a write data line CDadaOut of the control/status channel.

FIG. 3 shows a timing diagram for a read operation of the control/status channel. As shown in fig. 3, in clock cycle 2 of the clock signal Clk, the console selects a slave device to read data by pulling up the level of the strobe signal line CSel, and then issues a read operation command by pulling up the level of the read/write enable signal line CR/Wn, while sending out the address Addr0 of the register to be read through the address line CAddr. In clock cycle 3 of clock signal Clk, the addressed slave drives the read Data line CDataIn in its control/status channel, feeding the Data0 at address Addr0 onto the read Data line CDataIn of the control/status channel. In a continuous read operation, the console may also simultaneously send the address Addr1 of the next read Data at clock cycle 3, with the slave sending the Data1 at this address Addr1 onto the read Data bus of the control/status channel at clock cycle 4. The timing of multiple read Data operations, and so on, includes address Addr2 and Data2, which collectively comprise three Data read cycles in FIG. 3.

FIG. 4 shows a timing diagram for a write operation of the control/status channel. As shown in fig. 4, in clock cycle 2 of the clock signal Clk, the console selects a module to be read by the level of the pull-up strobe signal line CSel, issues a read operation command by the level of the pull-down read/write enable signal line CR/Wn, and sends out the address Addr0 of the written register through the address line CAddr while driving the write data line CDadaOut of the control/status channel. The data write operation is completed within one clock cycle. The timing of multiple write Data operations, and so on, includes addresses Addr1 and Addr2 and corresponding sum Data1 and Data2, again fig. 4 includes three Data write cycles in total.

Data channel

In the invention, the system-on-chip internally utilizes a data channel to exchange other data. In order to improve the performance of the system, it is necessary to increase the bandwidth of data communication as much as possible while reducing the delay of data transmission. In the invention, the data channel also adopts a master-slave device structure, namely, the functional modules exchange data in a master-slave device handshake mode, and can support a plurality of bus master devices. When multiple masters are included within a system-on-chip, a distributed arbitration mechanism is employed to associate an arbiter with a slave. The signal of address line and control line from the main device enters the arbitrator, which distributes the ownership of the bus according to the algorithm selected by the user. The arbiter generates the control signals for the multiplexers associated with that slave and the control signals for the multiplexers associated with all the associated masters (the masters operating that slave). Similar to the data lines of prior art system-on-chip, the data lines of the data channel are also made up of separate write data lines and read data lines, where the write data lines are oriented from the master to the slave and the read data lines are oriented from the slave to the master.

In the embodiment of fig. 5, a data channel structure of a system on chip is shown, in this embodiment, the system on chip internally includes two bus masters and two bus slaves, i.e., master 0 and master 1 and slave 0 and slave 1, respectively, and both master 0 and master 1 may operate both slave 0 and slave 1, where the master and slave in fig. 5 may be any functional module (including a console) in fig. 1.

In fig. 5, the master device 0 is connected to its address line 501, control line 502, and write data line 503, and the master device 1 is connected to its address line 501, control line 502, and write data line 503. Both

slave devices

0 and 1 are associated with one multiplexer and one arbiter, respectively, the first multiplexer S0 being associated with arbiter 0 and slave device 0, the first multiplexer S1 being associated with arbiter 1 and slave device 1. In order to select data returned from a plurality of slaves, one multiplexer is also associated with each of the two master terminals, the second multiplexer M0 being associated with master 0 and the second multiplexer M1 being associated with master 1.

As shown in FIG. 5, address lines 501 and 511, control lines 502 and 512, and write data lines 503 and 513 in the data channel are all connected from

masters

0 and 1 to

slaves

0 and 1. The address line 501, control line 502 and write data line 503 signals from the master device 0 and the address line 511, control line 512 and write data line 513 signals from the master device 1 need to be selected by the first multiplexer S0 and one of the signals is sent to the slave device 0 through the address line 51, the control line 52 and the write data line 53; similarly, the address line 501, control line 502 and write data line 503 signals from the master device 0 and the address line 511, control line 512 and write data line 513 signals from the master device 1 need to be selected by the first multiplexer S1 to send one of them to the slave device 1 through the address line 51 ', control line 52 ' and write data line 53 '.

As shown in fig. 5, signals according to which the first multiplexers S0 and S1 select are respectively from the arbiter 0 and the arbiter 1, wherein the arbiter 0 connects the master selection signal line 505 to the first multiplexer S0, and the arbiter 1 connects the master selection signal line 515 to the first multiplexer S1. Taking as an example the first multiplexer S0 and arbiter 0 associated with slave device 0, the address lines 501 and 511, and control lines 502 and 512 signals from the two

master devices

0 and 1 enter arbiter 0, arbiter 0 allocating ownership of the bus according to a user selected arbitration algorithm; arbiter 0 generates a master select signal and sends it to the first multiplexer S0 through the master select signal line 505. the first multiplexer S0 feeds the address, control and write data line signals of either master 0 or master 1 to slave 0 according to the master select signal it receives. The first multiplexer S1 and arbiter 1 associated with slave 1 operate in the same manner as the first multiplexer S0 and arbiter 0, with arbiter 1 generating a master select signal and sending it to the first multiplexer S1 via the master select signal line 515.

Read data lines 504 and 514 in the data lanes connect from slave 0 and slave 1 to master 0 and master 1. The read data lines 504 from the slave 0 and the read data lines 514 from the slave 1 are connected to the second multiplexer M0 associated with the master 0 and the second multiplexer M1 associated with the master 1, and one of the two paths is selected by the second multiplexers M0 and M1 and transmitted to the master 0 and the master 1 through the read data lines 54 and 54'.

The response signal of the slave device to the master device in the data channel is transmitted from the slave device to the master device through the response signal line. Wherein the reply signal of the slave device 0 is transmitted to the second multiplexers M0 and M1 through its reply signal line 500, respectively, and the reply signal of the slave device 1 is transmitted to the second multiplexers M0 and M1 through its reply signal line 510, respectively. The second multiplexer M0 selects the response signals from the slave device 0 and the slave device 1 and transmits one of the response signals to the master device 0 through the response signal line 50, and the second multiplexer M1 selects the response signals from the slave device 0 and the slave device 1 and transmits one of the response signals to the master device 1 through the response signal line 50'.

As shown in fig. 5, after the arbitration, the arbiter 0 and the arbiter 1 also send the bus use permission signal Gnt to the second multiplexer M0 and the second multiplexer M1. Therefore, the arbiter 0 connects the bus use permission signal lines 508 and 509 to the second multiplexer M0 and the second multiplexer M1, respectively, and the arbiter 1 connects the bus use permission signal lines 518 and 519 to the second multiplexer M0 and the second multiplexer M1, respectively. The second multiplexer M0 selects one of the bus use permission signal lines 508 and 518 to transmit to the master 0 through the bus use permission signal line 58, and the second multiplexer M1 selects one of the bus use permission signal lines 509 and 519 to transmit to the master 1 through the bus use permission signal line 59.

As previously indicated, the second multiplexer M0 and the second multiplexer M1 need to select the signals on the read data lines 504 and 514, the acknowledge signal lines 500 and 510, and the bus use permission signal lines 508 and 518, and 509 and 519 in order to transmit one of the signals to master 0 and master 1. The signals according to which the second multiplexer M0 and the second multiplexer M1 select are also from arbiter 0 and arbiter 1, respectively. As shown in fig. 5, the arbiter 0 is connected to the slave selection signal lines 506 and 507 to the first multiplexer M0 and the second multiplexer M1, respectively, so that the slave selection signal is transmitted from the arbiter 0 to the first multiplexer M0 and the second multiplexer M1; the arbiter 1 is connected to slave selection signal lines 516 and 517 to the first multiplexer M0 and the second multiplexer M1, respectively, so that the arbiter 1 transmits a slave selection signal to the first multiplexer M0 and the second multiplexer M1. The first multiplexer M0 performs a selection operation according to the slave selection signal transmitted from the device selection signal line 516 through the slave selection signal line 506 and the arbiter 1 through the slave selection signal line 506 for arbiter 0, and the second multiplexer M1 performs a selection operation according to the slave selection signal transmitted from the device selection signal line 517 through the slave selection signal line 507 and the arbiter 1 for arbiter 0.

In the data channel, since it transmits more data than the control/status channel, wider address and data lines are required. In one embodiment of the invention, address lines 501 and 511 of a data channel are 32 bits wide, addressing a 4GByte difference address space, and data lines of the data channel (including read data lines 504, 514 and write data lines 503, 513) are 128 bits wide. It should be understood that the widths of the address and data lines of the data channel may vary depending on the actual needs of the user.

In fig. 5, the direction of the control lines 501 and 511 of the data channel is from the master device to the slave device operated by the master device, and the signals transmitted include: the bus use request signal Req, the bus cycle flag signal Frame, the address valid flag signal AValid, the burst length BSize, the command signal or read/write enable signal R/Wn, the write data valid flag signal WValid, the byte enable flag DataBE on the data bus, the last write data flag signal WLast, the read data flag RReady that the master device can receive. Wherein,

the bus use request signal Req is used to transmit a bus use request sent by the master to the slave. In one embodiment, the bus use request Req is active high, which is used to signal a slave when a master needs to use the bus to transfer data.

The bus cycle flag signal Frame is used to transmit a one-time bus cycle flag. In one embodiment, the bus cycle flag signal Frame is active high.

The address valid flag signal AValid is used to transmit the address valid flag in the one-time bus operation request. In one embodiment, the address valid flag signal AValid is active high.

The burst length BSize is used to transmit the burst length in one bus operation. In one embodiment, the burst transfer length BSize uses an 8-bit bus width, and a maximum of 256 data can be transferred in one data read and write operation.

The command signal line or the read/write enable signal line R/Wn is used to transmit a read/write operation command sent from the master device to each slave device. In one embodiment, a high level of the read/write enable signal line R/Wn represents a read operation command, and a low level represents a write operation command.

The write data valid flag signal WValid is used to transmit a data valid flag on the write data bus in one bus write operation. In one embodiment, the write data valid flag signal WValid is active high.

The byte enable flags DataBE on the data bus are used to transmit the corresponding byte valid flags on the write data line and the read data line for a bus operation. In one embodiment, the byte enable flag DataBE uses a 16-bit bus width to indicate whether each byte of data is valid for a data transfer. In one embodiment, byte enable flag DataBE is active high, DataBE [0] is active high indicating byte 0 is active, DataBE [1] is active high indicating byte 1 is active, and so on.

The last write data flag signal WLast is used to transfer the flag of the last write data operation in a bus write operation. In one embodiment, the last write data flag signal WLast is active high.

The master device may receive the read data flag RReady for transmitting a read data ready flag for the master device in a bus read operation. In one embodiment, the master device may receive the read data flag RReady active high.

In the data channel, the reply signals transmitted by the reply signal lines 500 and 510 include: the bus operation acknowledge signal Ack, the slave device can receive the data flag WReady, the read data valid flag RValid, and the last read data flag RLast. Wherein,

the bus operation acknowledge signal Ack is used to transmit a one-time bus cycle acknowledge flag, which is used to inform a master when a slave is able to respond to a request addressed to its master. In one embodiment, the bus operation acknowledge signal Ack is active high.

The slave may receive a data flag WReady for transmitting a one-time bus write ready flag, which is used to signal the master when a slave is able to receive data on the write bus. In one embodiment, the slave device may receive the data flag WReady active high.

The read data valid flag RValid is used to transmit a bus read operation data valid flag, which is used to signal to the master when a slave sends valid data onto the read data bus. In one embodiment, the read data valid flag RValid is active high.

The last read data flag RLast is used to transmit the last data flag of a bus read operation, which is used to signal the master when a slave is to send the last data onto the read data bus. In one embodiment, the last read data flag RLast is active high.

As can be seen from the foregoing description of the data channel and fig. 5, the master device and the slave device in the data channel are connected to the data line, the address line and the control line in the data channel in the same manner, so that each master device or each slave device can have the same bus interface, which is very convenient for the expansion of the functional module of the system on chip.

Usually, only read and write operations are performed on the data channel, and both operations are initiated by the master device. When the master device needs to use the bus, it initiates a bus use request by means of a bus use request signal Req, and the slave devices respond by means of a bus use grant signal Gnt issued by their associated arbiters. The master device uses the bus cycle flag signal Frame to represent a bus operation, and sends out the address Addr, the address valid signal AValid and the command signal R/Wn at the same time, the slave device determines whether to respond to the operation or not by decoding, and uses the bus operation response signal Ack to inform the master device. If responding to the present bus operation, the slave device receives data on the write data lines or sends valid data to the read data lines according to the command signal R/Wn.

FIG. 6 illustrates a timing diagram for a read operation of a data channel. As shown in FIG. 6, the master pulls up the Req signal in clock cycle 1 to issue a data channel operation request. The arbiter pulls up the Gnt signal on clock cycle 2 to grant the master use of the data channel. In a clock period 3, the master device pulls up the Frame signal to indicate that one data channel operation is started, the pull-up R/Wn signal sends out a data channel reading command, the lowest address of the reading operation is sent out, the pull-up AValid signal indicates that the address is valid, and meanwhile, the length BSize of the burst transmission is sent out. Pulling the RReady signal up by the master device at clock cycle 4 indicates that the read data from the slave device may be received into a read ready state. The master determines to mask those invalid data bytes by setting the appropriate bits in the DataBE. In clock cycle 5 the slave device responds to the present read operation by decoding the address, pulling up the Ack signal for bus acknowledge. Keeping RValid zero continues since the internal data is not ready, inserting a wait period. Clock cycles 6 and 7 are both slave inserted latency cycles. At clock cycle 8, the RValid signal is pulled from the device to start transferring data onto the read data line Rdata of the data lane, and the period when RReady and RValid are simultaneously valid is one data transfer period. There are 8 data transmission cycles (BSize ═ 8) in fig. 6. Clock cycle 15 is the last data transfer cycle, which the master indicates by pull-up RLast is the last read data cycle. In clock cycle 16, the master device pulls down the Frame signal to mark the end of the read operation, and simultaneously pulls down the AValid, RReady and RLast signals. The slave pulls down the Ack and RValid signals to return to the idle state.

FIG. 7 illustrates a timing diagram for a write operation of a data channel. As shown in FIG. 7, the master pulls up the Req signal in clock cycle 1 to issue a data channel operation request. The arbiter pulls up the Gnt signal on clock cycle 2 to grant the master use of the data channel. In a clock period 3, the master device pulls up the Frame signal to indicate that one data channel operation is started, pulls down the R/Wn signal to send out a data channel writing command, sends out the lowest address of the current writing operation, and pulls up the AValid signal to indicate that the address is valid and simultaneously sends out the length BSize of the current burst transmission. Unlike a data channel read operation, the master sends out the first data to be transferred and pulls up the WValid signal. Some bytes may be masked off by setting the appropriate bit in the DataBE. In clock cycle 5 the slave device responds to the present read operation by decoding the address, pulling up the Ack signal for bus acknowledge. Since the slave internal space is ready, the data on the write data line Wdata can be received, pulling up the WReady signal. The period in which WReady and WValid are simultaneously valid is a data transmission period, and

periods

5, 6, 7, and 8 in fig. 7 are all data transmission periods. The slave device cannot receive data on the write data line any more internally in clock cycle 9 and the pull-down WReady signal inserts a wait cycle. At clock cycle 10, when the slave device internal space is ready, data on the write data lines may continue to be received, pulling up WReady signal to begin a new data transfer cycle. Clock cycle 15 is the last data transfer cycle, which the master device indicates by pulling WLast as the last write data cycle. And in a clock period 16, the master device pulls down the Frame signal to mark the end of the write operation, and simultaneously pulls down the AValid, WValid and RWast signals. The slave pulls down Ack and WReady signals and resumes an idle state.

In order to increase the data communication bandwidth within the system, the data channel uses a slave device association arbitration policy. If a slave device needs to respond to operation requests of a plurality of master devices, in order to avoid bus operation conflict, an arbiter is used for distributing the use right of the slave device. In one embodiment, the arbiter uses a round robin scheduling algorithm to decide which master's operation request to respond to. As shown in fig. 8, the arbiter receives master operation requests from all associated masters, selects the request signal with the highest current priority from the request signal queuing logic inside the arbiter according to the priority order stored in the priority queue inside the arbiter, and responds to the corresponding master (e.g., bus use grant signals 508 and 509 in fig. 5) by the arbitration and output control signal generation logic inside the arbiter, while sending out selection control signals to the multiplexer (e.g., master selection signal 505 and slave selection signals 506 and 507 of arbiter 0 in fig. 5). When a bus operation is completed, the request signal is deactivated, the arbiter reorders the priority order in its priority queue, with the least recently served master being ranked at the highest priority and the just served master being ranked at the lowest priority. Where N in fig. 8 is the number of master devices operating the same slave device.

Although only two masters and two slaves have been used as an example to illustrate the structure of the data channel of the present invention, those skilled in the art can easily derive embodiments of data channels with more masters and/or more slaves and also easily derive embodiments of data channels with fewer masters and/or fewer slaves from the above description. For example, it is obvious that when there is only one master in the data channel of the system on chip, the first multiplexer and arbiter on the slave side can be omitted; when there is only one slave in the data channel of the system on chip, the second multiplexer on the master side can be omitted.

In the present invention, each functional module as a master device or a slave device may be compiled, integrated, simulated, and debugged using a Hardware Description Language (Hardware Description Language HDL) and then downloaded into an FPGA device or an asic, thereby implementing a system on chip. Alternatively, the functional blocks may be implemented as Application Specific Integrated Circuits (ASICs),

the user designs or selects different functional modules according to the own needs, and can construct a high-performance application-specific integrated circuit suitable for different applications.

Claims

1. A system on chip, comprising a plurality of functional modules, connected with an internal bus between the functional modules, characterized in that the internal bus comprises two independent transmission channels, and is:

a control/status channel for transmitting control/status information; and

a data channel for transmitting data other than control/status information;

2. The system on chip of claim 1, wherein the control/status channel of the system on chip is a master-slave device structure, one of the plurality of functional modules connected to the control/status channel is a master device, and the functional modules other than the master device are slave devices.

3. The system on a chip of claim 2, wherein the data lines of the control/status channel comprise:

a write data line common to all slave devices; and

a read data line between the slave device and the master device.

4. System on chip according to claim 1 or 2, characterized in that the address line of the control/status channel is common to all slave devices.

5. The system on a chip of claim 2, wherein the control lines of the control/status channel comprise:

interrupt request signal lines from the respective slave devices to the master device;

a strobe signal line from the master device to each slave device; and

a command signal line common to all slave devices.

6. The system on chip of claim 1, wherein a data channel of the system on chip is a master-slave device structure, and the plurality of functional modules connected to the data channel include at least one master device and at least one slave device; the address lines and the control lines are connected from the master device to the slave device; the data lines include separate write data lines and read data lines, the write data lines being connected from the master device to the slave device, the read data lines and slave devices being connected to the master device.

7. The system on chip of claim 6, wherein the data channel comprises a plurality of masters, the data channel further comprises a first multiplexer and an arbiter associated with the slaves, the arbiter performs an arbitration operation according to address and control signals sent by the masters and allocates bus usage rights of the masters according to the arbitration result, and the arbiter is further connected to the first multiplexer and controls the first multiplexer to select signals from the masters.

8. The system on a chip of claim 6 or 7, wherein the data lane includes a plurality of slave devices, and further comprising a second multiplexer associated with a master device, the second multiplexer selecting signals from the plurality of slave devices.

9. The system on a chip of claim 8, wherein the second multiplexer is coupled to the arbiter and is controlled by the arbiter to select the signals from the plurality of slave devices.

10. The system on chip of claim 7, wherein the arbiter is an arbiter that employs a round robin scheduling algorithm.