CN1131484C - Structure for information transmission bus - Google Patents
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- CN1131484C CN1131484C CN 99113736 CN99113736A CN1131484C CN 1131484 C CN1131484 C CN 1131484C CN 99113736 CN99113736 CN 99113736 CN 99113736 A CN99113736 A CN 99113736A CN 1131484 C CN1131484 C CN 1131484C
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Abstract
The present invention discloses a structure of information transmission buses, which comprises a bus buffer area module, a bus logical module, a bus interface module, a bus arbitration module, a data transmission sub-bus, an arbitration sub-bus and an application sub-bus, and the bus structure can satisfy the real time performance of base station systems. The bus buffer area module increases the work efficiency of a processor and only adopts 32-bit synchronous transmission, and the bus buffer area module simplifies bus structures and increases the cost performance of products. In addition, a rotation priority level makes all processing plates completely equal and makes the arrangement of the processing plates more flexible.
Description
The present invention relates to the processing of interconnection or transfer requests for information or other signals between memories, input/output devices or central processing units, and more particularly to a message transmission bus system.
The VME bus structure of MOTOROLA corporation is a 32-bit computer bus, and the structure has the following main characteristics:
a, adopting a bus master control/target structure;
b, asynchronous and non-multiplexing transmission mode;
c, supporting 16-bit, 24-bit and 32-bit addressing and 8-bit, 16-bit, 24-bit and 32-bit data transmission;
d, transmission rate max 40 MPS;
e, 4 bus request lines, adopting daisy chain priority queue;
f, there are a maximum of 21 processors.
Obviously, the requirement of real-time performance of the communication base station system cannot be met by adopting the asynchronous transmission mode. Due to the adoption of the daisy chain priority queue in the 4 bus request lines, the processing boards are not completely equal and cannot be flexibly configured. The working efficiency of each processing plate is low; due to the fact that the VME bus structure is free of a buffer area, the working time of a CPU is always occupied by crowding when data signals are transmitted, and the working efficiency of the CPU is affected. Therefore, the VME bus structure and the data transmission mode are not suitable for the digital mobile communication base station system, and it cannot satisfy the characteristics of the communication base station system.
To this end, the object of the present invention is to provide a message transmission bus system that addresses the above-mentioned problems. The message transmission bus system can not only conform to the overall scheme of the mobile communication base station system, but also meet the characteristics of the base station system.
In order to achieve the purpose, the invention adopts the following technical scheme: the message transmission bus system comprises a bus buffer module, a bus logic module, a bus interface module, a bus arbitration module and three groups of signal sub-buses,
wherein,
the bus buffer module is used for buffering the transmitted data;
the bus logic module is divided into a data sending part and a data receiving part according to functions, the data sending part applies for a bus after receiving a command of requesting data sending of a CPU, transmits a data block to the bus according to requirements after acquiring the bus, and the data receiving part monitors the state of the bus, starts receiving operation when monitoring that a target address for transmitting data is the same as a board slot number of the data receiving part and writes the data into a bus buffer area;
the bus interface module is used for driving and isolating signals when each functional module is connected with a bus;
the bus arbitration module is used for processing bus request signals of all nodes in the system, arbitrating according to the principle of cycle priority and sending out bus grant commands.
Obviously, the message transmission bus system of the present invention has the following main features compared with the VME bus of MOTOROLA corporation:
a, 32 bit synchronous transmission and a maximum transmission rate of 40MBYTE per second;
b, adopting a system clock of 10 MBPS;
c, the data adopts a block transmission mode (64BYTE is used as a minimum transmission block);
d, synchronous arbitration and communication mode;
e, completely equal cycle priority bus arbitration and no daisy chain priority queue;
f, the bus buffer area is set to enable data communication not to occupy the working time of the CPU;
g, bus error and system error monitoring.
The bus system has the advantages that as the synchronous clock is added, and synchronous transmission and arbitration are adopted, the bus system can meet the real-time performance of the base station system; the bus buffer module improves the working efficiency of the processor, and only adopts 32-bit synchronous transmission, simplifies a bus system and improves the cost performance of a product; in addition, the adoption of the circulation priority level enables all the processing boards to be completely equal, and the configuration is more flexible.
The invention will be further explained in detail with reference to the following figures and examples:
FIG. 1 is a diagram of a bus buffer structure according to the present invention.
FIG. 2 is a diagram illustrating the definition of control bytes according to the present invention.
FIG. 3 is a schematic diagram of the round robin priority of the bus arbitration module according to the present invention.
Fig. 4 is a schematic diagram of a processor platform structure applied to a digital mobile communication base station system according to the present invention.
Referring to FIGS. 1 and 3,
the message transmission bus system of the invention comprises a bus buffer module, a bus logic module, a bus interface module, a bus arbitration module and three groups of signal sub-buses,
wherein,
the bus buffer module is used for buffering the transmitted data;
the bus logic module is divided into a data sending part and a data receiving part according to functions, the data sending part applies for a bus after receiving a command of requesting data sending of a CPU, transmits a data block to the bus according to requirements after acquiring the bus, and the data receiving part monitors the state of the bus, starts receiving operation when monitoring that a target address for transmitting data is the same as a board slot number of the data receiving part and writes the data into a bus buffer area;
the bus interface module is used for driving and isolating signals when each functional module is connected with a bus;
the bus arbitration module is used for processing bus request signals of all nodes in the system, arbitrating according to the principle of cycle priority and sending out bus grant commands.
The bus buffer module is arranged so as to enable data communication to not occupy the working time of a CPU, thereby improving the working efficiency of the whole system. In the design scheme of the MEST bus, a random access memory of 16KBYTE is used as a bus buffer, the bus takes a data block (64BYTE) as the minimum unit when data is transmitted, the whole buffer area is divided into a receiving data buffer area and a sending data buffer area which are equal in size, and the data block units of 128 blocks are occupied by each bus and are transmitted by taking the data block as the unit.
When a message is transferred, two BYTEs (called control BYTEs) must be added to the header of the message to enable the bus to function properly. The contents and meanings of the two control bytes are identical, and the hardware circuit carries out error identification through consistency check on the two bytes. The section definition of the control word is shown in fig. 2.
The MBN2 to MBN0 indicate the number of data blocks occupied by the transmitted message, and the TGAs 4 to 0 indicate the destination address of the transmitted message, that is, the slot number of the destination board.
The bus logic module is composed of a group of logic circuits, and is realized by a programmable gate array (FPGA) on the circuits.
And the data sending blocks of the data sending part of the bus logic module form a chain structure according to a circulation principle.
Due to the bus specificity, i.e., multiple (up to 21) input/output contacts are connected to each signal line, the signal connections must be carefully designed to account for the fan-in/fan-out factor of each signal driver. The MEST bus interface circuit is designed in accordance with the standard of the VME bus.
The clock signal is output by the system control panel and input by other panels in a RS485 balanced transmission mode. The bus error signal/BERR is in an Open Collector (OC) mode. Address lines, bus request grants, etc. are implemented using national semiconductor corporation's high performance interface integrated circuit 74ABT 245.
The bus arbitration module is arranged on a system control board, and the arbitration function is realized in a programmable gate array (FPGA).
The bus arbitration module carries out bus arbitration according to a cycle priority principle (figure 3), and adopts a grouping two-stage arbitration scheme, and the arbitration result is selected by a selection circuit and output by a bus permission output circuit.
The bus arbitration module is also provided with a timing generation circuit, which aims to prevent deadlock of the system or blocking of the bus due to abnormality of some processor boards. Its function has two aspects. First, the limit processor board must drive the Busy Bus Signal (BBSY) low for 32 system clock cycles after acquiring the bus; second, the processor board is limited to occupy the bus less than 1024 system clock cycles at a time.
The round robin order of the round robin priorities of the four application lines is shown in FIG. 3.
The three groups of signal sub-buses included in the invention are respectively called a Data Transmission Bus (DTB), an Arbitration Bus (AB) and an application bus (UB).
The data transfer bus includes the following signal lines:
and bidirectional data lines (32 lines) for transmitting data.
And bidirectional address lines (5 pieces) for indicating the addresses of the target boards.
The address latch signal (2 pieces) in both directions is used to indicate the valid time of the target address line.
When a group of data needs to be transmitted to the target board, the source signal board sends 32-bit data and a target address to the bus (32 data lines) and (5 address lines) respectively after acquiring the bus. With the target address unchanged, a maximum of 8 blocks of data can be transmitted at a time.
The arbitration bus includes the following signal lines:
unidirectional bus request signals (21), active low. The request lines of the 21 processor boards each apply for a bus to a main processor board that includes a bus arbiter.
Unidirectional buses grant signal lines (5). The master processor board is used to indicate a board slot number of the granted bus processor board.
The unidirectional bus permits latching the signal line (MBGS), active low. When the unidirectional bus grant latch signal line (MBGS) signal is low, each processor board samples the bus grant signal to determine whether it can occupy the bus.
The bus busy signal line (MBBSY), active low. When the signal is low, it indicates that the bus is being occupied by a processor board in the system.
The application bus contains the following signal lines:
system clock signal line (MSYSCLOCK). The system clock is provided to the bus logic module of each processor board by the main processor board so as to realize data synchronous transmission. The frequency is 10Mbps with a duty cycle of 50%.
System fault signal line (MSYSFAIL), active high. Each processor board monitors the signal. When MSYSFAIL is high, it indicates that the bus arbiter of the main processor board is not working properly.
Bus error signal line (MBERR), active low. The bus architecture of the present invention determines that each processor board must occupy the bus for a specified time, and the time to occupy the bus each time is limited. Therefore, when the processor board fails to meet the two-point requirement, the bus arbiter will drive (MBERR) low.
In a GSM900/1800 digital mobile communication base station system (developed by Shanghai Datang company), a BSC bus must work in a synchronous state, and the requirement on instantaneity is high; the process plates are in a completely equal position in the system and need to be flexibly configured. The bus structure and data transmission mode of the VME bus obviously cannot satisfy the characteristics of the base station system itself, and the message transmission bus system described above, which satisfies both the overall scheme and the characteristics of the base station system, is designed for this purpose.
The signal transmission of the bus interface of the present invention and the signal transmission on the motherboard are both referenced to the electrical characteristics standard of the VME bus (ANSI/IEEE STD1014-1987 IEC 821 and 297). The mechanical properties are also referenced to the standards of the VME bus. The connectors of each processor board employ EUROCARD (europad) sockets, the pin arrangement being referenced to the VME bus arrangement and being modified and adapted as appropriate to the specifics of the message transmission bus system of the present invention.
Referring to fig. 4, the bus structure of the present invention is a multi-processor bus designed for GSM900/1800 digital mobile communication base station system (BSC).
According to the overall scheme of the BSC, the BSC mainly comprises a switching platform and a processor platform. Wherein the processor platform can accommodate up to 21 processor BOARDs, named BOARD0, BOARD1, …, BOARD 20. BOARD0 and BOARD1 are system control BOARDs (SCs) and are primary backups of each other. All of them have the function of bus arbitration, but only one arbiter can really realize the function of bus arbitration in the system at the same time. The BOARD 2-20 are signaling processing BOARDs, which are identical in hardware, and the CPU on the BOARD can communicate with other CPU BOARDs through a bus circuit.
When CPUi is ready to communicate with CPUj (i ≠ j, i is greater than or equal to 0 and less than or equal to 20, j is greater than or equal to 0 and less than or equal to 20),
the CPUi writes the data to be transmitted into the corresponding position of the bus buffer of the board, and then sends a bus transmission request to the bus logic module of the board. The bus logic module requests the bus arbiter upon receiving a request command from the CPU for a bus transfer. The bus arbiter can simultaneously receive bus request signals from 21 boards (including itself), and according to the current bus state, the bus is allocated to a CPU board requesting the bus according to the round robin priority principle. When the CPUi board obtains the bus permission, the data is transmitted to a specific area of a bus buffer of the target board through the bus according to the target address provided by the CPU. And after the transmission is finished, the bus logic module releases the bus. The bus logic module of the target board assists the bus transmission on one hand, and informs the CPU of the target board in an interrupt form after the data reception is finished on the other hand. The target CPU fetches data from a specific bus buffer according to the related information provided by the bus logic module, thereby completing a bus transfer operation.
At present, the bus of the invention has good operation condition in a GSM900/1800 digital mobile communication base station system, and has the following advantages:
the synchronous transmission and the synchronous arbitration satisfy the overall scheme of the base station system.
The setting of the bus buffer, the data transmission mode (64BYTE is used as the minimum transmission block) and the bus error and system error monitoring are adopted, so that the running speed, the processing capacity and the working efficiency of the system are improved.
The completely equal cycle priority bus arbitration does not contain the daisy chain priority queue, just meets the characteristic that each signaling board is completely equal in the system, and enables each processing board to be flexibly configured.
The simplified bus system not only simplifies the operation process of the system, but also improves the cost performance of the product.
Claims (10)
1. A message transmission bus system, characterized by:
comprises a bus buffer module, a bus logic module, a bus interface module and a bus arbitration module;
and, three sets of signal sub-buses,
wherein,
the bus buffer module is used for buffering the transmitted data;
the bus logic module is divided into a data sending part and a data receiving part according to functions, the data sending part applies for a bus after receiving a command of requesting data sending of a CPU, transmits a data block to the bus according to requirements after acquiring the bus, and the data receiving part monitors the state of the bus, starts receiving operation when monitoring that a target address for transmitting data is the same as a board slot number of the data receiving part and writes the data into a bus buffer area;
the bus interface module is used for driving and isolating signals when each functional module is connected with a bus;
the bus arbitration module is used for processing bus request signals of all nodes in the system, arbitrating according to the principle of cycle priority and sending out bus grant commands.
2. The message transmission bus system as recited in claim 1, wherein: the bus buffer module is divided into a receiving data buffer and a transmitting data buffer.
3. The message transmission bus system as recited in claim 2, wherein: the receiving data buffer and the sending data buffer are equal in size, each of the receiving data buffer and the sending data buffer occupies 128 data block units, and the data blocks are used as units for transmission.
4. The message transmission bus system as recited in claim 1, wherein: the transmitted data blocks of the data transmitting part form a chain structure according to a circulation principle.
5. The message transmission bus system as recited in claim 1, wherein: the clock signal of the bus interface module adopts a RS485 balanced transmission mode and is output by a system control board, the bus error signal adopts an open collector mode, and the address line and the bus request permit to adopt an interface integrated circuit 74ABT 245.
6. The message transmission bus system as recited in claim 1, wherein: the bus arbitration module arbitrates the bus according to a cycle priority principle, and the arbitration result is selected by the selection circuit and output by the bus permission output circuit; the bus arbitration module is also provided with a timing generation circuit to prevent deadlock or bus blockage caused by exception of a certain processor.
7. The message transmission bus system as recited in claim 1, wherein: the three groups of signal sub-buses comprise a data transmission sub-bus, an arbitration sub-bus and an application sub-bus.
8. The message transmission bus system as recited in claim 7, wherein: the data transmission sub-bus comprises a bidirectional data signal line, a bidirectional address signal line and a bidirectional address latch signal line.
9. The message transmission bus system as recited in claim 7, wherein: the arbitration sub-bus comprises a unidirectional bus request signal line, a unidirectional bus grant latch signal line and a bus busy signal line.
10. The message transmission bus system as recited in claim 7, wherein: the application sub-bus comprises a system clock signal line, a system fault signal line and a bus error signal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99113736 CN1131484C (en) | 1999-05-27 | 1999-05-27 | Structure for information transmission bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99113736 CN1131484C (en) | 1999-05-27 | 1999-05-27 | Structure for information transmission bus |
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| Publication Number | Publication Date |
|---|---|
| CN1275737A CN1275737A (en) | 2000-12-06 |
| CN1131484C true CN1131484C (en) | 2003-12-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 99113736 Expired - Lifetime CN1131484C (en) | 1999-05-27 | 1999-05-27 | Structure for information transmission bus |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102525453B (en) * | 2012-02-15 | 2014-03-19 | 南京伟思医疗科技有限责任公司 | Electroencephalogram detection device and method |
| CN102551709A (en) * | 2012-02-15 | 2012-07-11 | 南京伟思医疗科技有限责任公司 | Data acquisition circuit for electroencephalogram detection |
| CN105320632B (en) * | 2015-09-23 | 2018-05-29 | 南京磐能电力科技股份有限公司 | A kind of high-speed-differential bus realization method independently arbitrated |
| CN109800534B (en) * | 2019-02-14 | 2020-03-10 | 广东高云半导体科技股份有限公司 | FPGA (field programmable Gate array) design circuit diagram generation method and device, computer equipment and storage medium |
| CN111478840A (en) * | 2020-04-15 | 2020-07-31 | 联合华芯电子有限公司 | Double-rate arbitration relay device for bus system |
| CN111314190A (en) * | 2020-04-15 | 2020-06-19 | 联合华芯电子有限公司 | Data transmission system and method with arbitration interface having reset function |
| CN112579490A (en) * | 2020-12-21 | 2021-03-30 | 太原智林信息技术股份有限公司 | Programmable electronic building block connecting bus |
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- 1999-05-27 CN CN 99113736 patent/CN1131484C/en not_active Expired - Lifetime
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Date of cancellation: 20100413 Granted publication date: 20031217 Pledgee: National Development Bank Pledgor: Datang Mobile Communications Equipment Co|Shanghai Datang Mobile Communications Equipment Co|Telecom Research Institute of science and technology Registration number: 2007110000354 |
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