CN112579490A - Programmable electronic building block connecting bus - Google Patents
Programmable electronic building block connecting bus Download PDFInfo
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- CN112579490A CN112579490A CN202011515001.1A CN202011515001A CN112579490A CN 112579490 A CN112579490 A CN 112579490A CN 202011515001 A CN202011515001 A CN 202011515001A CN 112579490 A CN112579490 A CN 112579490A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
Abstract
The invention belongs to the field of programmable electronic building block connection application. A programmable electronic building block connecting bus is composed of a power line, a ground line, a system processor data transmission line, a system processor data receiving line and a state line, wherein the system bus formed by the system processor data transmission line, the system processor data receiving line and the state line is connected with a plurality of electronic building blocks, the system processor defines a group of independent addresses for each electronic building block, the addresses are stored in programmable logic devices in the electronic building blocks, and a message transmission mechanism is adopted, and the system processor transmits data to all the electronic building blocks on the system bus through the system processor data transmission line.
Description
Technical Field
The invention discloses a programmable electronic building block connecting bus, and belongs to the field of programmable electronic building block connecting application.
Background
The electronic building blocks are formed by fixing electronic components on the building block modules and connecting a plurality of electronic building blocks with each other in a building block splicing mode to form an electronic system. Programmable electronic building blocks are widely applied to teenager creative guest programming activities, the electronic building blocks are connected with a main control board, and a user controls the electronic building blocks or collects data transmitted by the electronic building blocks through programming software by using the main control board. At present electronic toy adopts directly to link to each other the mode with the main control board, in the system design, every increase electronic toy, will occupy more controller IO ports, because main control board treater IO port quantity is limited, the electronic toy quantity of joinable in the system receives the restriction, and present electronic toy interface is non-uniform, the user need look over the interface definition when using, use the connecting wire to link to each other with the main control board, occupy a large amount of time, and if connect improper still can damage system circuit board, bring the potential safety hazard. Chinese patent CN107583288A has designed an electronic building block with an I2C interface, where the electronic building block and the controller communicate in an I2C communication mode, and the I2C communication mode is half-duplex communication, so that the data transmission efficiency is not high.
Disclosure of Invention
In order to realize the unification of programmable electronic building block interfaces, the number of electronic building blocks connected by a system main control board is easy to expand, the occupation of IO ports of a main control board processor is reduced, the data transmission efficiency of the electronic building blocks is improved, and a programmable electronic building block connection bus is designed.
The technical scheme adopted by the invention is as follows: a programmable electronic building block connecting bus is composed of a power line, a ground line, a system processor data transmission line, a system processor data receiving line and a state line, wherein the system bus formed by the system processor data transmission line, the system processor data receiving line and the state line is connected with a plurality of electronic building blocks, the system processor defines a group of independent addresses for each electronic building block, the addresses are stored on programmable logic devices in the electronic building blocks, a message transmission mechanism is adopted, the system processor transmits data to all the electronic building blocks on the system bus through the system processor data transmission line, each electronic building block receives the data transmitted by the system processor, whether the data are received or not is judged according to destination address information in the data, and each electronic building block receives the data through the system processor and transmits the data to the system processor, the system processor judges the electronic building block information of the transmitted data according to the source address in the data, before each electronic building block transmits the data, the current state of the state line is detected, if the state line is in an idle state, the system processor receiving bus is occupied to transmit the data to the processor, meanwhile, the state line is set to be in a working state, and if the state line is in the working state, the working state of the state line is detected again after a random time delay.
Each electronic building block is composed of an electronic building block bus interface circuit and an electronic component, each electronic building block bus interface circuit is composed of an interface controller module, a data receiving cache, a data sending cache and a data format conversion module, the interface controller module receives data sent by a data line sent by a system processor, converts the data into a data transmission format of the electronic component through the data format conversion module and sends the data transmission format to the electronic component, meanwhile, data transmission format data of the electronic component is stored in the data receiving cache, the electronic component converts the data transmission format data of the electronic component into the data transmission format data of the system processor through the data format conversion module and stores the data transmission format data of the system processor in the data sending cache, and meanwhile, the data transmission format data of the system processor is received by the system processor and sent to the system processor through the data line.
The invention has the beneficial effects that: the problem of programmable electronic building blocks interface is not unified, occupy a large amount of IO ports of treater when electronic building blocks quantity increases, electronic building blocks can not parallel work is solved. The electronic building block hardware interface is unified, the hardware connection is convenient, a bus connection mode is adopted, the number of the electronic building block connections is not limited, a plurality of electronic building blocks can work simultaneously, and the data transmission efficiency is improved.
Drawings
FIG. 1 is a diagram of a programmable electronic building block bus and its application system architecture;
FIG. 2 is a diagram of a master control board processor sending a data frame format;
FIG. 3 is a diagram of an electronic building block sending a control frame format;
FIG. 4 is a diagram of an electronic building block sending a data frame format;
FIG. 5 is a diagram of a master control board processor transmitting a broadcast frame format;
fig. 6 shows an internal structure of the bus interface of the electronic toy.
Detailed Description
The method comprises the steps of designing a unified hardware interface of the programmable electronic building blocks, wherein the unified hardware interface comprises a power line, a ground line, a system processor sending data line, a system processor receiving data line, a state line and the like, the system bus is composed of the system processor sending data line, the system processor receiving data line and the state line, a main control board processor is connected with the electronic building blocks through the system bus, and the electronic building blocks are connected to the system bus through the unified hardware interface, as shown in figure 1. Each electronic building block is allocated with a group of independent addresses, the main control board processor sends data frames to all the electronic building blocks through the system processor sending data lines, the data frames are composed of frame types, destination addresses, data and verification, as shown in fig. 2, after each electronic building block receives the data, whether the destination addresses in the data frames are the same as the allocated addresses of the electronic building blocks is judged, if yes, the data are received, otherwise, the data of the frames are discarded. The electronic building block receiving the data checks the data, if the data is checked correctly, the data transmission is completed, if the data is checked incorrectly, the electronic building block sends a control frame to the main control board processor, the format of the control frame consists of the frame type, the source address and the check, and as shown in fig. 3, the main control board processor retransmits the data after receiving the control frame.
Each electronic building block shares a system processor receiving data line to transmit data to a main control board processor, and the electronic building block transmitting data is composed of a frame type, a source address, data and verification, as shown in fig. 4. Before the electronic building block sends data, the state line state is detected, if the state line is in an idle state, the electronic building block occupies the system processor to receive the data line to send the data, meanwhile, the state line is set to be in a working state, after data transmission is finished, the state line is set to be in the idle state, before the electronic building block sends the data, if the state line is detected to be in the working state, the state line state is detected again after a random time is delayed, and until the state line is in the idle state, the system processor is occupied to receive the data line to send the data. The main control board processor checks the data sent by the electronic building block after receiving the data, if the data are correctly checked, the data transmission is finished, if the data are incorrectly checked, the processor sends a broadcast frame to the processor to send a data line, wherein the broadcast frame is composed of a frame type, an error type and a check, and as shown in fig. 5, the electronic building block retransmits the data after receiving the broadcast frame.
The electronic building block is composed of an electronic building block bus interface and electronic components, wherein the electronic building block bus interface is composed of an interface controller module, a data receiving cache, a data sending cache and a data format conversion module, and is shown in fig. 6. The electronic building block bus interface receives data sent by the system processor, the interface controller module judges a destination address in a data frame, if the destination address is the same as the current electronic building block address, the received data is written into a data receiving cache, and the data format conversion module converts the data in the receiving cache into a data format required by the electronic component and sends the data format to the electronic component. The data format conversion module receives data sent by the electronic components and converts the data into a data format defined by the electronic building block connection bus, the converted data are written into a data sending cache of the electronic building block bus interface, the electronic building block bus interface controller detects a system state line, and if the system state line is in an idle state, the interface controller module reads the data from the data sending cache, receives the data line through the system processor and sends the data line to the main control board processor.
The programmable electronic building block connecting bus designed by the invention consists of 5 lines such as a power supply, a ground wire, a system processor data sending line, a system processor data receiving line, a state line and the like, wherein the 5 lines are connected with a system main control board, the system processor data sending line, the system processor data receiving line and the state line are connected with a processor of the main control board to form the system bus, the state line is pulled high by an external pull-up resistor, and a hardware interface is designed by adopting an anti-reverse socket. The programmable electronic building blocks are connected to a system bus through a bus interface, the number of the electronic building blocks which can be connected to the system bus is related to the number of data bits of an address field in a data frame, and if the number of the data bits of the address field is 8 bits, the bus can be connected with 256 electronic building blocks at most. And a processor sending data line in the system bus is connected with a data receiving port of the electronic building block, a system processor receiving data line in the system bus is connected with a data sending port of the electronic building block, and a state line in the system bus is connected with a bus state detection port of the electronic building block.
The main control board processor transmits data to all electronic building blocks on a bus through a processor sending data line, each electronic building block is allocated with an address, the processor sending data frame is composed of a frame type, a destination address, data and check, wherein the frame type is defined as 0x01, the length of the destination address is defined as 8 bits, and the CRC-8 check algorithm is adopted, and the length is 8 bits. The electronic building blocks on the bus receive data sent by the main control board processor, judge whether a destination address in a data frame is the same as an address allocated by the node after receiving the data, discard the data of the data if the destination address is different from the address allocated by the node, continue to receive the data if the destination address is the same, perform CRC (cyclic redundancy check) on the received data after the data is received, end the data transmission if the check result is correct, and send a control frame to the main control board processor if the check result is wrong, wherein the format of the control frame is shown in FIG. 3, the frame type is defined as 0x02, the source address is the node address of the module, the length is 8 bits, a CRC-8 check algorithm is adopted, the length is 8 bits, and the main control board processor retransmits the data after receiving the control frame.
The programmable electronic building block is composed of an electronic building block bus interface circuit and electronic components, the electronic building block bus interface circuit is designed by adopting a VHDL or Verilog HDL hardware description language and is realized by using a programmable logic device CPLD or FPGA, and the interface circuit is composed of an interface controller module, a data receiving cache, a data sending cache and a data format conversion module. The interface controller module receives data sent by the main control board processor, judges whether a destination address in a data frame is the same as the node address, writes data segment data in the data frame into a data receiving cache, and carries out CRC (cyclic redundancy check) on the received data, if the check result is correct, the data format conversion module converts the data in the receiving cache into a data format required by the electronic component and transmits the data format to the electronic component.
All programmable electronic bricks on the system bus share a system processor receiving data line to transmit data to a main control board processor, and a data frame sent by each electronic brick consists of a frame type, a source address, data and check, wherein the frame type is defined as 0x03, the source address is an electronic brick node address, the length is 8 bits, and the length is 8 bits by adopting a CRC-8 check algorithm. The data format conversion module in the electronic building block bus interface circuit receives data sent by the electronic module, converts the data into a system bus data format, writes the data into a data sending cache, and the interface controller module detects a system state line, if the system state line is high level, the system processor receiving data line of the main control board is in an idle state, and if the system processor receiving data line is low level, the system processor receiving data line of the main control board is in a working state. When the system state line is in an idle state, the interface controller module reads data from the data sending cache, receives the data line through the system processor and sends the data line to the main control board processor, meanwhile, the state line is set to be a low level, and after data transmission is completed, the interface controller module sets the system state line to be a high-impedance state. And after receiving the data frame sent by the electronic building block, the main control board processor checks, if the check is correct, the data transmission is finished, if the check is wrong, the processor sends a broadcast frame to a processor sending data line, wherein the broadcast frame consists of a frame type, an error type and a check, the frame type is defined as 0x04, the error type is defined as 0x01, a CRC-8 check algorithm is adopted, the length is 8 bits, and the electronic building block retransmits the data after receiving the broadcast frame.
While the invention has been described in further detail in connection with specific embodiments thereof, it will be understood that the invention is not limited thereto, and that various other modifications and substitutions may be made by those skilled in the art without departing from the scope of the invention, which is to be determined by the claims appended hereto.
Claims (2)
1. A programmable electronic building block connection bus is characterized in that: the electronic building block connecting bus is composed of a power line, a ground line, a system processor sending data line, a system processor receiving data line and a state line, the system processor sends the data line through the system processor, the system processor receiving the data line and the state line is connected with a plurality of electronic building blocks, the system processor defines a group of independent addresses for each electronic building block, the addresses are stored on programmable logic devices in the electronic building blocks, a message transmission mechanism is adopted, the system processor sends the data line through the system processor to transmit the data to all the electronic building blocks on the system bus, each electronic building block receives the data sent by the system processor, whether the data is received or not is judged according to destination address information in the data, each electronic building block receives the data line through the system processor and transmits the data to the system processor, the system processor judges the electronic building block information which transmits the data according to a source address in the data, before each electronic building block sends data, the current state of a state line is detected, if the state line is in an idle state, a receiving bus of a system processor is occupied to transmit the data to the processor, meanwhile, the state line is set to be in a working state, and if the state line is in the working state, the working state of the state line is detected again after a random time is delayed.
2. A programmable electronic building block connection bus according to claim 1, characterized in that: each electronic building block is composed of an electronic building block bus interface circuit and an electronic component, each electronic building block bus interface circuit is composed of an interface controller module, a data receiving cache, a data sending cache and a data format conversion module, the interface controller module receives data sent by a data line sent by a system processor, converts the data into a data transmission format of the electronic component through the data format conversion module and sends the data transmission format to the electronic component, meanwhile, data transmission format data of the electronic component is stored in the data receiving cache, the electronic component converts the data transmission format data of the electronic component into the data transmission format data of the system processor through the data format conversion module and stores the data transmission format data of the system processor in the data sending cache, and meanwhile, the data transmission format data of the system processor is received by the system processor and sent to the system processor through the data line.
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| CN202011515001.1A CN112579490A (en) | 2020-12-21 | 2020-12-21 | Programmable electronic building block connecting bus |
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| CN202011515001.1A CN112579490A (en) | 2020-12-21 | 2020-12-21 | Programmable electronic building block connecting bus |
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| CN1275737A (en) * | 1999-05-27 | 2000-12-06 | 上海大唐移动通信设备有限公司 | Structure for information transmission bus |
| CN1818796A (en) * | 2006-03-16 | 2006-08-16 | 上海微电子装备有限公司 | Light-intensity data bus system and bus controller |
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| CN103605306A (en) * | 2013-11-18 | 2014-02-26 | 四川长虹电器股份有限公司 | Communication device based on UART communication interface extension |
| CN105389278A (en) * | 2015-10-13 | 2016-03-09 | 广东聚光电子科技有限公司 | CAN bus based serial communication method for master and slave machines |
| CN105635005A (en) * | 2016-03-23 | 2016-06-01 | 南京国电南自美卓控制系统有限公司 | Descriptor-based BLVDS bus data transmission device and method thereof |
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2020
- 2020-12-21 CN CN202011515001.1A patent/CN112579490A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1275737A (en) * | 1999-05-27 | 2000-12-06 | 上海大唐移动通信设备有限公司 | Structure for information transmission bus |
| CN1818796A (en) * | 2006-03-16 | 2006-08-16 | 上海微电子装备有限公司 | Light-intensity data bus system and bus controller |
| CN101145046A (en) * | 2007-08-24 | 2008-03-19 | 上海正航电子科技有限公司 | Programmable logic controller and expansion module interface |
| CN103605306A (en) * | 2013-11-18 | 2014-02-26 | 四川长虹电器股份有限公司 | Communication device based on UART communication interface extension |
| CN105389278A (en) * | 2015-10-13 | 2016-03-09 | 广东聚光电子科技有限公司 | CAN bus based serial communication method for master and slave machines |
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Application publication date: 20210330 |