CN217467655U

CN217467655U - Single IO mouth two-way communication structure of singlechip

Info

Publication number: CN217467655U
Application number: CN202221114081.4U
Authority: CN
Inventors: 滕跃; 李杰栋; 陈凯健; 田凯
Original assignee: Suzhou Jieyuefei Electronic Technology Co ltd
Current assignee: Suzhou Jieyuefei Electronic Technology Co ltd
Priority date: 2022-05-07
Filing date: 2022-05-07
Publication date: 2022-09-20
Anticipated expiration: 2032-05-07

Abstract

The utility model discloses a single IO mouth bidirectional communication structure of singlechip relates to the hardware communication field, include main circuit board, main singlechip, organize and protection resistance from singlechip, power module, lithium cell, power module's input and the output that lithium cell was organized are connected, power module's output and main circuit board are connected, supply power for main circuit board, main singlechip and from the singlechip all with main circuit board electric connection, main singlechip and from the singlechip carry out the communication connection through single IO interface, two IO mouths that main singlechip and communication from the singlechip are connected when connecting, establish ties between have protection resistance. The utility model has the advantages that: compared with the existing communication mode, fewer IO ports and cost can be used, effective transmission of data between the two single-chip microcomputers is achieved, communication is more reliable, the situation of data confusion cannot occur, and the data transmission rate is obviously improved.

Description

Single IO mouth bidirectional communication structure of singlechip

Technical Field

The utility model relates to a hardware communication field specifically relates to a single IO mouth bidirectional communication structure of singlechip.

Background

At present, the known communication modes between two singlechips mainly include the following communication modes:

(1) the hardware serial port UART of the singlechip is used for bidirectional communication, and the UART is a universal serial data bus and is a serial asynchronous receiving and transmitting protocol. The bus is in bidirectional communication, and full duplex transmission and reception can be realized. During bidirectional communication, hardware connection at least needs three signal wires which are TXD, RXD and GND respectively. TXD is a sender, RXD is a receiver, and the specific connection mode needs to enable the two singlechips to be grounded together, wherein the TXD of one party is connected with the RXD of the other party. The operating principle is that each byte of transmission data is transmitted according to bits, after a sender sends out data, the receiver does not need to send back a response, and then the next data frame can be sent. The serial port sends data through a level signal, and the specific process is as follows: firstly, sending 1-bit logic 0 (low level) as a start bit to start data transmission; transmitting data bits, generally transmitting one byte per 8 bits according to bits, transmitting low bits first and then transmitting high bits; thirdly, parity is sent, a parity check mode is usually adopted, the data bits are added with the parity bits, the number of bits of 1 is an even number (even check), and the number of bits of 1 is an odd number (odd check); sending logic 1 (high level) as stop bit to end data transmission; the UART is in high level when in idle, which represents no data transmission. The method has strict requirements on the time sequences of the two parties, the communication speed is low, and meanwhile, the UART is integrated on the single chip microcomputer, so that the cost of the corresponding single chip microcomputer is increased.

(2) I2C communication requires two wires, one SCL (clock line) and one SDA (data line). The clock line marks the data transmission process by a level change, and the SDA line transmits data. The start signal and the stop signal are both sent by the host, the SDA line represents the start signal from high level to low level during the SCL is high level, and represents the stop signal from low level to high level. After the starting signal is generated, the bus is in an occupied state, and data can be read and written through the SDA line by pulling down the SCL line; after the termination signal is generated, the bus is in an idle state, and data reading and writing can not be performed any more. The host needs to determine the response signal of the slave before reading and writing data, and can perform data transmission after receiving the response signal and confirming the slave. Data transmission typically has 8 bits for a frame of data followed by a single acknowledgement bit. The slave device receives the acknowledge bit and the acknowledge or non-acknowledge signal indicates the success or failure of the data reception (the opposite of the master-slave acknowledge for the read operation). In I2C communication, the master machine is used for programming control, the slave machine is used for autonomous control or hardware control, and the slave machine can be judged to give a master response signal only by checking that the SCL is kept at a low level for some time during the period that the SDA is high. The method can mount a plurality of devices as slaves theoretically, and the slaves are selected to communicate through the slave addresses, but the communication speed is very low because the slaves share two data lines and are half-duplex communication, meanwhile, the slaves cannot actively communicate, and if bidirectional communication is realized, a communication port line needs to be added.

(3) Similar to I2C, SPI communication is a master-slave communication mode, which generally has only one master and one or more slaves, standard SPI is 4 lines, which are SSEL (chip select, also written as SCS), SCLK (clock, also written as SCK), MOSI (master output slave input) and MISO (master input slave output), SPI is a synchronous data bus, that is, it uses a single data line and a single clock signal to ensure perfect synchronization of the sending end and the receiving end. The host pulls down the SSEL signal first, starts to receive data, selects the slave, starts to communicate, immediately reads the content on the data line when the slave detects the edge signal of the clock, and sends the data to the slave one bit by one bit from the MOSI signal line. When the Master receives the Slave data, if the Slave needs to send the data back to the Master, the Master will continue to generate a predetermined number of clock signals, and the Slave will send the data through the MISO signal line, that is, a data link loop will be generated between the Master device and the Slave device during the communication of the SPI device. The method has the advantages of simple software configuration, high data transmission rate and flexibility due to the perfect hardware condition, but the method occupies more pins, does not have hardware slave response signals, and can send data everywhere under the unknown condition by the host.

The existing single chip microcomputer communication structure at least needs two signal lines to complete data transmission and at least occupies two IO interfaces.

SUMMERY OF THE UTILITY MODEL

For solving the technical problem, the single IO port two-way communication structure of the single-chip microcomputer is provided, the technical scheme overcomes the problems that the transmission rate of the existing communication mode is low, the number of the occupied IO ports is large, the double-chip microcomputer communication realizes the complex, each IO port of the two single-chip microcomputers is used for carrying out the single-bus two-way communication, the single-bus two-way communication can be realized by only using one data line, the occupied IO ports are few, the data transmission rate is high, and the cost is effectively saved.

In order to achieve the above purpose, the utility model adopts the technical scheme that:

the utility model provides a single IO mouth bidirectional communication structure of singlechip, includes main circuit board, main singlechip, follows singlechip, power module, lithium cell group and protective resistance, power module's input is connected with the output of lithium cell group, power module's output and main circuit board are connected, for main circuit board supplies power, main singlechip and follow the singlechip all with main circuit board electric connection, main singlechip carries out the communication through single IO interface with following the singlechip and connects, two IO mouths that main singlechip and the communication of following the singlechip are connected when connecting, and it has protective resistance to establish ties between.

Preferably, only one of the master singlechip and the slave singlechip is in a data transmitting state, the other one of the master singlechip and the slave singlechip is in a data receiving state, and only one of the master singlechip and the slave singlechip can transmit data at the same time due to single-wire connection, otherwise, data confusion can occur.

Preferably, the resistance value of the protection resistor is 1K.

Furthermore, the data format transmitted between the master singlechip and the slave singlechip comprises a start bit and a data frame, each data bit has an end bit, when data communication is carried out, when the master singlechip starts to transmit, a bus busy line flag bit SBus _ TxBusy is set to be 1, firstly, low level is maintained for t1 time, then high level is maintained for t2 time, and t1 is greater than t2 and is used as the start bit, then the data frames are transmitted according to a certain sequence, after the transmission is finished, the master singlechip is switched to a receiving state, and after the transmission of the master singlechip is finished, the bus busy line flag bit SBus _ TxBusy is cleared to be 0;

reading a start bit signal sent by the main singlechip from the singlechip, reading a data frame, wherein the read data frame is opposite to the data frame sent by the main singlechip, the data frame needs to be shifted, and after reading a stop bit sent by the main singlechip, the slave singlechip stops receiving and is switched to a sending state;

each time the bus busy flag SBus _ TxBusy is cleared, the master singlechip and the slave singlechip can both select whether to switch the receiving state and the sending state, that is, the master singlechip and the slave singlechip can be used as a receiving party, and when the sending party finishes sending, the master singlechip and the slave singlechip can select whether to respond, and if not, the sending party can continue sending.

Compared with the prior art, the utility model has the advantages of:

compared with the existing communication mode, fewer IO ports and cost can be used, effective transmission of data between the two single-chip microcomputers is achieved, communication is more reliable, the situation of data confusion cannot occur, and the data transmission rate is obviously improved.

Drawings

FIG. 1 is a schematic view of the connection of the components of the present invention;

fig. 2 is a schematic circuit diagram of a main single chip computer in an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of the slave single chip in the embodiment of the present invention.

Detailed Description

The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments described below are by way of example only, and other obvious variations will occur to those skilled in the art.

Referring to fig. 1, a single IO mouth both-way communication structure of singlechip, its characterized in that includes main circuit board, main singlechip, follows singlechip, power module, lithium cell group and protection resistance, power module's input is connected with the output of lithium cell group, power module's output and main circuit board are connected, supply power for main circuit board, main singlechip and from the singlechip all with main circuit board electric connection, main singlechip and from the singlechip carry out the communication connection through single IO interface, two IO mouths that main singlechip and the communication of following the singlechip are connected when connecting, and it has protection resistance to establish ties between, and protection resistance is 1K.

Referring to fig. 2-3, in the present embodiment, the 8 th pin TX of the master single chip U1 is used as a communication port, and the line led out by the 1K resistor is connected to the pin of the slave single chip U2 used as the communication port; and the 3 rd pin P1.3 of the slave singlechip U2 is connected with a wire led out by the 1K resistor, so that the communication connection between the master singlechip U1 and the slave singlechip U2 is realized.

The data transmission mode of this embodiment is:

the example takes the time of maintaining high and low levels as a signal when transmitting data, and the specific process is as follows: when starting to transmit, the host maintains the low level for 4.5ms before transmitting the effective data, and then switches to the high level to maintain 2ms as the start bit. When transmitting data bits, with the time of low level as a reference, the data of 1: 250us 6 ═ 1.5 ms; data of 0: 250us 2-500 us, after the low level time of each bit of data is finished, maintaining the high level of 500us as the mark of the end of the transmission of the bit of data, and entering a receiving state after the data frame is transmitted for the designated length;

in the embodiment, since the data is sent from the low order to the high order, the received data is opposite to the sent data, and the transposition processing is required;

in order to ensure the accuracy of the communication time of the master singlechip and the slave singlechip, the master singlechip U1 and the slave singlechip U2 are both provided with timer interrupt of the same time, in the embodiment, the timer interrupt of 250us is set, and the value can be changed according to specific use, so that data omission is avoided;

meanwhile, if the master singlechip U1 or the slave singlechip U2 does not receive a response in the receiving state, the receiving is skipped and the transmission is continued, specifically, according to the preset transmission frequency, when the transmission frequency is determined, the length of the response needs to be considered, the receiving time is reserved, and meanwhile, the condition that no response enters a dead state is avoided.

It is worth explaining, the singlechip model in this embodiment only is as realizing this embodiment, and it is not as right the utility model discloses a restriction, the utility model provides a single IO mouth two-way communication structure of singlechip can realize through the ordinary IO mouth of arbitrary singlechip.

The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the principles of the present invention may be applied to any other embodiment without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. The utility model provides a single IO mouth both way communication structure of singlechip, its characterized in that includes main circuit board, main singlechip, follows singlechip, power module, lithium cell group and protective resistor, power module's input is connected with the output of lithium cell group, power module's output and main circuit board are connected, for main circuit board supplies power, main singlechip and follow the singlechip all with main circuit board electric connection, main singlechip and follow the singlechip carry out the communication through single IO interface and connect, two IO mouths that main singlechip and the communication of following the singlechip are connected when connecting, and it has protective resistor to establish ties between.

2. The single-chip microcomputer single-IO-port bidirectional communication structure of claim 1, wherein only one of the master single-chip microcomputer and the slave single-chip microcomputer is in a data transmission state, and the other one of the master single-chip microcomputer and the slave single-chip microcomputer is in a data reception state.

3. The single-chip microcomputer single-IO-port bidirectional communication structure as recited in claim 2, wherein the resistance value of the protection resistor is 1K.