CN209911956U - Improved double-wire to single-wire conversion module and serial-port to single-wire communication circuit - Google Patents
Improved double-wire to single-wire conversion module and serial-port to single-wire communication circuit Download PDFInfo
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Abstract
The utility model discloses an improved double-wire to single-wire conversion module and a serial port to single-wire communication circuit, wherein the improved double-wire to single-wire conversion module comprises a first buffer, a second buffer, a third buffer, a fourth buffer and a phase inverter; the enable end of the fourth buffer is connected with a high level, the signal input end receives a TXD signal output by the main equipment, and the signal output end outputs a TXD _ O signal to the signal input end of the third buffer, the signal input end of the first buffer and the signal input end of the phase inverter; the enable end of the third buffer is connected with a high level, and the signal output end outputs a BUF signal to the enable end of the second buffer; a signal input end of the second buffer receives a DATA signal output by the bus equipment, and a signal output end outputs an RXD signal to the main equipment; the signal output end of the inverter outputs a TXEN signal to the enabling end of the first buffer; the output end of the first buffer is connected with high level and outputs DATA signal to the bus equipment; the utility model discloses the probability that the master equipment received the wrong data has been reduced.
Description
Technical Field
The utility model relates to a serial ports data processing technology field especially relates to an improved generation double-line changes single line module and serial ports changes single line communication circuit.
Background
The TTL serial port is an interface which is commonly used in the technical field of single-chip microcomputers and used for communication between a peripheral and a main control, the commonly used TTL serial port is provided with a VCC, a GND, a TXD and a RXD four-wire transmission power supply and data, wherein the TXD is used for data transmission, the RXD is used for data reception, the TXD of the main equipment is connected with the RXD of the slave equipment to transmit the data to the slave equipment, the TXD of the slave equipment is connected with the RXD of the main equipment to enable the main equipment to receive the data transmitted from the slave equipment, and the 4-. In some special fields, the DATA throughput is not large during serial communication, more slave devices are provided, the wiring is simple, the wiring harness of a four-wire serial port is provided, so that a three-wire unibus serial port is created, the unibus comprises three lines of VCC, GND and DATA which are respectively connected with a power supply, a ground and a DATA bus, the unibus serial port is time-sharing and half-duplex, namely only a master device can only send DATA to the slave device at the same time, or the master device receives the DATA of the slave device, the sending and receiving processes need to be controlled by the master device, the bus is determined to be used for sending or receiving the DATA at a certain time, the serial ports of some single-chip microcomputers on the market already support a unibus mode, an external circuit is not needed to be hung on the bus by the state of automatically controlling serial port pins inside the single-chip microcomputers, but most of the devices supporting the serial ports have TXD and RXD pins for independently, therefore, a serial-to-single-wire communication circuit is needed, and original dual-wire duplex serial devices are mounted on a single-wire half-duplex single-bus circuit.
The patent application with publication number CN108874705A discloses a serial-to-single-wire communication circuit, which comprises a power supply module for supplying power, wherein the power supply module is connected with a wireless module for wirelessly transmitting data, the wireless module is connected with a data selection module for selecting a data channel, the data selection module is connected with a USB-to-serial module for wired transmission, the data selection module is connected with a double-wire-to-single-wire module for converting a duplex serial port into a time-sharing and half-time-sharing single-wire serial port, and the double-wire-to-single-wire module is connected with a bus interface module for connecting bus equipment.
Although the above patent can solve the problem of converting a two-wire serial port into a single wire, the following problems still exist: as shown in FIG. 1, the TXEN signal received at the first pin 1 of the four-buffer chip U2 is inverted by the TXD _ O signal through the inverter chip U4, such that the TXEN signal is delayed compared to the TXD _ O signal (as shown in FIG. 2) due to the delay of the inverter chip U4; because the signal TXD _ O is the enable signal for the second buffer of the quad buffer chip U2 and the TXEN signal is the enable signal for the first buffer of the quad buffer chip U2, the second buffer of the quad buffer chip U2 is turned on faster than the first buffer, so that when the TXD _ O signal goes from low to high, the first buffer (i.e., the output channel) of the quad buffer chip U2 is not turned off (i.e., the first buffer outputs the DATA signal), the second buffer (i.e., the input channel) is already turned on, and the DATA terminal of the second buffer receives the DATA signal output by the first buffer to the bus device; also, because there is a delay in the first buffer of the four-buffer chip U2, the DATA signal output by the first buffer of the four-buffer chip U2 is delayed from the TXD _ O signal input thereto (as shown in FIG. 2), so when the TXD _ O signal changes from low to high, the output of the first buffer of the four-buffer chip U2 continues to output low for a period of time, resulting in the DATA terminal of the second buffer of the four-buffer chip U2 receiving low and the RXD terminal of the second buffer receiving low on a transition, which in turn results in the master misinterpreting as receiving DATA from the bus device, resulting in a false determination (as shown in FIGS. 3 and 4).
SUMMERY OF THE UTILITY MODEL
The utility model discloses a first purpose aims at realizing an improved generation double-line changes single line module, reduces the probability that phase inverter chip time delay and first buffer time delay lead to the master equipment to receive wrong data.
The utility model discloses a first purpose is realized by following technical scheme:
an improved double-wire to single-wire module comprises a first buffer, a second buffer, a third buffer, a fourth buffer and an inverter; the enable end of the fourth buffer is connected with a high level, the signal input end receives a TXD signal output by the main equipment, and the signal output end outputs a TXD _ O signal to the signal input end of the third buffer, the signal input end of the first buffer and the signal input end of the phase inverter; the enable end of the third buffer is connected with a high level, and the signal output end outputs a BUF signal to the enable end of the second buffer; a signal input end of the second buffer receives a DATA signal output by the bus equipment, and a signal output end outputs an RXD signal to the main equipment; the signal output end of the inverter outputs a TXEN signal to the enabling end of the first buffer; the output terminal of the first buffer is connected with high level and outputs DATA signal to the bus device.
Further, the delay of the first buffer is less than or equal to the delay of the third buffer, or the delay of the first buffer is greater than the delay of the third buffer, and the improved dual-line to single-line module further includes a delay, and the delay is connected between the output end of the inverter and the enable end of the first buffer.
Further, the delayer is a capacitor; one end of the capacitor is connected with the output end of the phase inverter and the enabling end of the first buffer, and the other end of the capacitor is grounded; the capacitance value of the capacitor is greater than or equal to a critical capacitance value; when the capacitance value of the capacitor is equal to the critical capacitance value, the DATA signal output by the first buffer is delayed by the TXD _ O signal compared with the BUF signal output by the third buffer; when the capacitance value of the capacitor is larger than the critical capacitance value, the delay of the DATA signal output by the first buffer compared with the TXD _ O signal is smaller than the delay of the BUF signal output by the third buffer compared with the TXD _ O signal.
As a specific implementation, the first buffer, the second buffer, the third buffer, and the fourth buffer are implemented by four buffers in a four-buffer chip; the model of the four-buffer chip is 74HC 126; the inverter is realized by an inverter chip, and the model of the inverter chip is 74HC1G 04.
Further, the critical capacitance value is greater than 0nF and less than 100 nF.
As a specific embodiment, the capacitance value of said capacitor is equal to 100 nF.
Further, the improved two-wire to one-wire module further comprises a fourth resistor and a sixth resistor; the enable end of the third buffer and the enable end of the fourth buffer are connected with +5V voltage through the sixth resistor; the output end of the first buffer is connected with +5V voltage through the fourth resistor.
As a specific embodiment, part or all of the first buffer, the second buffer, the third buffer and the fourth buffer are implemented by four buffers in a buffer chip.
As a specific embodiment, the inverter is implemented by an inverter chip.
The utility model discloses a second purpose aims at realizing that a serial ports that adopts above-mentioned improved generation double-line to change single line module changes single line communication circuit.
The second purpose of the utility model is realized by the following technical scheme:
a serial port-to-single line communication circuit comprises the improved double-to-single line module, a power module, a wireless module, a USB-to-serial port module, a data selection module and a bus interface module; the wireless module and the USB-to-serial port module are main devices; the power supply module is electrically connected with the wireless module, the USB-to-serial port module, the data selection module, the improved double-wire-to-single-wire module and the bus interface module and is used for supplying power to the wireless module, the USB-to-serial port module, the data selection module, the improved double-wire-to-single-wire module and the bus interface module; the data selection module is electrically connected with the wireless module and the USB-to-serial port module and is used for selecting a TXD signal accessed to the wireless module or the USB-to-serial port module; the improved double-wire to single-wire conversion module is electrically connected with the DATA selection module, the wireless module, the USB to serial port module and the bus interface module, receives the TXD signal output by the DATA selection module, and outputs a DATA signal to the bus equipment through the bus interface module, or receives the DATA signal from the bus equipment through the bus interface module and outputs an RXD signal to the wireless module or the USB to serial port module.
The utility model discloses beneficial effect:
the utility model discloses a TXD _ O is for the enable end of second buffer as the enable signal output of second buffer through the BUF signal after the third buffer delay for the DATA signal of first buffer output becomes before the high level or the BUF signal becomes the high level from the low level at BUF signal, become the high level from the low level, make the main equipment can not receive the jump signal of the low level of first buffer output, reduce the probability that the error DATA was received to phase inverter chip delay and first buffer delay lead to the main equipment. Further, the utility model discloses the delay time of third buffer is more than or equal to first buffer delay time for the DATA signal of first buffer output becomes before the high level or simultaneously from the low level at the BUF signal, becomes the high level from the low level, makes the main equipment can not receive the low level jump signal of first buffer output, or, the utility model discloses the delay time of third buffer is less than the delay time of first buffer, and the delay of the DATA signal of first buffer output has been shortened to the time delay, makes the DATA signal of first buffer output before the BUF signal becomes the high level from the low level or simultaneously, becomes the high level from the low level, reduces the probability that the wrong DATA was received to main equipment to phase inverter chip delay and first buffer delay. Further, the utility model discloses a electric capacity is as the delayer, shortens the time delay of the DATA signal of first buffer output, through adopting the electric capacity that the capacitance value is greater than or equal to critical capacitance value for the DATA signal of first buffer output becomes the high level from the low level before or simultaneously at BUF signal change from the low level, becomes the high level from the low level, makes the main equipment can not receive the low level jump signal of first buffer output or. Further, the utility model discloses a serial ports is built to improved generation double-line commentaries on classics single line module and is changeed single line circuit, when carrying the single bus circuit of single line half-duplex with the serial devices mount of double-line duplex, reduces the probability that the host equipment received the wrong data.
Drawings
In order to more clearly illustrate the embodiments of the present invention, the drawings used in the embodiments will be briefly described below. The drawings in the following description are only examples of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a circuit schematic of a prior art two-wire to single-wire module;
FIG. 2 is a timing diagram of the prior art TXD _ O signal, the TXEN signal, the DATA signal, and the RXD signal;
FIG. 3 is a waveform diagram of a simulation of a TXD _ O signal and an RXD signal of the prior art;
FIG. 4 is a partial enlarged view of a low level transition signal portion of a prior art RXD signal;
fig. 5 is a block diagram of an improved dual-line to single-line module according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a modified module for converting two lines to a single line according to an embodiment of the present invention;
FIG. 7 is a timing diagram of the TXD _ O signal, the TXEN signal, the DATA signal, the BUF signal, and the RXD signal when the enable terminal of the first buffer is not connected to the capacitor C according to one embodiment of the present invention;
FIG. 8 is a timing diagram of the TXD _ O signal, the TXEN signal, the DATA signal, the BUF signal, and the RXD signal when the termination capacitor C is enabled for the first buffer according to one embodiment of the present invention;
fig. 9 is a waveform diagram of an RXD signal according to an embodiment of the present invention;
fig. 10 is a timing diagram of the TXD _ O signal, the TXEN signal, the DATA signal, the BUF signal, and the RXD signal when the delay of the third buffer is greater than the delay of the first buffer according to an embodiment of the present invention;
FIG. 11 is a timing diagram of the TXD _ O signal, the TXEN signal, the DATA signal, the BUF signal, and the RXD signal when the delay of the third buffer equals the delay of the first buffer according to an embodiment of the present invention;
fig. 12 is a timing diagram of the four TXD _ O signals, the TXEN signal, the DATA signal, the BUF signal, and the RXD signal according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings. In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 5, an improved serial-to-single line communication circuit includes a power module, a wireless module, a USB-to-serial module, a data selection module, an improved dual-to-single line module, and a bus interface module; the power supply module is electrically connected with the wireless module, the USB-to-serial port module, the data selection module, the improved double-wire-to-single-wire module and the bus interface module and is used for supplying power to the wireless module, the data selection module, the USB-to-serial port module, the improved double-wire-to-single-wire module and the bus interface module; the data selection module is electrically connected with the wireless module and the USB serial-to-serial module and is used for selecting a TXD signal accessed to the wireless module or the USB serial-to-serial module (in this embodiment, the wireless module and the USB serial-to-serial module are main devices); the improved dual-line to single-line conversion module is electrically connected with the DATA selection module, the wireless module, the USB to serial port module and the bus interface module, receives TXD signals output by the DATA selection module, outputs DATA signals and outputs the DATA signals to the bus equipment through the bus interface module, or receives DATA signals from the bus equipment through the bus interface module and outputs RXD signals to the wireless module or the USB to serial port module.
In the embodiment, the power supply module outputs +5V voltage to the improved double-wire to single-wire module; the wireless module is a Bluetooth module; the data selection module judges whether to access a USB-to-serial port signal or a signal of the wireless module through a USB upper port of the USB-to-serial port module; the improved double-wire to single-wire module is used for converting a duplex serial port into a time-sharing half-duplex single-wire serial port.
In other embodiments, the wireless module is a wireless transmission module such as a WIFI module or a 433 module.
As shown in fig. 6, in the present embodiment, the improved dual-wire to single-wire module includes a four-buffer chip U2, an inverter chip U4, a time delay, a fourth resistor R4, a sixth resistor R6, and a seventh resistor R7; the four-buffer chip U2 includes a first buffer, a second buffer, a third buffer, and a fourth buffer; the inverter chip U4 includes an inverter; the delayer is a capacitor C; the model of the four-buffer chip U2 is 74HC126, and the model of the inverter chip U4 is 74HC1G 04; the capacitance value of the capacitor C is 100 nF; the resistances of the fourth resistor R4, the sixth resistor R6 and the seventh resistor R7 are all 10K Ω.
As shown in fig. 6, the enable terminal 4OE of the fourth buffer is connected to +5V through a sixth resistor R6, the signal input terminal 4A receives the TXD signal output by the data selection module and output by the wireless module or the USB serial-to-serial module, and the signal output terminal 4Y outputs a TXD _ O signal to the signal input terminal 3A of the third buffer, the signal input terminal 1A of the first buffer, and the signal input terminal a of the inverter chip U4; the enable end 3OE of the third buffer is electrically connected with the enable end 4OE of the fourth buffer, and the signal output end 3Y outputs a BUF signal to the enable end 2OE of the second buffer; a signal input end 2A of the second buffer receives a DATA signal received by the bus interface module from the bus equipment, and a signal output end 2Y outputs an RXD signal to the wireless module or the USB serial-to-serial port module; a signal input end A of the inverter chip U4 is connected with +5V voltage through a seventh resistor R7, and a signal output end Y outputs a TXEN signal to an enabling end 1OE of the first buffer and one end of a capacitor C; the output end Y of the first buffer is electrically connected with one end of a fourth resistor R4 and the bus interface module, the other end of the fourth resistor R4 is connected with +5V voltage, and the output end Y of the first buffer outputs a DATA signal to the bus interface module; the other end of the capacitor C is grounded.
In the present embodiment, the enable terminal 30E of the third buffer and the enable terminal 40E of the fourth buffer are connected to the voltage of +5V through the sixth resistor R6; the enable terminals 30E and 40E of the third and fourth buffers are pulled up to a high level to be turned on.
In this embodiment, because there is the time delay in the third buffer, so there is the time delay in the BUF signal of third buffer output compared TXD _ O signal, because the BUF signal is the enable signal of second buffer again, the speed of second buffer disconnection in the utility model is slow compared with the speed of second buffer disconnection among the prior art, compares prior art, the utility model discloses an enable end 2OE of second buffer is exported with the BUF signal of TXD _ O after the time delay to the third buffer, has shortened the time difference between first buffer switch-on and the second buffer disconnection.
In this embodiment, the delay of the first buffer pair TXD _ O is greater than the delay of the third buffer pair TXD _ O; as shown in fig. 7, when the enable terminal 1OE of the first buffer does not have the capacitor C, and the TXD _ O changes from low level to high level, the DATA signal output by the first buffer does not yet change from low level to high level, and the BUF signal output by the third buffer changes from low level to high level, so that the second buffer is turned on before the DATA signal output by the first buffer changes to high level, the second buffer receives the low level DATA signal output by the first buffer, and when the TXD _ O changes from low level to high level, the second buffer receives the low level transition signal output by the first buffer and transmits the RXD signal including the low level transition signal to the host device (wireless module or USB serial port module), so that the RXD signal received by the host device includes the low level signal, and the host device mistakenly considers that the low level DATA transition is received, and in fact the low level signal is the signal output by the output channel (i.e. the first buffer), a signal that is not to be sent by the bus device to the master device; as shown in fig. 8, when the enable terminal 1OE of the first buffer is connected to the capacitor C, since the capacitor C is discharged when the TXEN signal changes from high level to low level, when the enable terminal 1OE of the first buffer is connected to the capacitor C, the time for the TXEN signal to maintain high level before the TXEN signal changes to low level is longer than when the enable terminal 1OE of the first buffer is not connected to the capacitor C, the time for the TXEN signal to maintain high level is longer, the driving force of the first buffer is enhanced, and the ramp-up time for the DATA signal output from the first buffer to change from low level to high level is shortened, that is, when the enable terminal 1OE of the first buffer is connected to the capacitor C, the time for the DATA signal output from the first buffer to change from low level to high level is shortened than when the enable terminal 1OE of the first buffer is not connected to the capacitor C, and before the BUF signal changes to high level (i.e., the second buffer is turned on), the DATA signal has already gone high, so the second buffer does not output a low transition signal.
In the present embodiment, the capacitance value of the capacitor C is 100nF, which is larger than the critical capacitance value; the critical capacitance value is the capacitance value of the capacitor C which makes the DATA signal change from low level to high level and is synchronous with the BUF signal change from low level to high level, and the critical capacitance value is larger than OnF and smaller than 100 nF.
In this embodiment, the BUF signal of TXD _ O delayed by the third buffer is output to the enable terminal 2OE of the second buffer, and the delay of the capacitor C for the TXEN signal increases the ramp rate of the DATA signal, so that the DATA signal output by the first buffer becomes high before the BUF signal changes from low level to high level, i.e., the second buffer is turned on, and even if the TXEN signal has a delay compared with the TXD _ O signal, the master device does not receive the low-level transition signal when the TXD _ O signal changes from low level to high level (as shown in fig. 9).
Example two
The difference between this embodiment and the first embodiment is: the first buffer, the second buffer, the third buffer and the fourth buffer are not realized by four buffers on a four-buffer chip, but are four buffers which are manufactured separately.
EXAMPLE III
The difference between this embodiment and the second embodiment is: the delay of the third buffer is greater than or equal to the delay of the first buffer; the first buffer enable end is not connected with the capacitor C.
As shown in fig. 10, when the delay of the third buffer is greater than that of the first buffer, the DATA signal has changed from the low level to the high level before the BUF signal changes from the low level to the high level, and the second buffer does not output the low-level transition signal.
As shown in fig. 11, when the delay time of the third buffer is equal to that of the first buffer, the BUF signal changes from a low level to a high level while the DATA signal changes from a low level to a high level, and the second buffer does not output a low-level transition signal.
EXAMPLE III
The difference between this embodiment and the first embodiment is: the capacitance value of the capacitor C is a critical capacitance value.
As shown in fig. 12, in the present embodiment, the BUF signal changes from the low level to the high level at the same time as the DATA signal changes from the low level to the high level, and the second buffer does not output the low-level transition signal.
Claims (10)
1. An improved generation double-line changes single line module which characterized in that: comprises a first buffer, a second buffer, a third buffer, a fourth buffer and an inverter; the enable end of the fourth buffer is connected with a high level, the signal input end receives a TXD signal output by the main equipment, and the signal output end outputs a TXD _0 signal to the signal input end of the third buffer, the signal input end of the first buffer and the signal input end of the phase inverter; the enable end of the third buffer is connected with a high level, and the signal output end outputs a BUF signal to the enable end of the second buffer; a signal input end of the second buffer receives a DATA signal output by the bus equipment, and a signal output end outputs an RXD signal to the main equipment; the signal output end of the inverter outputs a TXEN signal to the enabling end of the first buffer; the output terminal of the first buffer is connected with high level and outputs DATA signal to the bus device.
2. The improved two-wire to one-wire module of claim 1, wherein: the delay of the first buffer is less than or equal to the delay of the third buffer, or the delay of the first buffer is greater than the delay of the third buffer; the improved double-wire to single-wire module further comprises a delayer, and the delayer is connected between the output end of the phase inverter and the enabling end of the first buffer.
3. The improved two-wire to one-wire module of claim 2, wherein: the delayer is a capacitor; one end of the capacitor is connected with the output end of the phase inverter and the enabling end of the first buffer, and the other end of the capacitor is grounded; the capacitance value of the capacitor is greater than or equal to a critical capacitance value; when the capacitance value of the capacitor is equal to the critical capacitance value, the DATA signal output by the first buffer is delayed by the TXD _0 signal compared with the BUF signal output by the third buffer; when the capacitance value of the capacitor is larger than the critical capacitance value, the delay of the DATA signal output by the first buffer compared with the TXD _0 signal is smaller than the delay of the BUF signal output by the third buffer compared with the TXD _0 signal.
4. The improved two-wire to one-wire module of claim 3, wherein: the first buffer, the second buffer, the third buffer and the fourth buffer are realized by four buffers in a four-buffer chip; the model of the four-buffer chip is 74HC 126; the inverter is realized by an inverter chip, and the model of the inverter chip is 74HClG 04.
5. The improved two-wire to one-wire module of claim 4, wherein: the critical capacitance value is greater than OnF and less than 100 nF.
6. The improved two-wire to one-wire module of claim 5, wherein: the capacitance value of said capacitor is equal to 100 nF.
7. The improved two-wire to one-wire module according to any one of claims 1 to 6, wherein: the circuit also comprises a fourth resistor and a sixth resistor; the enable end of the third buffer and the enable end of the fourth buffer are connected with +5V voltage through the sixth resistor; the output end of the first buffer is connected with +5V voltage through the fourth resistor.
8. The improved two-wire to one-wire module according to any one of claims 1 to 3, wherein: and part or all of the first buffer, the second buffer, the third buffer and the fourth buffer are realized by buffers in a buffer chip.
9. The improved two-wire to one-wire module according to any one of claims 1 to 3, wherein: the inverter is implemented by an inverter chip.
10. An improved serial-to-single wire communication circuit using the improved two-to-single wire module of any one of claims 1-9, wherein: the USB interface module is connected with the USB interface module through a USB interface; the wireless module and the USB-to-serial port module are main devices; the power supply module is electrically connected with the wireless module, the USB-to-serial port module, the data selection module, the improved double-wire-to-single-wire module and the bus interface module and is used for supplying power to the wireless module, the USB-to-serial port module, the data selection module, the improved double-wire-to-single-wire module and the bus interface module; the data selection module is electrically connected with the wireless module and the USB-to-serial port module and is used for selecting a TXD signal accessed to the wireless module or the USB-to-serial port module; the improved double-wire to single-wire conversion module is electrically connected with the DATA selection module, the wireless module, the USB to serial port module and the bus interface module, receives the TXD signal output by the DATA selection module, and outputs a DATA signal to the bus equipment through the bus interface module, or receives the DATA signal from the bus equipment through the bus interface module and outputs an RXD signal to the wireless module or the USB to serial port module.
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| WO2022000813A1 (en) * | 2020-06-30 | 2022-01-06 | 上海美仁半导体有限公司 | Signal conversion method, chip, and household appliance |
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| WO2022000813A1 (en) * | 2020-06-30 | 2022-01-06 | 上海美仁半导体有限公司 | Signal conversion method, chip, and household appliance |
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