CN111858459B

CN111858459B - Processor and computer

Info

Publication number: CN111858459B
Application number: CN202010521904.4A
Authority: CN
Inventors: 刘义; 黄维; 冯雷
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-06-10
Filing date: 2020-06-10
Publication date: 2022-08-16
Anticipated expiration: 2040-06-10
Also published as: CN111858459A

Abstract

The application provides a processor and a computer, which comprises a plurality of Physical Coding Sublayers (PCS), at least one physical medium adaptation layer (PMA) and a protocol selection module; the high-speed transmission protocols supported by the PCS are different; the protocol selection module is to configure a connected PCS for each of the at least one PMA. Each of the plurality of PCS may support a different high speed transmission protocol from each other, and each PMA may establish a connection with the plurality of PCS. The protocol selection module is used for configuring the PCS connected with each PMA and the high-speed transmission protocol corresponding to the PCS for each PMA, so that the high-speed transmission protocol supported by a line connected from the PMA to the outside of the processor can be switched, the processor can be connected with more high-speed transmission protocol devices or other processors, and the application range of the processor is improved.

Description

Processor and computer

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a processor and a computer.

Background

The same Central Processing Unit (CPU) generally needs to support multiple high-speed transmission protocol devices or interconnect with other processors in different application scenarios. However, in the existing CPU, the corresponding relationship between the high-speed transmission protocol and the Physical Medium adaptation layer (PMA for short) is often fixed, so that once the CPU is manufactured, the supported high-speed transmission protocol device is usually single, and the application range of the CPU is reduced.

Disclosure of Invention

An object of the present invention is to provide a processor and a computer, so as to solve the problem of low application range of the processor in the prior art.

In a first aspect, an embodiment of the present application provides a processor, including a plurality of physical coding sublayers PCS, at least one physical medium adaptation layer PMA, and a protocol selection module; wherein, the high-speed transmission protocols supported by the PCS are different; the protocol selection module is to configure a connected PCS for each of the at least one PMA.

In the above-described embodiments, each of the plurality of PCSs may support a different high-speed transmission protocol from each other, and each PMA may establish a connection with the plurality of PCSs. The protocol selection module is used for configuring the PCS connected with each PMA and the high-speed transmission protocol corresponding to the PCS for each PMA, so that the high-speed transmission protocol supported by a line connected from the PMA to the outside of the processor can be switched, the processor can be connected with more high-speed transmission protocol devices or other processors, and the application range of the processor is improved.

In one possible design, each PCS of the plurality of PCSs is connected to the at least one PMA via the protocol selection module via a respective at least one set of buses, wherein, for the each PCS, one set of buses of the at least one set of buses corresponds to the at least one PMA; the protocol selection module is used for receiving a protocol selection signal input by a user and selecting a PCS corresponding to the protocol selection signal from PCS correspondingly connected with each PMA for each PMA in the at least one PMA.

In the above embodiments, each PCS may include one or more buses, and each of the buses in the plurality of buses of the PCS may be respectively connected to different PMAs, that is, each PMA may be connected to a plurality of PCS. For each PMA, the protocol selection module may determine, based on a protocol selection signal input by a user, that the PMA is currently connected to one of the PCS's, such that switching may be achieved for a high speed transmission protocol supported by a line from the PMA connected to the processor.

In one possible design, the system further comprises a software configuration module and a software configuration path, wherein the software configuration module is connected with the protocol selection module through the software configuration path; the protocol selection signal is transmitted to the protocol selection module through the software configuration module and the software configuration path.

In the above embodiment, the user may send the protocol selection signal to the protocol selection module through the software configuration module, so that the user can control the protocol selection module more conveniently.

In one possible design, the software configuration module includes a reset register and a configurable register; the reset register is used for switching the protocol selection module, the at least one PMA and the software configuration channel between a reset state and a non-reset state according to a state switching signal input by a user; the configurable register is used for receiving a protocol selection signal input by a user and transmitting the protocol selection signal to the protocol selection module through the software configuration path.

In the above embodiment, a user may first control the reset register to enable the protocol selection module, the at least one PMA, and the software configuration path to be in a reset state, and then input a protocol selection signal to be implemented by the user through the configurable register, so that the PCS corresponding to the protocol selection signal to be implemented is connected to the PMA in the reset state, thereby effectively avoiding software misoperation during a process of switching the PCS connected to the PMA.

In one possible design, the software configuration path includes a protocol selection register connected to the configurable register; the protocol selection register is used for transmitting a protocol selection signal sent by the configurable register to the protocol selection module in a reset state; the protocol selection register is also used for receiving and reserving the protocol selection signal sent by the configurable register in a non-reset state and transmitting the reserved protocol selection signal to the protocol selection module in the reset state.

In the above embodiment, the protocol selection signal transmitted by the configurable register to the protocol selection module may be sent to the protocol selection register in the software configuration path, and the protocol selection register may ensure that the protocol selection signal is transmitted to the protocol selection module only in the reset state, thereby avoiding a possibility of sending the protocol selection signal to the protocol selection module in a non-reset state due to a user misoperation.

In one possible design, each PMA of the at least one PMA corresponds to at least one PCS, each of the at least one PCS having an interface corresponding to the PMA; the interface is arranged on the PCS corresponding to each PMA, and the interface arranged on the PCS is connected with the protocol selection module through a corresponding group of buses.

In the above embodiments, the interface corresponding to each PCS and PMA may be provided in the corresponding PCS itself, and the PCS and PMA may be connected by a bus connected by the interface of the PCS itself.

In one possible design, each PMA of the at least one PMA corresponds to at least one PCS, each of the at least one PCS having an interface corresponding to the PMA; the interfaces are all arranged in a protocol selection module, and each PCS in the at least one PCS is connected with the corresponding interface arranged in the protocol selection module through the same group of buses.

In the above embodiment, the interface corresponding to each PCS and the PMA may be disposed in the protocol selection module, so that each PCS in the multiple PCS may be connected to the corresponding interface on the protocol selection module through the same set of buses, which may reduce the number of buses and save cost.

In one possible design, the plurality of PCS's include one or more of a processor CPU interconnect protocol PCS, a high speed serial computer expansion bus standard PCIe PCS, a serial high technology configuration SATA PCS, a universal serial bus USB PCS, an ethernet PCS.

In the above embodiments, the PCS may include one or more of a processor CPU interconnect protocol PCS, a high speed serial computer expansion bus standard PCIe PCS, a serial high technology configuration SATA PCS, a universal serial bus USB PCS, an ethernet PCS, and other types, and the specific type of PCS should not be construed as limiting the application.

In one possible design, a plurality of controllers are further included, the number of the plurality of controllers is the same as the number of the plurality of PCS, and the plurality of controllers correspond to the plurality of PCS one to one.

In one possible design, a processor CPU core is also included, the CPU core being coupled to the various controllers.

In a second aspect, the present application provides a computer, including the processor described above.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 is a block diagram of a schematic architecture of a processor provided by an embodiment of the present application;

FIG. 2 is a schematic block diagram of one embodiment of a processor provided by an embodiment of the present application;

FIG. 3 is a schematic block diagram of another embodiment of a processor provided in an embodiment of the present application;

FIG. 4 is a schematic block diagram of yet another embodiment of a processor provided by an embodiment of the present application;

fig. 5 is a schematic structural block diagram of a computer provided in an embodiment of the present application.

A processor 100; PCS 110; a protocol selection module 120; the PMA 130; a software configuration module 140; a software configuration path 150; a controller 160; a CPU core 170; a circuit board slot 210.

Detailed Description

Compared with the embodiment, the corresponding relation between the high-speed transmission protocol of the existing CPU and the PMA is often fixed, so that once the CPU is manufactured, the supported high-speed transmission protocol equipment is generally single, and the application range of the CPU is reduced.

In the processor provided in the embodiment of the present application, each PMA may correspond to multiple PCSs, and a protocol selection module is used to configure a connected PCS and a high-speed transmission protocol corresponding to the PCS for each PMA, so that a high-speed transmission protocol supported by a line connected from the PMA to the outside of the processor may be switched, and thus, the processor may be connected to more high-speed transmission protocol devices or other processors, and an application range of the processor is improved.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Referring to fig. 1, fig. 1 shows a schematic block diagram of a processor 100 according to an embodiment of the present application, where the processor 100 according to the embodiment of the present application includes a plurality of Physical Coding Sublayers (PCS), at least one Physical Medium adaptation layer (PMA), and a protocol selection module 120.

Each PCS 110 of the plurality of PCS 110 supports a different high-speed transmission protocol, and referring to fig. 1, the PCS 110 may include one or more of a central processing unit 100CPU Interconnect protocol PCS 110, a high-speed Serial computer extended Bus (PCIe) PCS 110, a Serial Advanced Technology Attachment (SATA) PCS 110, a Universal Serial Bus (USB) PCS 110, and an ethernet PCS 110. The PCS 110 corresponds to a respective high-speed transmission protocol, for example, the PCIe PCS 110 corresponds to a PCIe high-speed transmission protocol, the SATA PCS 110 corresponds to a SATA high-speed transmission protocol, and the ethernet PCS 110 corresponds to a gigabit ethernet high-speed transmission protocol. The PMA130 may be used to perform parallel-to-serial/serial-to-parallel conversion of the bus.

The protocol selection module 120 is to configure the connected PCS 110 for each PMA130 of the at least one PMA 130. For each PCS 110 of the plurality of PCS 110, may be connected to the PMA130 via the protocol selection module 120 via a respective bus; the PCS 110 may be directly connected to the PMA130 through the corresponding bus, and the protocol selection module 120 may control the connection of each PMA130 to a plurality of PCS 110.

For convenience of description, it is not illustrated that each PCS 110 may be connected to the PMA130 through the protocol selection module 120 via a respective bus: the number of bus groups corresponding to each PCS 110 may be different, for example, the PCIe PCS 110 may have four groups of buses, and the four groups of buses are respectively connected to four different PMA130 via the protocol selection module 120; the SATA PCS 110 may have two sets of buses, which are respectively connected to two different PMA130 via the protocol selection module 120; the USB PCS 110 may have a set of buses connected to a PMA130 via the protocol selection module 120. Wherein each group of buses may comprise four buses lane.

The four sets of buses of the PCIe PCS 110 may be connected to the first PMA130, the second PMA130, the third PMA130, and the fourth PMA130, respectively, provided that the number of PMA130 is four; the two groups of buses of the SATA PCS 110 may be set by a user to be connected to any two of the four PMA130, but are not set to be connected to the first PMA130 and the fourth PMA 130; the set of buses of the USB PCS 110 may be connected to any one of the four PMAs 130, but not to the third PMA130, via a user setting.

Thus, the first PMA130 may be connected with a PCIe PCS 110 or a SATA PCS 110;

the second PMA130 is connected to the PCIe PCS 110;

the third PMA130 may be connected to the PCIe PCS 110 or USB PCS 110;

the fourth PMA130 may be connected to a PCIe PCS 110 or a SATA PCS 110.

The protocol selection module 120 may receive a protocol selection signal input by a user and determine the PCS 110 to which the first PMA130, the third PMA130 and the fourth PMA130 are respectively connected according to the protocol selection signal. For example, each PCS 110 has a protocol selection signal corresponding thereto, such as 010 corresponding to PCIe PCS and 011 corresponding to SATA PCS. When the protocol selection module 120 selects the PCS 110 for the first PMA130, it may obtain a protocol selection signal corresponding to the first PMA130, and determine that the first PMA130 is connected to a PCIe PCS or a SATA PCS according to a specific value of the protocol selection signal. Optionally, the protocol selection signal may carry an identity of the PMA, which characterizes the PMA to which the protocol selection signal specifically corresponds.

Optionally, in a specific embodiment, the protocol selection signal received by the protocol selection module 120 may also be transmitted from a circuit board slot 210 connected to the external device, and the circuit board slot 210 may be provided with a sensing chip for sensing a device type connected to the slot and transmitting the device type to the protocol selection module 120 in the form of the protocol selection signal, so that the protocol selection module 120 determines, for the PMA130, the PCS 110 corresponding to the device type of the external device. In the embodiments of the present application, the specific source of the protocol selection signal should not be construed as a limitation to the present application.

In the above embodiment, each PMA130 may be configured with the connected PCS 110 by using the protocol selection module 120, so that the high-speed transmission protocol supported by the line connected from the PMA130 to the outside of the processor 100 may be switched, so that the processor 100 may be connected to more high-speed transmission protocol devices or other processors 100, and the application range of the processor 100 may be increased.

Referring to fig. 2, in an embodiment provided in the present application, the processor 100 may further include a software configuration module 140 and a software configuration path 150, where the software configuration module 140 is connected to the protocol selection module 120 via the software configuration path 150. The protocol selection signal may be input by a user via software configuration module 140 and communicated to protocol selection module 120 via software configuration path 150.

Optionally, the software configuration module 140 may include a reset register (not shown) and a configurable register (not shown). The reset register is used for switching the protocol selection module 120, the PMA130 and the software configuration path 150 between a reset state and a non-reset state according to a state switching signal input by a user; the configurable register is used for receiving a protocol selection signal input by a user and transmitting the protocol selection signal to the protocol selection module 120 through the software configuration path 150.

Optionally, the software configuration path 150 may include a protocol selection register (not shown), and the above-mentioned configurable register may be connected to the protocol selection register. The protocol selection register is configured to transmit a protocol selection signal sent by the configurable register to the protocol selection module 120 in a reset state; in a non-reset state, the protocol selection signal sent by the configurable register is received and retained, and in a reset state, the retained protocol selection signal is passed to the protocol selection module 120.

Each PMA130 corresponds to at least one PCS 110, and each PCS 110 of the at least one PCS 110 has an interface (not shown) corresponding to the PMA 130.

In one embodiment, the above-mentioned interfaces may be disposed on each PCS 110 itself, and each PCS 110 connects a set of buses to the protocol selection module 120 through its own interface, as shown in detail in fig. 2. Each interface corresponding to the PCS 110 and the PMA130 may be disposed in the corresponding PCS 110 itself, and the PCS 110 and the PMA130 may be connected by a bus connected by the interface of the PCS 110 itself.

In another embodiment, the above-mentioned interface may be disposed in the protocol selection module 120, and each PCS 110 may be connected to the corresponding interface disposed in the protocol selection module 120 through the same set of buses, as shown in detail in fig. 3. The interface corresponding to each PCS 110 and the PMA130 may be disposed in the protocol selection module 120, so that each PCS 110 in the multiple PCS 110 may be connected to the corresponding interface on the protocol selection module 120 through the same set of buses, which may reduce the number of buses and save cost.

The interface between the PCS 110 and the PMA130 may transport the following types of interface signals:

configuration path interface signal: the user may signal the PMA130 to be configured according to different protocols and different speed requirements, which is mainly manifested as infrequent changes in value. The configuration path interface signal includes information such as clock frequency of a phase locked loop inside the PMA130, data bit width, and the like. The interface corresponding to the interface signal may be implemented in each PCS 110, or may be implemented in the protocol selection module 120.

Data path interface signals: including data valid signals and data signals, the interface corresponding to the interface signal can be implemented in each PCS 110 and selected by the protocol selection module 120.

Handshake signals: the request/response signals between the PCS 110 and the PMA130 may be selected by the protocol selection module 120.

The PCS 110 controls the interface signals: instructions initiated by the PCS 110, including link power consumption commands, link speed, etc., may be selected by the protocol selection module 120.

Other signals from the PMA130 to the PCS 110.

Referring to fig. 4, in another embodiment of the present application, the processor 100 may further include various controllers 160 and a CPU core 170, and the various controllers 160 may be a CPU interconnect protocol controller 160, a PCIe controller 160, a SATA controller 160, a USB controller 160, and a gigabit ethernet controller 160, respectively. The controllers 160 are connected to the PCS 110. The CPU core 170 is connected to various controllers 160.

Various controllers 160 may be responsible for link training, link management, and transaction processing for CPU core 170 with external devices or other CPUs.

The PCS 110 is responsible for encoding data destined for the PMA130 or decoding data returned from the PMA130, and each protocol has a corresponding PCS 110, since the way the respective protocols are encoded and decoded differs.

The software configuration module 140 is responsible for configuring the various modules based on the requirements of the software.

The protocol selection module 120 selects different high-speed transmission protocols and PCS 110 corresponding to the high-speed transmission protocols based on the configuration of the user.

The PMA130 may operate at different speeds or different high-speed transmission protocols according to different user configurations.

The working principle of the processor 100 provided by the embodiment of the application is as follows:

in the case where software configuration module 140 includes reset and configurable registers, and software configuration path 150 does not include a protocol selection register:

the user may first determine whether the protocol selection module 120, the at least one PMA130 and the software configuration path 150 are in a reset state, if so, the user may directly input a protocol selection signal through the configurable register, the protocol selection signal may be directly transmitted to the protocol selection module 120, and the protocol selection module 120 determines the connected PCS 110 for the PMA130 according to the protocol selection signal. The specific manner in which the protocol selection module 120 determines the connected PCS 110 for a certain PMA130 according to the protocol selection signal input by the user has been described above, and is not described herein again.

If the protocol selection module 120, the at least one PMA130 and the software configuration path 150 are in a non-reset state, a user may first control the reset register to switch the protocol selection module 120, the at least one PMA130 and the software configuration path 150 from the non-reset state to a reset state, and then input a protocol selection signal through the configurable register, where the protocol selection signal may be directly transmitted to the protocol selection module 120, and the protocol selection module 120 determines the connected PCS 110 for the PMA130 according to the protocol selection signal.

The user may first control the reset register to make the protocol selection module 120, the at least one PMA130 and the software configuration path 150 in the reset state, and then input a protocol selection signal to be implemented by the user through the configurable register, so that the PCS 110 corresponding to the protocol selection signal to be implemented is connected with the PMA130 in the reset state, thereby effectively avoiding software misoperation during the process of switching the PCS 110 connected by the PMA 130.

In the case where software configuration module 140 includes reset registers and configurable registers, and software configuration path 150 includes protocol selection registers:

the user can input the protocol selection signal through the configurable register at any time, and the protocol selection signal input by the user is transmitted to the protocol selection register.

If the protocol selection register receives the protocol selection signal, the software configuration path 150 is in a reset state, the protocol selection register sends the protocol selection signal to the protocol selection module 120, and the protocol selection module 120 determines the connected PCS 110 for the PMA130 according to the protocol selection signal.

If the protocol selection register receives the protocol selection signal, the software configuration path 150 is in a non-reset state, the protocol selection register retains the protocol selection signal, and after the software configuration path 150 is switched from the non-reset state to the reset state, the retained protocol selection signal is sent to the protocol selection module 120, and the protocol selection module 120 determines the connected PCS 110 for the PMA130 according to the protocol selection signal.

The protocol selection register can ensure that the protocol selection signal is transmitted to the protocol selection module 120 only in the reset state, thereby avoiding the possibility of sending the protocol selection signal to the protocol selection module 120 in the non-reset state caused by misoperation of a user, switching the PCS 110 in the reset state, and avoiding the burr problem and the clock domain problem caused by switching in the non-reset state.

Both of the above cases can be realized when the software configuration path 150 and the functional path are controlled by the same reset signal, or when the software configuration path 150 and the functional path are controlled by different reset signals. Wherein the functional path includes the protocol selection module 120 and the PMA 130.

In one embodiment, instead of using the reset register, only the configurable register may be reserved, and the PCS 110 connected to the PMA130 may be manually switched in the reset state in cooperation with a suitable clock switching module.

The processor 100 provided by the embodiment of the present application can be flexibly configured to use a chip corresponding to a high speed transmission protocol according to application requirements of different external devices, the configuration process is flexible, safe and controllable, and meanwhile, the overhead of hardware is reduced.

Referring to fig. 5, the embodiment of the present application further provides a computer, as shown in fig. 5, including a processor (processor)100, a memory (memory)502 and a bus 503; wherein, the processor 100 and the memory 502 complete the communication with each other through the bus 503; the processor 100 is used for invoking the program instructions in the memory 502, and the processor 100 may be a general-purpose processor including a CPU including a plurality of DIEs, each DIE including at least one CPU core.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A processor comprising a plurality of physical coding sublayers, PCS, at least one physical medium adaptation layer, PMA, and a protocol selection module;

the high-speed transmission protocols supported by the PCS are different; the protocol selection module is to configure a connected PCS for each of the at least one PMA;

each PCS of the plurality of PCS is connected with the at least one PMA through the protocol selection module through at least one set of bus corresponding to the at least one PMA;

the protocol selection module is used for receiving a protocol selection signal input by a user and selecting a PCS corresponding to the protocol selection signal from PCS correspondingly connected with each PMA for each PMA in the at least one PMA.

2. The processor of claim 1, further comprising a software configuration module and a software configuration path, wherein the software configuration module is connected with the protocol selection module via the software configuration path;

the protocol selection signal is transmitted to the protocol selection module through the software configuration module and the software configuration path.

3. The processor of claim 2, wherein the software configuration module comprises a reset register and a configurable register;

the reset register is used for switching the protocol selection module, the at least one PMA and the software configuration channel between a reset state and a non-reset state according to a state switching signal input by a user;

the configurable register is used for receiving a protocol selection signal input by a user and transmitting the protocol selection signal to the protocol selection module through the software configuration path.

4. The processor of claim 3, wherein the software configuration path comprises a protocol selection register coupled to the configurable register;

the protocol selection register is used for transmitting a protocol selection signal sent by the configurable register to the protocol selection module in a reset state;

the protocol selection register is also used for receiving and reserving the protocol selection signal sent by the configurable register in a non-reset state and transmitting the reserved protocol selection signal to the protocol selection module in the reset state.

5. The processor of claim 1, wherein each PMA of the at least one PMA corresponds to at least one PCS, each of the at least one PCS having an interface corresponding to the PMA;

the interface is arranged at a PCS corresponding to each PMA, and the interface arranged at the PCS is connected with the protocol selection module through a corresponding group of buses.

6. The processor of claim 1, wherein each PMA of the at least one PMA corresponds to at least one PCS, each of the at least one PCS having an interface corresponding to the PMA;

the interfaces are all arranged in a protocol selection module, and each PCS in the at least one PCS is connected with the corresponding interface arranged in the protocol selection module through the same group of buses.

7. The processor of claim 1, wherein the plurality of PCS's comprise one or more of a central processing unit, CPU, interconnect protocol, PCS, a PCIe-express serial computer expansion bus standard, a serial advanced technology configuration, SATA, USB, PCS, and an ethernet PCS.

8. The processor according to claim 1, further comprising a plurality of types of controllers, the plurality of types of controllers being the same in number as the plurality of PCS's, the plurality of types of controllers corresponding one-to-one to the plurality of PCS's.

9. The processor of claim 8, further comprising a CPU core, the CPU core being connected to the plurality of controllers.

10. A computer comprising a processor according to any one of claims 1 to 9.