CN101272405B - Receiving equipment, MMIS interface and data interaction method - Google Patents
Receiving equipment, MMIS interface and data interaction method Download PDFInfo
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Abstract
The invention discloses a receiving device, an MMIS interface and a data interaction method, which are used for multiplexing at least two types of interfaces. The receiving device of the invention comprises the MMIS interface used for multiplexing at least two types of interfaces, a receiving module used for receiving indicator signals sent by users, a selecting module used for selecting the interface type and the working mode of a stand-to interface device according to the indicator signals received by the receiving module; a control module used for controlling interface signals of the MMIS interface corresponding to the interface type and the working mode selected by the selecting module and interacting with the interface device. The MMIS interface comprises 11 pins used for multiplexing an SPI, an SDIO and a DVB-TS interface; the 11 pins transmits interface signals corresponding to the current working mode under different working modes of the SPI, the SDIO and the DVB-TS interface.
Description
Technical field
The present invention relates to field of data transmission, particularly relate to a kind of receiving equipment, MMIS interface and data interactive method.
Background technology
Serial peripheral equipment interface SPI (Serial Peripheral Interface) bus system is a kind of synchronous serial Peripheral Interface, allow main equipment and various slave unit with serial mode communicate, exchanges data.There is the branch of monofilar mode and bifilar mode in the SPI system, and is in the majority with the bifilar mode use, supports I
2C bus or universal asynchronous receiving-transmitting bus UART configured port.Referring to shown in Figure 1, based on the SPI bifilar mode, main equipment HOST (being SPI equipment) and slave unit SLAVE are (for example: 4 lines of main use PDA etc.): serial time clock line (SPICLK), main frame input/slave output data line SPISO, main frame output/slave input data line SPISI and the effective slave selection wire of low level SPICS.
Secure digital input/output interface SDIO (Secure Digital I/O) is the socket of SDIO card.SDIO card and SD card are from mechanism, and electrical characteristic parameter, aspects such as signal and software are compatible fully.SDIO generally supports 1bitSD transmission mode and 4bitSD transmission mode.With the 4bitSD transmission mode is example, referring to shown in Figure 2, main equipment HOST (being SDIO equipment) and slave unit SLAVE (for example: 6 signals of main use PDA etc.): clock signal clk, order wire CMD, and 4 data wires, i.e. DAT[3:0].Wherein order wire and data wire are bidirectional signal line.
Support that the multiple interfaces standard is a trend of equipment development.The socket of more than a kind of interface equipment correspondence all is provided at present a lot of equipment, for example: the socket of SDIO interface equipment is provided on the PDA, and the socket of SPI interface equipment.But the interface as the different specification that comprises on the fruit chip is fully discrete, obviously can increase area of chip and number of pin, thereby increase unnecessary cost input.
Summary of the invention
The invention provides a kind of receiving equipment, MMIS interface and data interactive method, with multiplexing at least two types interface.
Receiving equipment of the present invention, comprise: mobile multimedia interface system MMIS interface, be used for multiplexing at least two types interface, multiplexing interface comprises at least with two kinds in the lower interface: serial peripheral equipment interface SPI, secure digital input/output interface SDIO, and digital video broadcasting transport stream interface DVB-TS;
Receiver module is used to receive the index signal that the user sends;
Select module, be used for the index signal received according to receiver module, select the interface type and the mode of operation of the interface equipment of awaiting orders, wherein:
When multiplexing mode of operation was single line SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation was two-wire SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation is four line SPI and four line SDIO, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation was two-wire SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation is four line SPI and DVB-TS, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin,
Or
When multiplexing mode of operation was four line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin;
When mode of operation was single line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was two-wire SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the data input; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for data output; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was four line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the 4th circuit-switched data; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit chip selection signal; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was single line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D2 pin is used for transmission and reads waiting signal;
When mode of operation was four line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit Third Road data or interrupt signal; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was DVB-TS, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the effective enable signal of data; The MMIS_SYNC pin is used for the transmitting synchronous marking signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit the 5th circuit-switched data; The MMIS_D5 pin is used to transmit the 6th circuit-switched data; The MMIS_D6 pin is used to transmit the 7th circuit-switched data; The MMIS_D7 pin is used to transmit the 8th circuit-switched data;
Control module is used to control the MMIS interface to select the interface signal of module selected interface type and mode of operation correspondence, carries out alternately with described interface equipment.
Described single line SPI mode of operation, single line SDIO mode of operation, two-wire SPI mode of operation, four line SDIO mode of operations, and in the interface signal of four line SPI mode of operation correspondences, comprise interrupt signal.
Mobile multimedia interface system MMIS interface of the present invention comprises 11 pins, is used for multiplexing serial peripheral equipment interface SPI, secure digital input/output interface SDIO, and at least two kinds of interfaces among the digital video broadcasting transport stream interface DVB-TS; Described 11 pins are at SPI, SDIO, and under the different working modes of DVB-TS interface, the interface signal of transmission work at present pattern correspondence;
Wherein: when multiplexing mode of operation was single line SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation was two-wire SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation is four line SPI and four line SDIO, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation was two-wire SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation is four line SPI and DVB-TS, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin,
Or
When multiplexing mode of operation was four line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin;
When mode of operation was single line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was two-wire SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the data input; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for data output; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was four line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the 4th circuit-switched data; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit chip selection signal; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was single line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D2 pin is used for transmission and reads waiting signal;
When mode of operation was four line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit Third Road data or interrupt signal; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was DVB-TS, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the effective enable signal of data; The MMIS_SYNC pin is used for the transmitting synchronous marking signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit the 5th circuit-switched data; The MMIS_D5 pin is used to transmit the 6th circuit-switched data; The MMIS_D6 pin is used to transmit the 7th circuit-switched data; The MMIS_D7 pin is used to transmit the 8th circuit-switched data.
In the interface signal of described single line SPI mode of operation, single line SDIO mode of operation, two-wire SPI mode of operation, four line SDIO mode of operations and four line SPI mode of operation correspondences, comprise interrupt signal.
Data interactive method of the present invention, after comprising the following steps: index signal that receiving equipment receives that the user sends, select the interface type and the mode of operation of the interface equipment of awaiting orders according to this index signal, and, carry out alternately with described interface equipment with the interface signal of selected interface type and mode of operation correspondence;
Alternative interface type comprises at least: serial peripheral equipment interface SPI, secure digital input/output interface SDIO, and digital video broadcasting transport stream interface DVB-TS;
When selecting two kinds of interfaces from alternative interface type, the mode of operation of interface is multiplexed with:
When multiplexing mode of operation was single line SPI and single line SDIO, multiplexing mobile multimedia interface system MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation was two-wire SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation is four line SPI and four line SDIO, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation was two-wire SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation is four line SPI and DVB-TS, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin,
Or
When multiplexing mode of operation was four line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin;
When mode of operation was single line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was two-wire SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the data input; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for data output; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was four line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the 4th circuit-switched data; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit chip selection signal; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was single line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D2 pin is used for transmission and reads waiting signal;
When mode of operation was four line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit Third Road data or interrupt signal; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was DVB-TS, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the effective enable signal of data; The MMIS_SYNC pin is used for the transmitting synchronous marking signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit the 5th circuit-switched data; The MMIS_D5 pin is used to transmit the 6th circuit-switched data; The MMIS_D6 pin is used to transmit the 7th circuit-switched data; The MMIS_D7 pin is used to transmit the 8th circuit-switched data.
Beneficial effect of the present invention is as follows:
Receiving equipment of the present invention, MMIS interface and data interactive method under the situation of supporting the polytype interface, have proposed the MMIS interface of reusable multiple interfaces.The present invention is according to the index signal of receiving, the interface type of the interface equipment that selection is awaited orders and mode of operation, and control MMIS interface carries out alternately with the interface signal and the described interface equipment of selected interface type and mode of operation correspondence, thereby realize the multiplexing of all types of interfaces, and then reduced area of chip and number of pin, avoided unnecessary cost input.
Table 1 is the tabulation of MMIS interface capability.By table 1 as seen, SPI, SDIO and DVB-TS interface are by together multiplexing effectively.Under various mode of operations, the interface efficient of MMIS is minimum possibility in the tabulation, and every kind of mode of operation is all supported 16 bits, 32 bit transfer patterns, and under these several mode of operations, data transmission efficiency can be very high.
And the present invention also provides SPI four lineman's operation modes.By table 1 as seen, under four lineman's operation modes, data transfer rate is brought up to 54Mbit/s at SPI, has improved 3 times than the data transfer rate of SPI two-wire mode of operation.
Table 1
Description of drawings
Fig. 1 is for having under the SPI mode of operation annexation figure between main equipment and the slave unit now;
Fig. 2 is for having under the SDIO mode of operation annexation figure between main equipment and the slave unit now;
Fig. 3 is the structural representation of receiving equipment of the present invention;
Fig. 4 is based on the main equipment of MMIS interface and the annexation figure between the slave unit among the present invention;
Fig. 5 is the inventive method flow chart of steps;
Fig. 6 is single line SPI mode of operation of the present invention and single line SDIO mode of operation when multiplexing, the annexation between main equipment and the slave unit;
Fig. 7 is main equipment under the two-wire SPI mode of operation of the present invention and the annexation between the slave unit;
Fig. 8 is the present invention's four line SPI mode of operations and four line SDIO mode of operations when multiplexing, the annexation between main equipment and the slave unit;
Fig. 9 is main equipment under the DVB-TS mode of operation of the present invention and the annexation between the slave unit.
Embodiment
For under the situation of supporting the polytype interface, multiplexing all types of interface, thereby reduce area of chip and number of pin, avoid unnecessary cost input, the invention provides a kind of receiving equipment, it uses mainly as slave unit SLAVE, and referring to shown in Figure 3, it comprises: the receiver module of Xiang Lianing, selection module, control module and MMIS interface successively.
Described MMIS interface (can be described as the mobile multimedia interface system) is used for multiplexing at least two types interface.Further, multiplexing interface comprises following two kinds at least: SPI, SDIO, and DVB-TS interface.
Described receiver module is used to receive the index signal that the user sends.For example: described receiving equipment is a mobile phone, and the user selects " connecting the SDIO interface equipment " in the mobile phone operating system menu, and then receiver module can be received the index signal of connecting the SDIO interface equipment.
Described selection module is used for the index signal received according to receiver module, selects the interface type and the mode of operation of the interface equipment of awaiting orders.
Described control module is used to control the MMIS interface to select the interface signal of module selected interface type and mode of operation correspondence, carries out alternately with described interface equipment.
Based on the MMIS interface, main equipment HOST (being SPI interface equipment, SDIO interface equipment, DVB-TS interface equipment etc.) and slave unit SLAVE are receiving equipment of the present invention (receiving equipment of the present invention is a main frame under the DVB-TS mode of operation), between annexation, referring to shown in Figure 4, the pin that links to each other comprises: the MMIS_CLK pin of MMIS interface, the MMIS_VLD pin of MMIS interface, the MMIS_SYNC pin (optional) of MMIS interface, and other related data transmission pin.
The present invention also provides a kind of MMIS interface, and this MMIS interface can be used as the MMIS interface in the above-mentioned receiving equipment, and it comprises: 11 pins, be used for multiplexing SPI, SDIO, and the DVB-TS interface; Described 11 pins are at SPI, SDIO, and under the different working modes of DVB-TS interface, the interface signal of transmission work at present pattern correspondence.
The present invention also provides a kind of data interactive method, referring to shown in Figure 5, comprises the following steps:
S1, receiving equipment are received the index signal that the user sends.
S2, select the interface type and the mode of operation of the interface equipment of awaiting orders according to this index signal.
The interface type of described interface equipment of awaiting orders can be SPI, SDIO, or the DVB-TS interface.
S3, carry out alternately with the interface signal and the described interface equipment of selected interface type and mode of operation correspondence.
In above-mentioned receiving equipment, MMIS interface and the data interactive method, described SPI comprises: single line SPI mode of operation, two-wire SPI mode of operation and four line SPI mode of operations; Described SDIO comprises: single line SDIO mode of operation and four line SDIO mode of operations; Described DVB-TS interface comprises: the DVB-TS mode of operation.In the SPI of MMIS interface duplex, SDIO and the DVB-TS interface, belong between each mode of operation of distinct interface and have multiplexing relation.For example: have multiplexing relation between single line SPI mode of operation and the single line SDIO mode of operation, have multiplexing relation between single line SPI mode of operation and the four line SDIO mode of operations, have multiplexing relation between single line SPI mode of operation and the DVB-TS mode of operation.
● further, if mode of operation is single line SPI or single line SDIO, the annexation between main equipment HOST and the slave unit SLAVE then, referring to shown in Figure 6, the pin that links to each other comprises: the MMIS_CLK pin of MMIS interface, the MMIS_D3 of MMIS interface (MMIS_CS) pin, the MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin, the MMIS_D1 of MMIS interface (MMIS_IRQ) pin, and the MMIS_D0 of MMIS interface (MMIS_TRXD) MMIS_TXD pin.
In mode of operation is that ginseng is shown in Table 2 under the single line SPI, and corresponding interface signal is defined as follows:
The MMIS_CLK pin of MMIS interface is used for transmit clock signal;
The MMIS_SYNC pin of MMIS interface is used to transmit multiplexed frame frame head index signal;
The MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin is used for bi-directional transfer of data;
The MMIS_D1 of MMIS interface (MMIS_IRQ) pin is used to transmit interrupt signal;
The MMIS_D3 of MMIS interface (MMIS_CS) pin is used to transmit chip selection signal.
In mode of operation is that ginseng is shown in Table 2 under the single line SDIO, and corresponding interface signal is defined as follows:
The MMIS_CLK pin of MMIS interface is used for transmit clock signal;
The MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin is used for the transmission command signal;
The MMIS_SYNC pin of MMIS interface is used to transmit multiplexed frame frame head index signal;
The MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin is used for bi-directional transfer of data;
The MMIS_D1 of MMIS interface (MMIS_IRQ) pin is used to transmit interrupt signal;
The MMIS_D2 of MMIS interface (MMIS_RW) pin is used for transmission and reads waiting signal.
Table 2
By table 2 as seen, MMIS_D0 (MMIS_TRXD/MMIS_TXD) pin of the MMIS_CLK pin of MMIS interface, the MMIS_SYNC pin of MMIS interface, MMIS interface, MMIS_D1 (MMIS_IRQ) pin of MMIS interface are re-used under single line SPI and single line SDIO mode of operation.
All comprise interrupt signal in single line SPI and the single line SDIO mode of operation, be used for after the slave DSR, notifying main frame to receive.
● further, if mode of operation is two-wire SPI, the annexation between main equipment HOST and the slave unit SLAVE then, referring to shown in Figure 7, the pin that links to each other comprises: the MMIS_CLK pin of MMIS interface, the MMIS_D3 of MMIS interface (MMIS_CS) pin, the MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin, the MMIS_SYNC pin of MMIS interface, the MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin, and the MMIS_D1 of MMIS interface (MMIS_IRQ) pin.
Ginseng is shown in Table 3, and the interface signal of two-wire SPI mode of operation correspondence is defined as follows:
The MMIS_CLK pin of MMIS interface is used for transmit clock signal;
The MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin is used for the data input;
The MMIS_SYNC pin of MMIS interface is used to transmit multiplexed frame frame head index signal;
The MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin is used for data output;
The MMIS_D1 of MMIS interface (MMIS_IRQ) pin is used to transmit interrupt signal;
The MMIS_D3 of MMIS interface (MMIS_CS) pin is used to transmit chip selection signal.
Table 3
With the contrast of the single line SDIO mode of operation in table 3 and the table 2, can obtain the multiplexing relation of each pin under two-wire SPI mode of operation and the single line SDIO mode of operation.
Comprise interrupt signal in the two-wire SPI mode of operation, effect is with single line SPI or SDIO mode of operation.
Because the single, double ray mode data throughout of SPI is less, the present invention proposes a kind of four line SPI mode of operations, promptly has 4 data pin bidirectional transmit-receive data.
● further, if mode of operation is four line SPI or four line SDIO, the annexation between main equipment HOST and the slave unit SLAVE then, referring to shown in Figure 8, the pin that links to each other comprises: the MMIS_CLK pin of MMIS interface, the MMIS_D3 of MMIS interface (MMIS_CS) pin, the MMIS_SYNC pin of MMIS interface, the MMIS_D1 of MMIS interface (MMIS_IRQ) pin, the MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin, the MMIS_D2 of MMIS interface (MMIS_RW) pin, the MMIS_D3 of MMIS interface (MMIS CS) pin, and the MMIS_D4 of MMIS interface (MMIS_IRQ) pin.
In mode of operation is that ginseng is shown in Table 4 under the four line SPI, and corresponding interface signal is defined as follows:
The MMIS_CLK pin of MMIS interface is used for transmit clock signal;
The MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin is used to transmit the 4th circuit-switched data;
The MMIS_SYNC pin of MMIS interface is used to transmit multiplexed frame frame head index signal;
The MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin is used to transmit first via data;
The MMIS_D1 of MMIS interface (MMIS_IRQ) pin is used to transmit second circuit-switched data;
The MMIS_D2 of MMIS interface (MMIS_RW) pin is used to transmit the Third Road data;
The MMIS_D3 of MMIS interface (MMIS_CS) pin is used to transmit chip selection signal.
The MMIS_D4 of MMIS interface (MMIS_IRQ) pin is used to transmit interrupt signal;
The MMIS_D5 pin of MMIS interface, the MMIS_D6 pin of MMIS interface, and the MMIS_D7 pin free time of MMIS interface.
In mode of operation is that ginseng is shown in Table 4 under the four line SDIO, and corresponding interface signal is defined as follows:
The MMIS_CLK pin of MMIS interface is used for transmit clock signal;
The MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin is used for the transmission command signal;
The MMIS_SYNC pin of MMIS interface is used to transmit multiplexed frame frame head index signal;
The MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin is used to transmit first via data;
The MMIS_D1 of MMIS interface (MMIS_IRQ) pin is used to transmit second circuit-switched data;
The MMIS_D2 of MMIS interface (MMIS_RW) pin is used to transmit Third Road data or interrupt signal;
The MMIS_D3 of MMIS interface (MMIS_CS) pin is used to transmit the 4th circuit-switched data.
The MMIS_D4 of MMIS interface (MMIS_IRQ) pin is used to transmit interrupt signal;
The MMIS_D5 pin of MMIS interface, the MMIS_D6 pin of MMIS interface, and the MMIS_D7 pin free time of MMIS interface.
Table 4
By table 4 as seen, under four line SPI and four line SDIO mode of operations, remove MMIS_D5 pin, MMIS_D6 pin, and outside the MMIS_D7 pin free time, all the other each pins are re-used all.
Table 4 and table 3 or table 2 contrast also can be drawn other multiplexing relations, no longer repeat explanation.
Include interrupt signal in four line SDIO mode of operations and the four line SPI mode of operations, effect is with single line and bifilar mode.
● further, if mode of operation is DVB-TS, the annexation between main equipment HOST and the slave unit SLAVE then, referring to shown in Figure 9, the pin that links to each other comprises: the MMIS_CLK pin of MMIS interface, the MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin, the MMIS_SYNC pin of MMIS interface, and 8 circuit-switched data transmission pin.
Ginseng is shown in Table 5, and the interface signal of DVB-TS mode of operation correspondence is defined as follows:
The MMIS_CLK pin of MMIS interface is used for transmit clock signal;
The MMIS_VLD of MMIS interface (MMIS_CMD/MMIS_RXD) pin is used to transmit the effective enable signal of data;
The MMIS_SYNC pin of MMIS interface is used for the transmitting synchronous marking signal;
The MMIS_D0 of MMIS interface (MMIS_TRXD/MMIS_TXD) pin is used to transmit first via data;
The MMIS_D1 of MMIS interface (MMIS_IRQ) pin is used to transmit second circuit-switched data;
The MMIS_D2 of MMIS interface (MMIS_RW) pin is used to transmit the Third Road data;
The MMIS_D3 of MMIS interface (MMIS_CS) pin is used to transmit the 4th circuit-switched data;
The MMIS_D4 pin of MMIS interface is used to transmit the 5th circuit-switched data;
The MMIS_D5 pin of MMIS interface is used to transmit the 6th circuit-switched data;
The MMIS_D6 pin of MMIS interface is used to transmit the 7th circuit-switched data;
The MMIS_D7 pin of MMIS interface is used to transmit the 8th circuit-switched data.
Table 5
Table 5 and table 4, table 3 or table 2 contrast also can be drawn other multiplexing relations, no longer repeat explanation.
Below by a specific embodiment the present invention is described.
Embodiment: the user inserts receiving equipment of the present invention with 4 line SDIO mobile multimedia cards, and (for example: the SDIO socket that mobile phone) provides is connected with MMIS interface in this mobile phone.The user selects " connecting the SDIO interface equipment " in the menu of this mobile phone operating system.Receiver module in this mobile phone can be received the indication of the connection SDIO interface equipment that the user sends by mobile phone operating system.Afterwards, the interface type (SDIO) and the mode of operation (4 line SDIO) of the corresponding option interface equipment of the meeting of the selected cell in this mobile phone.At last, the control module control MMIS interface in this mobile phone sticks into row alternately with the interface signal of 4 line SDIO mode of operation correspondences with 4 line SDIO mobile multimedias.
In sum, specific to the mobile multimedia technology, the MMIS interface rate can be from 167K bit/s to 108M bit/s.Satisfied the pin and the bandwidth demand of multimedia application, and can directly link to each other, improved the compatibility of chip and different multimedia application processor with present common SPI/SDIO interface equipment.
At SPI bifilar mode data throughout problem of smaller, a kind of four line SPI mode of operations have been proposed.And the interruption controls signal of adding slave output/main frame input.
The present invention can support single line SPI, two-wire SPI, four line SPI; Compatible to SD IO single-bit transmission mode (being single line SDIO), compatible to SD IO 4 bit transfer patterns (i.e. four line SDIO), compatible with DVB-TS interface; Receiving equipment can be from I
2C or UART port receive configuration information.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. a receiving equipment is characterized in that, comprising:
Mobile multimedia interface system MMIS interface, be used for multiplexing at least two types interface, multiplexing interface comprises at least with two kinds in the lower interface: serial peripheral equipment interface SPI, secure digital input/output interface SDIO, and digital video broadcasting transport stream interface DVB-TS;
Receiver module is used to receive the index signal that the user sends;
Select module, be used for the index signal received according to receiver module, select the interface type and the mode of operation of the interface equipment of awaiting orders, wherein:
When multiplexing mode of operation was single line SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation was two-wire SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation is four line SPI and four line SDIO, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation was two-wire SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation is four line SPI and DVB-TS, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin,
Or
When multiplexing mode of operation was four line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin;
When mode of operation was single line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was two-wire SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the data input; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for data output; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was four line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the 4th circuit-switched data; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit chip selection signal; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was single line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D2 pin is used for transmission and reads waiting signal;
When mode of operation was four line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit Third Road data or interrupt signal; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was DVB-TS, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the effective enable signal of data; The MMIS_SYNC pin is used for the transmitting synchronous marking signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit the 5th circuit-switched data; The MMIS_D5 pin is used to transmit the 6th circuit-switched data; The MMIS_D6 pin is used to transmit the 7th circuit-switched data; The MMIS_D7 pin is used to transmit the 8th circuit-switched data;
Control module is used to control the MMIS interface to select the interface signal of module selected interface type and mode of operation correspondence, carries out alternately with described interface equipment.
2. receiving equipment as claimed in claim 1, it is characterized in that, described single line SPI mode of operation, single line SDIO mode of operation, two-wire SPI mode of operation, four line SDIO mode of operations, and in the interface signal of four line SPI mode of operation correspondences, comprise interrupt signal.
3. a mobile multimedia interface system MMIS interface is characterized in that, comprising:
11 pins are used for multiplexing serial peripheral equipment interface SPI, secure digital input/output interface SDIO, and at least two kinds of interfaces among the digital video broadcasting transport stream interface DVB-TS; Described 11 pins are at SPI, SDIO, and under the different working modes of DVB-TS interface, the interface signal of transmission work at present pattern correspondence;
Wherein: when multiplexing mode of operation was single line SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation was two-wire SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation is four line SPI and four line SDIO, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation was two-wire SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation is four line SPI and DVB-TS, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin,
Or
When multiplexing mode of operation was four line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin;
When mode of operation was single line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was two-wire SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the data input; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for data output; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was four line SPI, corresponding interface signal was defined as follows:
The MMISC_LK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the 4th circuit-switched data; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit chip selection signal; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was single line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D2 pin is used for transmission and reads waiting signal;
When mode of operation was four line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit Third Road data or interrupt signal; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was DVB-TS, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the effective enable signal of data; The MMIS_SYNC pin is used for the transmitting synchronous marking signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit the 5th circuit-switched data; The MMIS_D5 pin is used to transmit the 6th circuit-switched data; The MMIS_D6 pin is used to transmit the 7th circuit-switched data; The MMIS_D7 pin is used to transmit the 8th circuit-switched data.
4. interface as claimed in claim 3 is characterized in that, described single line SPI mode of operation, single line SDIO mode of operation, two-wire SPI mode of operation, four line SDIO mode of operations, and in the interface signal of four line SPI mode of operation correspondences, comprise interrupt signal.
5. a data interactive method is characterized in that, comprises the following steps:
After receiving equipment is received the index signal that the user sends, select the interface type and the mode of operation of the interface equipment of awaiting orders according to this index signal, and, carry out alternately with described interface equipment with the interface signal of selected interface type and mode of operation correspondence;
Alternative interface type comprises at least: serial peripheral equipment interface SPI, secure digital input/output interface SDIO, and digital video broadcasting transport stream interface DVB-TS;
When selecting two kinds of interfaces from alternative interface type, the mode of operation of interface is multiplexed with:
When multiplexing mode of operation was single line SPI and single line SDIO, multiplexing mobile multimedia interface system MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation was two-wire SPI and single line SDIO, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin,
Or
When multiplexing mode of operation is four line SPI and four line SDIO, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation was two-wire SPI and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D3 pin,
Or
When multiplexing mode of operation is four line SPI and DVB-TS, multiplexing MMIS interface pin is MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin
Or
When multiplexing mode of operation was single line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin,
Or
When multiplexing mode of operation was four line SDIO and DVB-TS, multiplexing MMIS interface pin was MMIS_CLK pin, MMIS_VLD pin, MMIS_SYNC pin, MMIS_D0 pin, MMIS_D1 pin, MMIS_D2 pin, MMIS_D3 pin, MMIS_D4 pin;
When mode of operation was single line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was two-wire SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the data input; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for data output; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D3 pin is used to transmit chip selection signal;
When mode of operation was four line SPI, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the 4th circuit-switched data; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit chip selection signal; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was single line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used for bi-directional transfer of data; The MMIS_D1 pin is used to transmit interrupt signal; The MMIS_D2 pin is used for transmission and reads waiting signal;
When mode of operation was four line SDIO, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used for the transmission command signal; The MMIS_SYNC pin is used to transmit multiplexed frame frame head index signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit Third Road data or interrupt signal; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit interrupt signal;
When mode of operation was DVB-TS, corresponding interface signal was defined as follows:
The MMIS_CLK pin is used for transmit clock signal; The MMIS_VLD pin is used to transmit the effective enable signal of data; The MMIS_SYNC pin is used for the transmitting synchronous marking signal; The MMIS_D0 pin is used to transmit first via data; The MMIS_D1 pin is used to transmit second circuit-switched data; The MMIS_D2 pin is used to transmit the Third Road data; The MMIS_D3 pin is used to transmit the 4th circuit-switched data; The MMIS_D4 pin is used to transmit the 5th circuit-switched data; The MMIS_D5 pin is used to transmit the 6th circuit-switched data; The MMIS_D6 pin is used to transmit the 7th circuit-switched data; The MMIS_D7 pin is used to transmit the 8th circuit-switched data.
6. method as claimed in claim 5 is characterized in that, described single line SPI mode of operation, single line SDIO mode of operation, two-wire SPI mode of operation, four line SDIO mode of operations, and in the interface signal of four line SPI mode of operation correspondences, comprise interrupt signal.
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| CN2007100646644A CN101272405B (en) | 2007-03-22 | 2007-03-22 | Receiving equipment, MMIS interface and data interaction method |
| US12/025,458 US20080235411A1 (en) | 2007-03-22 | 2008-02-04 | Peripheral Interface, Receiving Apparatus and Data Communication Method Using the Same |
| KR1020080026464A KR20080086405A (en) | 2007-03-22 | 2008-03-21 | Peripheral interface, receiving apparatus and data communication method using the same |
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| US8738827B2 (en) * | 2011-07-18 | 2014-05-27 | O2Micro International Ltd. | Circuits and methods for providing communication between a memory card and a host device |
| CN104618059A (en) * | 2015-01-14 | 2015-05-13 | 华为技术有限公司 | Method, device and system for transmitting transport stream data |
| DE102016122421A1 (en) * | 2016-11-22 | 2018-05-24 | Robert Bosch Gmbh | Method and device for the serial transmission of data between two communication partners without synchronization clock transmission |
| CN108417181B (en) * | 2018-01-19 | 2021-05-25 | 昆山国显光电有限公司 | Interface definition method and device of driving circuit |
| CN108462508A (en) * | 2018-02-09 | 2018-08-28 | 深圳市元征软件开发有限公司 | A kind of data transmission method and equipment |
| CN113177009B (en) * | 2021-05-24 | 2022-10-21 | 上海航天计算机技术研究所 | Multi-interface multiplexing method and system for deep space probe |
| CN113534995B (en) * | 2021-06-24 | 2023-02-28 | 合肥松豪电子科技有限公司 | TDDI chip shared by SPI interfaces |
| CN115941382A (en) * | 2022-11-10 | 2023-04-07 | 星河智联汽车科技有限公司 | Flow control method and device for SPI communication, terminal equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2786711Y (en) * | 2005-03-04 | 2006-06-07 | 吕小辉 | SD card supporting two number input and output interface |
| CN1794272A (en) * | 2005-12-30 | 2006-06-28 | 无锡商炜科技有限公司 | Format converting method capable of compatible multikind numberical multimedia storage card and its storage card |
| CN1851682A (en) * | 2006-03-28 | 2006-10-25 | 华为技术有限公司 | Method for realizing serial peripheral unit interface |
| WO2006123707A1 (en) * | 2005-05-18 | 2006-11-23 | Sony Corporation | Memory card and card adapter |
-
2007
- 2007-03-22 CN CN2007100646644A patent/CN101272405B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2786711Y (en) * | 2005-03-04 | 2006-06-07 | 吕小辉 | SD card supporting two number input and output interface |
| WO2006123707A1 (en) * | 2005-05-18 | 2006-11-23 | Sony Corporation | Memory card and card adapter |
| CN1794272A (en) * | 2005-12-30 | 2006-06-28 | 无锡商炜科技有限公司 | Format converting method capable of compatible multikind numberical multimedia storage card and its storage card |
| CN1851682A (en) * | 2006-03-28 | 2006-10-25 | 华为技术有限公司 | Method for realizing serial peripheral unit interface |
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| CN101272405A (en) | 2008-09-24 |
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