CN115941382A - Flow control method and device for SPI communication, terminal equipment and storage medium - Google Patents
Flow control method and device for SPI communication, terminal equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a flow control method, a device, terminal equipment and a storage medium for SPI communication, wherein the method is applied to a flow control system comprising a master device and a slave device for SPI communication, and a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface; the method comprises the following steps: data transmission is carried out between the master equipment and the slave equipment through a communication channel; when the slave device sends data to the master device, the second GPIO pin is set to be in a first state, and an interrupt signal is sent to the master device; the master device initiates transmission after receiving the interrupt signal and receives the data sent from the slave device; and when the slave device detects that the first GPIO pin changes from a high level to a low level, judging that the data frame transmission is finished. The invention uses less GPIO pins, saves chip hardware resources, and the master device and the slave device can send data at any time, thereby realizing a data response and retransmission mechanism, ensuring the real-time and reliability of the data and reducing the extra expense of a CPU.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a flow control method and apparatus for SPI communications, a terminal device, and a storage medium.
Background
According to the SPI communication principle, in each Clock cycle, an SPI device sends and receives data (whether master or slave) of one bit size, which is equivalent to the device having one bit size exchanged. Since the clock is provided by the master device, the slave device cannot actively transmit data. If the slave device wants to send data at any time, the master device must use a polling method to continuously initiate transmission, and invalid data exists on the bus most of the time, which causes additional CPU overhead for the master device. When the master device and the slave device do not have a fixed frame length, the slave device does not know whether the data reception is completed. In addition, the SPI has no specified flow control, no response mechanism is used to confirm whether data is received, or more GPIO pins are used to implement flow control and response, which is higher in cost.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a flow control method, apparatus, terminal device and storage medium for SPI communication, which uses fewer GPIO pins, saves chip hardware resources, and enables the master device and the slave device to send data at any time, thereby implementing a data response and retransmission mechanism, ensuring real-time and reliability of data, and reducing additional overhead of a CPU.
In order to achieve the above object, an embodiment of the present invention provides a flow control method for SPI communication, which is applied to a flow control system for SPI communication, where the flow control system includes a master device and at least one slave device, and a communication channel between the master device and the slave device includes an SPI interface and two GPIO pins associated with the SPI interface; the first GPIO pin is an input of the slave device and is connected with a CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected with the master device, and the flow control method of the SPI communication comprises the following steps:
the master device and the slave device carry out data transmission through the communication channel;
when the slave device sends data to the master device, the second GPIO pin is set to be in a first state, and an interrupt signal is sent to the master device;
the master device initiates transmission after receiving the interrupt signal and receives data sent from the slave device;
and when the slave device detects that the first GPIO pin changes from a high level to a low level, determining that data frame transmission is finished.
As an improvement of the above solution, when the slave device transmits data to the master device, the interface transmission length of the slave device is set to be a maximum frame length, and the interface transmission length of the master device is set to be a minimum frame length.
As an improvement of the above scheme, when the slave device detects that the first GPIO pin changes from high level to low level, it determines that data frame transmission is complete, and then further includes:
judging whether the data frame returned from the main equipment is valid;
if the data frame is valid, judging the type of the data frame returned from the main equipment; if the request frame is the request frame, the data frame returned by the master device is placed in a receiving buffer area of the slave device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the slave device; if the frame is a response frame, setting a response zone bit, and transmitting the next frame of data;
if the data frame is invalid, directly entering response waiting, and removing the sent data frame from the sending buffer area of the slave equipment to transmit the next frame data after receiving the response.
As an improvement of the above scheme, when the master device initiates transmission, circularly detecting a sending buffer of the master device;
when the sending buffer area of the master device has the data frame to be sent, the data frame to be sent is taken out in a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.
As an improvement of the above scheme, the invoking the SPI interface to send the data frame to be sent to the slave device further includes:
the master device receives the data frame returned from the slave device and judges whether the returned data frame is valid;
if the data frame is valid, processing the valid data frame, and entering response waiting after the processing is finished;
if the response is invalid, directly entering response waiting;
and if the response is overtime, retransmission is initiated, and if the response is received, the data frame to be sent is removed from the sending buffer area of the main equipment, and the transmission of the next frame data is carried out.
As an improvement of the above scheme, the processing the valid data frame specifically includes:
judging whether the length of the effective data frame is not more than the length of the preset frame;
if not, initiating secondary transmission and receiving the residual data which is not received;
if yes, judging the type of the effective data frame;
if the effective data frame is a request frame, the effective data frame is placed in a receiving buffer area of the main equipment, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the main equipment;
and if the effective data frame is a response frame, setting a response zone bit and transmitting the next frame of data.
As an improvement of the above scheme, the length of the valid data frame is the sum of the frame header length, the data length and the check region length.
The embodiment of the invention also provides a flow control device for SPI communication, which is applied to a flow control system for SPI communication, wherein the flow control system comprises a master device and at least one slave device, and a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface; the first GPIO pin is an input of the slave device and is connected with a CS pin in the SPI interface; the second GPIO pin is an output of the slave device and is connected to the master device, and the SPI communication flow control device includes:
the transmission module is used for carrying out data transmission between the master equipment and the slave equipment through the communication channel;
the interrupt module is used for setting the second GPIO pin to be in a first state and sending an interrupt signal to the master device when the slave device sends data to the master device;
a receiving module, configured to initiate transmission after the master device receives the interrupt signal, and receive data sent from the slave device;
and the detection module is used for judging that the data frame transmission is finished when the slave device detects that the first GPIO pin is changed from a high level to a low level.
An embodiment of the present invention further provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, where the processor implements the flow control method for SPI communication described in any one of the above when executing the computer program.
An embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program, and when the computer program runs, a device where the computer-readable storage medium is located is controlled to execute any one of the above-mentioned SPI communication flow control methods.
Compared with the prior art, the flow control method, the flow control device, the terminal device and the storage medium for the SPI communication provided by the embodiment of the invention have the beneficial effects that: adding two GPIO pins associated with an SPI (serial peripheral interface) through a communication channel between a master device and a slave device, wherein the first GPIO pin is the input of the slave device and is connected with a CS (circuit switching) pin in the SPI; and the second GPIO pin is the output of the slave device and is connected with the master device. Data transmission is carried out between the master equipment and the slave equipment through the communication channel; when the slave device sends data to the master device, the second GPIO pin is set to be in a first state, and an interrupt signal is sent to the master device; the master device initiates transmission after receiving the interrupt signal and receives data sent from the slave device; and when the slave device detects that the first GPIO pin changes from a high level to a low level, determining that data frame transmission is finished. The embodiment of the invention uses fewer GPIO pins, saves chip hardware resources, and the master device and the slave device can send data at any time, thereby realizing a data response and retransmission mechanism, ensuring the real-time performance and reliability of the data and reducing the extra expense of a CPU.
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Fig. 1 is a schematic flow chart of a preferred embodiment of a flow control method for SPI communication provided in the present invention;
FIG. 2 is a schematic structural diagram of a preferred embodiment of a flow control system for SPI communication according to the present invention;
fig. 3 is a schematic flow chart of a slave device initiating transmission in a flow control method of SPI communication provided in the present invention;
fig. 4 is a schematic flowchart of a master device receiving a slave device transmission request in the SPI communication flow control method provided in the present invention;
fig. 5 is a schematic flowchart of a master device initiating transmission in a flow control method for SPI communication provided in the present invention;
fig. 6 is a schematic flowchart illustrating a process of processing an effective data frame by a master device in a flow control method for SPI communication according to the present invention;
fig. 7 is a schematic structural diagram of an effective data frame in a flow control method for SPI communication provided in the present invention;
FIG. 8 is a schematic structural diagram of a preferred embodiment of a fluidic device for SPI communication provided by the present invention;
fig. 9 is a schematic structural diagram of a preferred embodiment of a terminal device provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
Referring to fig. 1, fig. 1 is a schematic flowchart of a flow control method for SPI communication according to a preferred embodiment of the present invention. The flow control method of the SPI communication is applied to a flow control system of the SPI communication, the flow control system comprises a master device and at least one slave device, and a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface; the first GPIO pin is an input of the slave device and is connected with a CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected with the master device, and the flow control method of the SPI communication comprises the following steps:
s1, data transmission is carried out between the master equipment and the slave equipment through the communication channel;
s2, when the slave device sends data to the master device, the second GPIO pin is set to be in a first state, and an interrupt signal is sent to the master device;
s3, the master device initiates transmission after receiving the interrupt signal and receives data sent by the slave device;
and S4, when the slave device detects that the first GPIO pin is changed from high level to low level, the slave device judges that data frame transmission is completed.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of a flow control system for SPI communication according to a preferred embodiment of the present invention. The flow control system for SPI communication in the embodiment of the invention comprises a master device and at least one slave device, wherein a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface. And the first GPIO pin is input of the slave device and is connected with a CS pin in the SPI interface. And the second GPIO pin is the output of the slave device and is connected with the master device. The SPI interface includes MOSI, MISO, SCLK and CS signal lines. The SCLK, MOSI and CS signals are all controlled and generated by the master device, and the SCLK is a clock signal used for synchronizing data. MOSI is the master device outputting the slave device input signal, the master device transmitting data to the slave device through this signal line. CS is a chip select signal for selecting the slave device, active low. And the MISO signal is generated by the slave device, and the master device reads the data of the slave device through the signal line. The signals MOSI and MISO are only active when CS is low, transmitting one bit of data per clock cycle of SCLK. In the embodiment of the invention, data transmission is carried out between the master equipment and the slave equipment through the communication channel. When the slave device actively sends data to the master device, the second GPIO pin is set to be in the first state, and an interrupt signal is sent to the master device. The first state refers to that the GPIO2 is set from high (default state is high) to low and then to high, because the master device uses a falling edge to trigger an interrupt. And the master equipment initiates transmission after receiving the interrupt signal and receives the data sent by the slave equipment. If the master device does not initiate a transmission, the slave device will always block. When the slave device detects that the first GPIO pin changes from high level to low level, the data frame transmission is judged to be completed.
It should be noted that, in SPI communication, an SPI master device is given to an SPI slave device through an SCLK line at a frequency supported by the SPI slave device, which means that the SPI slave device cannot actively send data to the SPI master device, and only the SPI master device can poll the SPI slave device or the SPI slave device actively informs the SPI slave device of data arrival through an IO port. Therefore, the embodiment of the invention adds two GPIO pins associated with the SPI interface to the communication channel between the master device and the slave device.
The embodiment of the invention realizes the flow control of the SPI communication by using fewer GPIO pins, uses one GPIO pin for the main device and two GPIO pins for the auxiliary device, has simple hardware structure and saves chip hardware resources. The slave device uses the maximum frame length for transmission, and the master device judges whether to perform secondary transmission by detecting the data length in the frame header. Therefore, the master device and the slave device do not need to use a fixed frame length to transmit and receive data, the transmission frame length is determined by the data length actually required to be transmitted each time, and the additional clock overhead is avoided. The slave device uses GPIO interruption to inform the master device to start transmission, the slave device can actively send data at any time, the master device does not need to circularly receive the data, and the CPU resource occupation is reduced. The master device and the slave device can receive and transmit data at any time and process the received data when transmitting the data, thereby realizing full-duplex transmission of effective data and greatly improving the communication rate of the SPI. The master device and the slave device both carry out a software response retransmission mechanism, and the correctness of data receiving and transmitting each time is ensured.
In another preferred embodiment, when the slave device sends data to the master device, the interface transmission length of the slave device is set to be a maximum frame length, and the interface transmission length of the master device is set to be a minimum frame length.
Specifically, since the master may initiate multiple calls, and the slave does not know how long each time the slave transmits, the interface transmission length of the slave needs to be set to the maximum frame length, and the interface transmission length of the master needs to be set to the minimum frame length.
In another preferred embodiment, the determining that the data frame transmission is completed when the slave device detects that the first GPIO pin changes from high level to low level further includes:
judging whether a data frame returned from the main equipment is valid;
if the data frame is valid, judging the type of the data frame returned from the main equipment; if the request frame is the request frame, the data frame returned by the master device is placed in a receiving buffer area of the slave device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the slave device; if the frame is a response frame, setting a response zone bit, and transmitting the next frame of data;
if the data frame is invalid, the slave equipment directly enters a response waiting mode, and if the data frame is received, the sent data frame is removed from a sending buffer area of the slave equipment, and the next frame data is transmitted.
Specifically, please refer to fig. 3 and fig. 4, where fig. 3 is a schematic flow diagram of a transmission initiated by a slave device in a flow control method for SPI communication provided by the present invention, and fig. 4 is a schematic flow diagram of a transmission request received by a master device in the flow control method for SPI communication provided by the present invention. When the slave device actively sends data to the master device, the data frame to be sent is taken out from the sending buffer area of the slave device, the second GPIO pin is set to be in the first state, an interrupt signal is sent to the master device, and the master device is informed to initiate transmission. And the master equipment initiates transmission after receiving the interrupt signal and receives the data sent by the slave equipment. And when the slave device detects that the first GPIO pin is changed from high level to low level in the receiving state, the slave device judges that the data frame transmission is finished, exits the receiving state and processes the received data. And judging whether the data frame returned from the master equipment is valid. If the data frame is valid, the type of the data frame returned from the master device is judged. And if the request frame is the request frame, the data frame returned by the master device is placed in a receiving buffer area of the slave device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the slave device. And if the frame is a response frame, setting a response flag bit and transmitting the next frame of data. If the data frame is invalid, the slave device directly enters a response waiting mode, and if the data frame is received, the sent data frame is removed from a sending buffer area of the slave device, and the next frame data is transmitted.
It should be noted that, unlike the processing of the received valid data frame by the master device, the slave device does not need to perform secondary transmission, and can determine whether the transmission of the entire data frame is completed through the state of the GPIO 1.
The embodiment of the invention uses fewer GPIO pins, saves chip hardware resources, and the master device and the slave device can send data at any time, thereby realizing a data response and retransmission mechanism, ensuring the real-time performance and reliability of the data and reducing the additional expense of a CPU.
In another preferred embodiment, when the master device initiates transmission, the transmission buffer of the master device is circularly detected;
when the sending buffer area of the master device has the data frame to be sent, the data frame to be sent is taken out in a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.
Specifically, please refer to fig. 5, wherein fig. 5 is a schematic flowchart of a master device initiating transmission in the SPI communication flow control method provided in the present invention. And when the main equipment initiates transmission, the sending task continuously and circularly detects a sending buffer area of the main equipment. When a data frame to be sent exists in a sending buffer area of the master device, taking out the data frame to be sent according to a preset frame length sLen, and calling an SPI (serial peripheral interface) to send the data frame to be sent to the slave device.
In another preferred embodiment, the invoking the SPI interface to send the data frame to be sent to the slave device further includes:
the master device receives the data frame returned from the slave device and judges whether the returned data frame is valid;
if the data frame is valid, processing the valid data frame, and entering response waiting after the processing is finished;
if the response is invalid, directly entering response waiting;
and if the response is overtime, initiating retransmission, and if the response is received, removing the data frame to be transmitted from the transmission buffer area of the main equipment to transmit the next frame data.
Specifically, please refer to fig. 6, where fig. 6 is a schematic flow diagram illustrating a process of processing an effective data frame by a master device in a flow control method for SPI communication according to the present invention. When the sending buffer area of the master device has the data frame to be sent, the data frame to be sent is taken out in a preset frame length, the SPI is called to send the data frame to be sent to the slave device, the master device receives the data frame returned from the slave device, and whether the returned data frame is valid or not is judged. And if the data frame returned by the slave equipment is valid, processing the valid data frame, and entering response waiting after the processing is finished. And if the data frame returned by the slave equipment is invalid, directly entering response waiting. And if the response is overtime, retransmission is initiated, and if the response is received, the data frame to be transmitted is removed from the transmission buffer area of the main equipment, and the next frame data is transmitted.
In another preferred embodiment, the processing the valid data frame specifically includes:
judging whether the length of the effective data frame is not greater than the length of the preset frame;
if not, initiating secondary transmission and receiving the residual data which is not received;
if yes, judging the type of the effective data frame;
if the effective data frame is a request frame, the effective data frame is placed in a receiving buffer area of the main equipment, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the main equipment;
and if the effective data frame is a response frame, setting a response zone bit and transmitting the next frame of data.
Specifically, when the main device processes the valid data frame, the length rLen of the frame data is obtained from the frame header of the received data, and it is determined whether the length rLen of the valid data frame is not greater than the preset frame length sLen. If the length rLen of the valid data frame is greater than the preset frame length sLen, it indicates that the data frame sent by the slave device has remaining data which is not received, and the SPI interface needs to be called again to initiate secondary transmission to complete reception of the remaining data. If the length rLen of the valid data frame is not greater than the preset frame length sLen, it indicates that the data frame sent by the slave device is completely received in the current call, and further determines the type of the valid data frame through the frame header information. And if the effective data frame is the request frame, the effective data frame is placed in a receiving buffer area of the main equipment, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the main equipment. If the valid data frame is a response frame, it indicates that the last request frame of the master device received a response, and the next frame of data can be transmitted.
Preferably, the length of the valid data frame is the sum of the frame header length, the data length and the check region length.
Specifically, please refer to fig. 7, fig. 7 is a schematic structural diagram of an effective data frame in a flow control method for SPI communication according to the present invention. The effective data frame in the embodiment of the invention comprises a frame header, data and a check area. Wherein the frame header includes an identifier, a sequence number, and a total length. The identifier identifies the data class of the frame, and may be a request frame sent by the master device to the slave device, a request frame sent by the slave device to the master device, a response frame sent by the master device to the slave device, and a response frame sent by the slave device to the master device. The serial number is unique every time the request frame is sent, and the corresponding response frame is consistent with the serial number. Total length = frame header length + data length + check zone length.
Correspondingly, the invention also provides a flow control device for the SPI communication, which can realize all the processes of the flow control method for the SPI communication in the above embodiment.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a flow control apparatus for SPI communication according to a preferred embodiment of the present invention. The flow control device of the SPI communication is applied to a flow control system of the SPI communication, the flow control system comprises a master device and at least one slave device, and a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface; the first GPIO pin is an input of the slave device and is connected with a CS pin in the SPI interface; the second GPIO pin is an output of the slave device and is connected to the master device, and the SPI communication flow control device includes:
a transmission module 801, configured to perform data transmission between the master device and the slave device through the communication channel;
an interrupt module 802, configured to set the second GPIO pin to a first state when the slave device sends data to the master device, and send an interrupt signal to the master device;
a receiving module 803, configured to initiate transmission after the master device receives the interrupt signal, and receive data sent from the slave device;
a detecting module 804, configured to determine that data frame transmission is completed when the slave device detects that the first GPIO pin changes from high level to low level.
Preferably, when the slave device sends data to the master device, the interface transmission length of the slave device is set to be a maximum frame length, and the interface transmission length of the master device is set to be a minimum frame length.
Preferably, when the slave device detects that the first GPIO pin changes from high level to low level, determining that data frame transmission is complete further includes:
judging whether a data frame returned from the main equipment is valid;
if the data frame is valid, judging the type of the data frame returned from the main equipment; if the request frame is the request frame, the data frame returned by the master device is placed in a receiving buffer area of the slave device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the slave device; if the frame is a response frame, setting a response zone bit, and transmitting the next frame of data;
if the data frame is invalid, the slave equipment directly enters a response waiting mode, and if the data frame is received, the sent data frame is removed from a sending buffer area of the slave equipment, and the next frame data is transmitted.
Preferably, when the master device initiates transmission, the sending buffer of the master device is circularly detected;
when the sending buffer area of the master device has the data frame to be sent, the data frame to be sent is taken out in a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.
Preferably, the invoking the SPI interface to send the data frame to be sent to the slave device further includes:
the master device receives the data frame returned from the slave device and judges whether the returned data frame is valid;
if the data frame is valid, processing the valid data frame, and entering response waiting after the processing is finished;
if the response is invalid, directly entering response waiting;
and if the response is overtime, retransmission is initiated, and if the response is received, the data frame to be sent is removed from the sending buffer area of the main equipment, and the transmission of the next frame data is carried out.
Preferably, the processing the valid data frame specifically includes:
judging whether the length of the effective data frame is not greater than the length of the preset frame;
if not, initiating secondary transmission and receiving the residual data which is not received;
if yes, judging the type of the effective data frame;
if the effective data frame is a request frame, the effective data frame is placed in a receiving buffer area of the main equipment, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the main equipment;
and if the effective data frame is a response frame, setting a response zone bit and transmitting the next frame of data.
Preferably, the length of the valid data frame is the sum of the frame header length, the data length and the check area length.
In specific implementation, the working principle, the control flow and the implementation technical effect of the SPI communication flow control device provided in the embodiment of the present invention are the same as those of the SPI communication flow control method in the above embodiment, and are not described herein again.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a terminal device according to a preferred embodiment of the present invention. The terminal device includes a processor 901, a memory 902, and a computer program stored in the memory 902 and configured to be executed by the processor 901, and when the processor 901 executes the computer program, the flow control method for SPI communication described in any of the above embodiments is implemented.
Preferably, the computer program may be divided into one or more modules/units (e.g., computer program 1, computer program 2, 8230; etc.) which are stored in the memory 902 and executed by the processor 901 to accomplish the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing certain functions, which are used to describe the execution of the computer program in the terminal device.
The Processor 901 may be a Central Processing Unit (CPU), other general purpose processors, digital Signal Processors (DSP), application Specific Integrated Circuits (ASIC), field Programmable Gate Array (FPGA) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, etc., the general purpose Processor 901 may be a microprocessor, or the Processor 901 may be any conventional Processor, the Processor 901 is a control center of the terminal device, and various interfaces and lines are used to connect various parts of the terminal device.
The memory 902 mainly includes a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function, and the like, and the data storage area may store related data and the like. In addition, the memory 902 may be a high speed random access memory, a non-volatile memory such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash Card (Flash Card), and the like, or the memory 902 may be other volatile solid state memory devices.
It should be noted that the terminal device may include, but is not limited to, a processor and a memory, and those skilled in the art will understand that the structural diagram of fig. 9 is only an example of the terminal device and does not constitute a limitation of the terminal device, and may include more or less components than those shown, or combine some components, or different components.
The embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program, and when the computer program runs, a device where the computer-readable storage medium is located is controlled to execute the flow control method for SPI communication according to any one of the above-mentioned embodiments.
The embodiment of the invention provides a flow control method and device for SPI communication, terminal equipment and a storage medium, wherein two GPIO pins associated with an SPI interface are added in a communication channel between master equipment and slave equipment, wherein the first GPIO pin is used as the input of the slave equipment and is connected with a CS pin in the SPI interface; and the second GPIO pin is the output of the slave device and is connected with the master device. Data transmission is carried out between the master equipment and the slave equipment through the communication channel; when the slave device sends data to the master device, the second GPIO pin is set to be in a first state, and an interrupt signal is sent to the master device; the master device initiates transmission after receiving the interrupt signal and receives data sent from the slave device; and when the slave device detects that the first GPIO pin changes from a high level to a low level, determining that data frame transmission is finished. The embodiment of the invention uses fewer GPIO pins, saves chip hardware resources, and the master device and the slave device can send data at any time, thereby realizing a data response and retransmission mechanism, ensuring the real-time performance and reliability of the data and reducing the additional expense of a CPU.
It should be noted that the above-described system embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the system embodiment provided by the present invention, the connection relationship between the modules indicates that there is a communication connection therebetween, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (10)
1. The flow control method of the SPI communication is characterized in that the flow control system is applied to the SPI communication and comprises a master device and at least one slave device, wherein a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface; the first GPIO pin is an input of the slave device and is connected with a CS pin in the SPI interface; the second GPIO pin is the output of the slave device and is connected with the master device, and the flow control method of the SPI communication comprises the following steps:
the master device and the slave device carry out data transmission through the communication channel;
when the slave device sends data to the master device, the second GPIO pin is set to be in a first state, and an interrupt signal is sent to the master device;
the master device initiates transmission after receiving the interrupt signal and receives data sent from the slave device;
and when the slave device detects that the first GPIO pin changes from a high level to a low level, determining that data frame transmission is finished.
2. The flow control method for SPI communication according to claim 1, wherein when said slave device sends data to said master device, an interface transmission length of said slave device is set to a maximum frame length, and an interface transmission length of said master device is set to a minimum frame length.
3. The method for flow control of SPI communication of claim 2, wherein said determining that data frame transmission is complete when said slave device detects that said first GPIO pin changes from high to low further comprises:
judging whether the data frame returned from the main equipment is valid;
if the data frame is valid, judging the type of the data frame returned from the main equipment; if the request frame is the request frame, the data frame returned by the master device is placed in a receiving buffer area of the slave device, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the slave device; if the frame is a response frame, setting a response zone bit, and transmitting the next frame of data;
if the data frame is invalid, directly entering response waiting, and removing the sent data frame from the sending buffer area of the slave equipment to transmit the next frame data after receiving the response.
4. The flow control method for SPI communication according to claim 3, wherein when said master device initiates a transmission, a transmission buffer of said master device is cyclically detected;
when the sending buffer area of the master device has the data frame to be sent, the data frame to be sent is taken out in a preset frame length, and the SPI interface is called to send the data frame to be sent to the slave device.
5. The flow control method for SPI communication of claim 4, wherein said invoking said SPI interface to send said data frame to be sent to said slave device, thereafter further comprises:
the master device receives the data frame returned from the slave device and judges whether the returned data frame is valid;
if the data frame is valid, processing the valid data frame, and entering response waiting after the processing is finished;
if the response is invalid, directly entering response waiting;
and if the response is overtime, initiating retransmission, and if the response is received, removing the data frame to be transmitted from the transmission buffer area of the main equipment to transmit the next frame data.
6. The SPI communication flow control method according to claim 5, wherein the processing of the valid data frames specifically comprises:
judging whether the length of the effective data frame is not more than the length of the preset frame;
if not, initiating secondary transmission and receiving the residual data which is not received;
if yes, judging the type of the effective data frame;
if the effective data frame is a request frame, the effective data frame is placed in a receiving buffer area of the main equipment, a response frame of the request frame is generated, and the response frame is placed in a sending buffer area of the main equipment;
and if the effective data frame is a response frame, setting a response zone bit and transmitting the next frame of data.
7. The method for flow control of SPI communication according to claim 6, wherein the length of said valid data frame is the sum of the length of the frame header, the length of the data and the length of the check region.
8. A flow control device for SPI communication is characterized in that the flow control device is applied to a flow control system for SPI communication, the flow control system comprises a master device and at least one slave device, and a communication channel between the master device and the slave device comprises an SPI interface and two GPIO pins associated with the SPI interface; the first GPIO pin is input of the slave device and is connected with a CS pin in the SPI interface; the second GPIO pin is an output of the slave device and is connected to the master device, and the SPI communication flow control device includes:
the transmission module is used for carrying out data transmission between the master equipment and the slave equipment through the communication channel;
the interrupt module is used for setting the second GPIO pin to be in a first state and sending an interrupt signal to the master device when the slave device sends data to the master device;
a receiving module, configured to initiate transmission after the master device receives the interrupt signal, and receive data sent from the slave device;
and the detection module is used for judging that the data frame transmission is finished when the slave device detects that the first GPIO pin is changed from a high level to a low level.
9. A terminal device comprising a processor and a memory, wherein the memory has a computer program stored therein and the computer program is configured to be executed by the processor, and the processor executes the computer program to implement the flow control method of SPI communication according to any one of claims 1 to 7.
10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by an apparatus, the apparatus implements the flow control method for SPI communication according to any one of claims 1 to 7.
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| CN118535357A (en) * | 2024-07-25 | 2024-08-23 | 北京鉴智科技有限公司 | Synchronous communication system, method, device, electronic equipment and storage medium |
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