CN112395230A - UART interface extension circuit based on programmable logic device - Google Patents
UART interface extension circuit based on programmable logic device Download PDFInfo
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- CN112395230A CN112395230A CN202011514179.4A CN202011514179A CN112395230A CN 112395230 A CN112395230 A CN 112395230A CN 202011514179 A CN202011514179 A CN 202011514179A CN 112395230 A CN112395230 A CN 112395230A
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention relates to the field of UART communication interface extension. A UART interface extension circuit based on a programmable logic device is provided with a plurality of UART interfaces connected with UART interface equipment, and comprises a main controller module and UART interface control units with the same number as the UART interfaces, wherein each UART interface control unit corresponds to one UART interface, each UART interface control unit comprises a UART controller module of the UART interface corresponding to the UART interface control unit, a baud rate generator module, a data sending module, a data receiving cache module and a data sending cache module, the main controller module defines a group of independent addresses for each UART interface, and the corresponding addresses of the UART interfaces corresponding to the UART controller module are stored in each UART controller module.
Description
Technical Field
The invention discloses a UART interface extension circuit based on a programmable logic device, and belongs to the field of UART communication interface extension.
Background
A UART (Universal Asynchronous Receiver/Transmitter) is a serial communication interface, which uses two data lines for transmitting and receiving data, has a simple hardware circuit, can implement full-duplex communication, and is widely used in digital communication, especially in the field of sensor data transmission. In order to implement communication with the UART interface device, the CPU processor is usually designed with one or more UART communication interfaces, most CPUs have 1-4 UART interfaces, each UART communication interface can be connected to the UART interface device to implement data transmission, because the CPU uses an instruction execution mode, the CPU processor can only perform data transmission with one external UART interface device at the same time, and the transmission rate is usually not greater than 115200 bps.
In order to implement communication between the processor and the plurality of UART interface devices, a plurality of CPU processors are usually used in the control system, each UART interface device is connected to the UART interface of one of the CPU processors, and the plurality of CPU processors in the system perform data transmission in a certain communication manner. Chinese patent CN103605306A has designed a UART communication interface extension device, a UART interface of the single chip is connected in parallel with N external UART interface devices, the enable end of the UART interface devices is controlled by the IO interface of the single chip, when the enable end of a certain UART interface device is valid, the single chip is connected with the device through the UART interface for data transmission, the design can realize the communication between a single chip processor and a plurality of UART interface devices, but each additional UART interface device will occupy more than one IO interface of the single chip, the UART interface devices cannot work simultaneously, and when the communication parameters of the UART interface devices are not consistent, the single chip needs to reconfigure the UART serial communication parameters in the execution process, thereby reducing the data transmission rate.
In order to realize the communication between a CPU processor and a plurality of UART interface devices with different communication parameters, the UART interface devices can work simultaneously and improve the data transmission rate, a UART interface extension circuit based on a programmable logic device is designed, the circuit comprises a plurality of UART communication interfaces, the number of the UART interfaces is determined by the IO number of the programmable logic device and the logic resources in a chip, the communication parameters can be flexibly configured, the CPU processor can communicate with the UART interface devices through the circuit, the UART interface devices can transmit data simultaneously, and the data transmission rate is greatly improved.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: how to realize the high-speed data transmission between the CPU processor and a plurality of external UART interface devices with different communication parameters.
The technical scheme adopted by the invention is as follows: a UART interface extension circuit based on a programmable logic device is provided with a plurality of UART interfaces connected with UART interface equipment, and comprises a main controller module and UART interface control units with the same number as the UART interfaces, wherein each UART interface control unit corresponds to one UART interface, each UART interface control unit comprises a UART controller module of the UART interface corresponding to the UART interface control unit, a baud rate generator module, a data sending module, a data receiving cache module and a data sending cache module, the main controller module defines a group of independent addresses for each UART interface, and the corresponding addresses of the UART interfaces corresponding to the UART controller module are stored in each UART controller module.
The programmable logic device is connected with the CPU processor through an 8-bit data bus, the CPU sends a data frame comprising destination address information to the main controller module, and the main controller module forwards received data to a corresponding UART interface control unit according to the destination address information in the data frame; the data frame comprises a frame type, a destination address, configuration parameters and check information, wherein the configuration parameters comprise a baud rate, data bits, parity check, a stop bit and priority.
The UART interface equipment connected with each UART interface sends data to the UART interface control unit corresponding to the corresponding interface of the UART interface equipment through the UART interface connected with the UART interface equipment, the UART interface control unit receives the data through the data receiving module and writes the data into the data receiving buffer module, the UART interface control unit sends a trigger signal to the main controller module through the data sending module, if the main controller module is in an idle state, the main controller module sends an interrupt request to the CPU processor, the CPU processor sends an interrupt response to the main controller module after receiving the interrupt request, the main controller module sends a read command to the UART interface control unit sending the trigger signal after receiving the interrupt response, the UART control module transmits the data received in the data receiving buffer module to the main controller module after receiving the read command, the main controller module packs the received data, and packs the UART interface address, the UART interface address, Transmitting the data and the check information to a CPU; if a plurality of UART interface control units simultaneously send trigger signals to the main controller module through the data sending module, the main controller module responds according to the priority order of the UART interfaces corresponding to the UART interface control units corresponding to the trigger signals, the data of the UART interface control units corresponding to the UART interfaces with high priority respond first, and the priority information of the UART interface control units is stored in the main controller module.
The invention has the beneficial effects that: the UART interface device can realize high-speed data transmission between the CPU and multiple paths of UART interface devices with different communication parameters, and the UART interface devices can work simultaneously.
Drawings
FIG. 1 is a diagram of the UART interface extension circuit application system architecture of the present invention;
FIG. 2 is an internal structure of the UART interface extension circuit of the present invention;
FIG. 3 shows a control frame format sent by the CPU;
FIG. 4 shows a data frame format sent by the CPU;
FIG. 5 shows a data frame format sent by the host controller module.
Detailed Description
The UART interface extension circuit is designed by utilizing a programmable logic device, and comprises a main controller module and UART interface control units, wherein each UART interface control unit is allocated with different addresses, and each UART interface control unit comprises a UART controller module, a baud rate generator module, a data transmitting module, a data receiving cache module and a data transmitting cache module, as shown in figure 2. The CPU processor is connected with the UART extension circuit through a parallel bus, a connection signal comprises an 8-bit data bus, a clock, a receiving response, an interrupt request, an interrupt response and the like, the CPU sends information which is divided into a control frame and a data frame, the control frame is used for configuring communication parameters of each UART interface in the UART extension circuit, the communication parameters comprise baud rate, data bits, parity check, stop bits, priority and the like, and the control frame comprises frame sections of frame type, destination address, configuration parameters, check and the like, as shown in figure 3. The CPU sends a data frame to the UART interface extension circuit to communicate with any UART interface device, where the data frame is composed of frame segments such as frame type, destination address, data, and checksum, as shown in fig. 4.
The main controller module receives data sent by the CPU, forwards the data to a corresponding UART controller according to destination address information, the UART controller executes corresponding operation according to frame type information after receiving the data, if the data is a control frame, the UART controller configures UART communication parameters according to information such as baud rate, data bit, parity check, stop bit, priority and the like, if the data is a data frame, the received data is written into a sending cache, and the data in the sending cache is output from a sending interface through the data sending module. After receiving the data transmitted by the UART interface device, the UART interface writes the data into the receiving buffer to trigger the main controller module, if the main controller module is in an idle state, the main controller module sends an interrupt request to the CPU, after receiving an interrupt response returned by the CPU, the main controller module sends a read command to the UART controller module, reads the UART receiving buffer data, adds information such as UART interface address and verification, and transmits the information to the CPU, and the data frame format sent to the CPU by the main controller module is as shown in fig. 5. If a plurality of UART interfaces receive data sent by UART interface equipment at the same time, the main controller module responds according to the priority of each UART interface, and the UART interface data with high priority is transmitted first.
The UART interface expansion circuit designed by the invention is described by adopting a hardware description language VHDL or Verilog HDL, is realized by using an FPGA (field programmable gate array) or CPLD (complex programmable logic device), designs a main controller module, a UART controller module, a baud rate generator module, a data transmitting module and a data receiving module by using internal logic resources of a programmable logic device, and designs a data receiving cache and a data transmitting cache module by using internal storage resources of the programmable logic device. The number of the UART interfaces expanded by the circuit is related to the IO number of the used programmable logic device and the internal logic resource number, and can reach more than 20.
When the system works, the CPU sends a control frame to the main controller module through a parallel bus, the control frame is composed of frame sections of frame type, destination address, baud rate, data bit, parity check, stop bit, priority, check and the like, wherein the length of the frame type is 1 byte and is defined as 0x01, the length of the destination address is 1 byte, the length of the baud rate is 3 bytes, the data bit, the parity check and the stop bit occupy 1 byte, the length of the data bit is 4 bits, the length of the parity check is 2 bits, 00 represents no check, 01 represents odd check, 10 represents even check, the length of the stop bit is 2 bits, 00 represents 1 stop bit, 01 represents 1.5 stop bit, 10 represents 2 stop bits, the length of the priority is 1 byte, and the CRC-8 check algorithm is adopted, and the length is 1 byte. And the main controller module forwards the received data to the corresponding UART controller module according to the destination address of the received control frame, and simultaneously performs CRC (cyclic redundancy check) on the received data, if the CRC is correct, the main controller module sends a receiving response to the CPU after the data reception is finished, and if the CRC is wrong, the CPU does not send a receiving response signal, and the CPU retransmits the data. The UART controller module receives the control frame forwarded by the main controller module, sets UART communication parameters according to frame information, and the baud rate generator module performs frequency division according to the baud rate parameters to generate corresponding clock frequency.
The CPU sends a data frame to the main controller module through the parallel bus, the data frame is composed of frame sections of frame type, destination address, data, check and the like, wherein the length of the frame type is 1 byte and is defined as 0x02, the length of the destination address is 1 byte, the length of the data section is determined by actually transmitted data, and the CRC-8 check algorithm is adopted, and the length of the data section is 1 byte. The main controller module forwards the received data to the corresponding UART controller module according to the destination address of the received data frame, and simultaneously performs CRC (cyclic redundancy check) on the received data, if the CRC is correct, the main controller module sends a receiving response to the CPU after the data reception is finished, and if the CRC is wrong, the CPU does not send a receiving response signal, and the CPU retransmits the data. The UART controller module receives the data frame forwarded by the main controller module, writes the data frame into the sending buffer, and outputs the data in the sending buffer to the UART interface equipment through the data sending interface by the data sending module.
A data receiving module in the UART interface control unit writes the received data into a receiving buffer memory after receiving the data sent by the UART interface equipment, the receiving buffer memory is designed as an asynchronous FIFO (first-in first-out memory), when the written data reaches a certain length, the UART controller triggers a main controller module, if the main controller module is in an idle state, the main controller module sends an interrupt request to a CPU, after receiving an interrupt response returned by the CPU, the main controller module sends a read command to the UART controller module, reads the data in the UART receiving buffer memory, generates a data frame by packaging and transmits the data frame to the CPU, the data frame consists of frame sections of frame types, source addresses, data, check and the like, wherein the frame type length is 1 byte, the frame type is defined as 0x03, the source address length is 1 byte, the UART interface address is used for receiving the data, the data section length is determined by actual transmission data, and, the length is 1 byte. And the CPU performs CRC on the received data, if the CRC is correct, a response signal is sent to the main controller module, if the CRC is wrong, the response signal is not sent, and if the main controller module does not receive the response signal, the data is retransmitted. If a plurality of UART interfaces simultaneously receive data sent by UART interface equipment, each UART controller simultaneously writes the received data into respective data receiving buffer memory and respectively sends a trigger signal to the main controller module, the main controller module responds according to the priority of each UART interface, the UART interfaces with high priority are responded firstly, and the UART interfaces with low priority are responded in sequence after the data transmission of the UART receiving buffer memory with high priority is completed. The CPU processor and the main controller perform data transmission under the synchronization of a connection clock, and the clock frequency is related to the performance of the processor and the performance of the programmable logic device. The data transmission rate between the main controller module and the UART controller module is related to the internal operating clock frequency of the programmable device, which can usually reach over 100 MHz.
While the invention has been described in further detail in connection with specific embodiments thereof, it will be understood that the invention is not limited thereto, and that various other modifications and substitutions may be made by those skilled in the art without departing from the scope of the invention, which is to be determined by the claims appended hereto.
Claims (3)
1. A UART interface extension circuit based on a programmable logic device, wherein the programmable logic device is provided with a plurality of UART interfaces connected with UART interface equipment, and is characterized in that: the UART interface extension circuit comprises a main controller module and UART interface control units with the same number as the UART interfaces, wherein each UART interface control unit corresponds to one UART interface, each UART interface control unit comprises a UART controller module of the UART interface corresponding to the UART interface control unit, a baud rate generator module, a data sending module, a data receiving cache module and a data sending cache module, the main controller module defines a group of independent addresses for each UART interface, and the corresponding addresses of the UART controller module corresponding to the UART interfaces are stored in each UART controller module.
2. The UART interface extension circuit based on the programmable logic device as claimed in claim 1, wherein: the programmable logic device is connected with the CPU processor through an 8-bit data bus, the CPU sends a data frame comprising destination address information to the main controller module, and the main controller module forwards received data to a corresponding UART interface control unit according to the destination address information in the data frame; the data frame comprises a frame type, a destination address, configuration parameters and check information, wherein the configuration parameters comprise a baud rate, data bits, parity check, a stop bit and priority.
3. The UART interface extension circuit based on the programmable logic device as claimed in claim 2, wherein: the UART interface equipment connected with each UART interface sends data to the UART interface control unit corresponding to the corresponding interface of the UART interface equipment through the UART interface connected with the UART interface equipment, the UART interface control unit receives the data through the data receiving module and writes the data into the data receiving buffer module, the UART interface control unit sends a trigger signal to the main controller module through the data sending module, if the main controller module is in an idle state, the main controller module sends an interrupt request to the CPU processor, the CPU processor sends an interrupt response to the main controller module after receiving the interrupt request, the main controller module sends a read command to the UART interface control unit sending the trigger signal after receiving the interrupt response, the UART control module transmits the data received in the data receiving buffer module to the main controller module after receiving the read command, the main controller module packs the received data, and packs the UART interface address, the UART interface address, Transmitting the data and the check information to a CPU; if a plurality of UART interface control units simultaneously send trigger signals to the main controller module through the data sending module, the main controller module responds according to the priority order of the UART interfaces corresponding to the UART interface control units corresponding to the trigger signals, the data of the UART interface control units corresponding to the UART interfaces with high priority respond first, and the priority information of the UART interface control units is stored in the main controller module.
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Cited By (6)
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| CN113204512A (en) * | 2021-05-08 | 2021-08-03 | 山东英信计算机技术有限公司 | Data transmission method, system, medium and equipment based on UART bus |
| CN114490474A (en) * | 2021-12-28 | 2022-05-13 | 武汉微创光电股份有限公司 | System for realizing extension of multi-path UART (universal asynchronous receiver/transmitter) interface through CPLD (complex programmable logic device) |
| CN115022159A (en) * | 2022-06-27 | 2022-09-06 | 汉中一零一航空电子设备有限公司 | Control equipment main controller redundancy backup system and method |
| CN115237036A (en) * | 2022-09-22 | 2022-10-25 | 之江实验室 | Full-digitalization management device for wafer-level processor system |
| CN115499032A (en) * | 2022-09-01 | 2022-12-20 | 上海盛本智能科技股份有限公司 | One-to-many UART communication method |
| CN116737635A (en) * | 2023-08-08 | 2023-09-12 | 石家庄科林电气股份有限公司 | Interface expansion method, electronic system, electronic device and medium of power distribution terminal |
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Application publication date: 20210223 |