RU175049U9 - COMMUNICATION INTERFACE DEVICE SpaceWire - Google Patents

Abstract

The utility model “SpaceWire communication interface device” refers to digital computing, namely, high-speed local area networks for airborne systems. The technical result is the creation of network structures for collecting and transmitting data from multiple sensors based on SpaceWire technology by serial connection of two-port communication interface devices SpaceWire among themselves. A sensor controller can be connected to each device via the ANV bus interface. At the same time, the ability to implement data transfer from an arbitrary set of sensors to one SpaceWire port is achieved, fully using its bandwidth to load the data processor connected to it as fully as possible. The device supports packet switching SpaceWire and the transport layer protocol RMAP for configuring the device itself and accessing the sensor controller data. The closest to the claimed device is a communication interface device (RF Patent for the invention No. 2460124), which is a SpaceWire port and contains a data output unit, a receiving unit data, control unit, data and communication flow control unit. The technical result is achieved by the fact that a second SpaceWire port, a data packet switching unit, two control units are introduced into the device transmission speed, two blocks for generating transmission clock signals, a block of mode / status registers, a block of routing registers, a packet selector, an RMAP protocol shaper, an ANV Master interface controller and an ANV Slave interface controller, and new communications. 1 s.p. crystals, 12 ill., 26 tab.

Description

This utility model is a device (system) of communication interfaces and relates to digital computing, namely to high-speed communication systems for multiprocessor computing systems with distributed information processing and local area networks based on SpaceWire technology [ECSS Standard ECSS-E-50 -12A, "SpaceWire, Links, Nodes, Routers and Networks", Issue 1, European Cooperation for Space Data Standardization, February 2003]. This device is intended, in particular, to collect information from a variety of sensors and other similar modules that do not have processor control, when building distributed computing systems used in embedded applications, including on-board computer systems.

As an analogue from the prior art, a communication interface device is known [PATENT GB No. 91304711.4. Communication interface for serial transmission of variable length data tokens / Priority 05/25/90, No. 9011700. Data of filing 05/24/91. Data of publication 11/27/91. Bulletin 91/48 of European Patent Office. Publication number 0458648 A2] for use in a communication system connecting at least two computers, the communication interface device comprising a data output unit, a data receiving unit, a control unit and a data flow control unit.

In this device, the use of DS-coding allows you to slightly reduce power consumption without reducing speed characteristics compared to previously known analogues due to the fact that only one signal can change at a time, either on gating line S or on data line D of the communication interface . The DS encoding method used in the device is characterized in that the data signals on the data line D are a sequential stream of data bits representing a sequence of signal changes. only when the data bits change their value, while the strobe signal on the gating line S changes the value only at the bit boundary at those moments when the data signal does not change its state, thus eliminating simultaneous changes in the serial flow of data and strobe signals. In the data receiving unit, by combining the D-signal and S-signal using the XOR function, a clock signal is generated that changes its state in each bit interval, which allows its use to receive data signals from data line D and further process bit data in a communication interface device, such as this is required by the SpaceWire standard.

The disadvantage of this device is the limited functionality when organizing the collection of information from sensors in a distributed computing system. This is due to the fact that this device, realizing the functions of an input / output port, is intended for use in a communication system that connects two computers in a distributed system, or two processor modules, or other similar nodes that have software control, between which you want to transfer at high speeds in both directions are large flows of information. In this case, both interacting parties implement a symmetric interface and can effectively use the capabilities of their ports for high-speed data reception and transmission. If you need to connect another type of module to the high-speed port of the computer, which can transmit information from the low-speed sensor using this communication interface device, then the high-speed port of the computer will be used inefficiently, since its throughput allows you to receive information from many similar sensors. However, to connect more than one sensor to one port of a computer or processor unit does not allow the limited functionality of this communication interface device.

Known switching device that provides data switching between multiple ports - switch LINK ports [Patent RU No. 2405196 C1. LINK Port Switch / Application No. 2009116950/08, 05/04/2009. Publ. 11/27/2010. Bull. No. 33], containing N LINK ports, N LINK port controllers, a switching matrix, a register block, an address issuing protocol decoder, a response message shaper, a comparison circuit, a constant, a LINK port number counter, an RCP-2 protocol shaper.

The disadvantage of this LINK port switch is that it cannot switch the data presented in a serial code in accordance with the SpaceWire standard, has high power consumption and therefore has limited use, since it cannot be used in on-board computer systems and in embedded applications.

The closest analogue to the claimed is a communication interface device [Patent RU No. 2460124 C1. Communication Interface Device / Application No.2012121016, 05.26.2010. Publ. 08/27/2012. Bull. No. 24, 2012], which is an input-output port from the host system to the serial channel in accordance with the SpaceWire standard and contains a data output unit, a data reception unit, a control unit and a data flow control unit, the output of the request for the output of the flow control symbol of which is connected with the input of the data output unit of the same name, the output of the readiness for issuing the flow control symbol which is connected to the input of the data flow control unit of the same name, inputs for acknowledging the receipt of the flow control symbol and acknowledging the information the symbol of which is connected respectively to the outputs of the data receiving unit and the inputs of the control unit of the same name, the output of the character encoding error of which is the output of the character encoding error of the SpaceWire port system interface, the reset input of the SpaceWire port system interface is the reset input of the control unit, the first and second reset outputs of which connected to the reset inputs, respectively, of the data issuing unit and the data receiving unit, the “received NULL” output of which is connected to the same input of the control unit, input for reading data of the SpaceWire port system interface, the input of the data receiving unit of the same name, data outputs for receiving and data readiness for receiving which are the corresponding outputs of the SpaceWire port system interface, the credit error of the SpaceWire port system interface is the same output of the data flow control unit and connected to the same the input of the control unit, the third output of the reset of which is connected to the reset input of the control unit of the data flow, inputs confirm the issuance of information from mvola and permits reception of which data are connected with similar yields, respectively, the block data output and the data receiving unit, an output ready dispensing system interface device data is the same name output data output unit inputs data recording and for discharging port system interface SpaceWire are appropriate data output unit inputs.

This device provides operation at frequencies up to 400 MHz in accordance with the SpaceWire standard, supports encoding of data bytes received in the data packet through the system port interface in the form of SpaceWire characters and their subsequent transmission to the serial communication port interface (SpaceWire link), as well as decoding SpaceWire characters when they are received from the communication interface of the port and the subsequent output of the received bytes of data in the form of data packets through the system interface of the port. That is, this device, which is a single SpaceWire port, allows you to send and receive data packets of arbitrary size in the form of a stream of data bits and gates through the SpaceWire link. However, it can transmit information received from one sensor to the SpaceWire communication interface, since it is possible to connect one host system to the port system interface.

The disadvantage of this technical solution is the limited functionality when organizing the collection of information from sensors in a distributed computing system, because on the basis of two of these devices you can create a high-speed communication channel (SpaceWire link served by two input / output ports) between two host systems: processor modules, or other similar nodes with software control. When one host system is a processor module for collecting and processing data and through the link receives a stream of information from the sensor, the controller of which is the second host system, then, as a rule, the speed of data coming from the sensor is many times less than the bandwidth of the SpaceWire link ( 400 Mbps) and the processor module for data processing in this case remains unloaded. The limited functionality of the second port on the other end of the link does not allow to increase the flow by combining the transmitted data from a certain set of low-speed sensors through the link and the input / output port of the processor data processing module for efficient use of its processing power. This technical solution used to implement the I / O port does not allow connecting more than one host system to its system interface, therefore several sensor controllers cannot be combined into one pool.

Overcoming of these limitations allows the packet switching used in SpaceWire technology using the SpaceWire switch, which is additionally included in the switching system and puts the link between the two host systems in break. As a rule, such switches have a sufficient number of ports, which allows you to connect the required number of sensor controllers to them. However, the SpaceWire switch is a separate external device in relation to this technical solution. This is a much more complex and energy-consuming device, and therefore not in all projects its use will be justified not only from a technical, but also from an economic point of view.

Another functional limitation is manifested when organizing the interaction of this technical solution with the host system. Through the system interface of the SpaceWire port and the host system, a stream of bytes is received, received or transmitted as data packets. Therefore, the host system must be able to support the functions of the network layer and the higher transport layer of the OSI reference model, as well as solve the administrative tasks associated with setting up and configuring the port for implementing the SpaceWire link protocols. This range of tasks is solved if the host system is a computer or processor module with software control. To control the operation of the sensor, a controller with a control logic based on strict logic is sufficient, and the use of a processor module with program control in this case is an excess option that is not justified from a technical or economic point of view, but is completely unacceptable for on-board systems.

The present utility model is based on the task of developing the SpaceWire communication interface device (two-port), with the possibility of packet switching between ports, as well as connecting terminal nodes (host systems) in a lightweight version without software control and requiring only a control machine with hard logic that is inherent in sensor controllers.

The technical result of the proposed solution is to expand the scope of the SpaceWire communication interface device by expanding the device’s functionality: it is possible to build various configurations by connecting the SpaceWire communication interface devices two-way in series with each other and, as a result, the ability to implement data transmission from an arbitrary set of sensors to one port is achieved SpaceWire, making full use of its bandwidth, To download the connected data acquisition and processing engine as fully as possible. In addition, such communication systems have the ability to scale, allowing you to connect an arbitrary set of processors for collecting and processing data with the required number of sensors.

The technical result is achieved by the fact that in the proposed solution, the SpaceWire communication interface device for use in a communication system that combines at least one computer or data processor with one or more terminal nodes, provides a serial connection of devices through the SpaceWire communication channel, and in the device of the SpaceWire communication interfaces containing the SpaceWire port, which includes a data output unit, a data reception unit, a control unit, and a data flow control unit s, the output of the request for issuing a flow control symbol which is connected to the input of the data output unit of the same name, the output of the readiness of issuing the flow control symbol of which is connected to the input of the data flow control unit of the same name, the inputs of acknowledging the receipt of the flow control symbol and confirming receipt of the information symbol of which are connected respectively with the same name inputs of the control unit and the same outputs of the data receiving unit, the output of the character encoding error of which is the output of the coding error the port of the system interface of the port and is connected to the input of the control unit of the same name, the first and second reset outputs of which are connected to the reset inputs of the data output unit and data reception unit, the data and gating inputs of which are inputs of the communication channel for receiving the SpaceWire port, the communication channel for issuing the SpaceWire port are data outputs and gates of the data output unit, the input of the data output synchronization of which is the input of the data output synchronization of the port system interface, the input is read The data of the system interface of the port receiver is the input of the data receiving unit of the same name, the data outputs for receiving and readiness of data for receiving which are the corresponding outputs of the system interface of the port receiver, the credit error output of the port system interface is the same output of the data flow control unit and is connected to the unit input of the same name control, the third output of the reset of which is connected to the reset input of the data flow control unit, inputs confirm the issuance of informational sim ol and data reception permissions of which are connected to the outputs of the same data output unit and data reception unit, the port system interface reset input is the control unit reset input, the port transmitter system interface readiness output output is the same output as the data output unit, recording and data inputs for the output of the system interface of the port are the corresponding inputs of the data output unit, the input of the local port synchronization is connected to the inputs of the local synchronization unit board, data flow control unit, data receiving unit, data output unit, the flow control symbol transmitting permission input of which is connected to the same output of the control unit, the disconnect error output of the data receiving unit is connected to the same input of the control unit and is the output of the disconnection of the port system interface the output of the connection of the system interface of the port is the output of the connection of the data receiving unit and connected to the input of the control unit of the same name, introduced the second SpaceWire port, a data packet switching unit, two transmission rate control units, two transmission clock generation units, a mode / status register unit, a routing register unit, a packet selector, RMAP protocol shaper, an ANV Master interface controller and an ANV Slave interface controller, with outputs the system interface of each of the two SpaceWire ports are connected respectively to the status input groups of the same name port of the mode / status register block, and are also connected respectively to the presence of sync inputs onization of the transmission rate control units, the speed change outputs of which are connected respectively to the inputs of the transmit clock generation units, the outputs of which are connected to the data output synchronization inputs of each of the two SpaceWire ports, in each of which the status control inputs of the control unit are the inputs of the same name of each of the two SpaceWire ports and connected respectively to the first and second outputs of the state control of the block of registers of the mode / state, the first and second inputs and outputs of the state of which are connected respectively to the status input / output of each of the speed control units, the third status input / output of the mode / status register block is connected to the status input / output of the data packet switching unit, the first and second transmission inputs and outputs of which are connected respectively to the same input / output of each SpaceWire ports, the input-output of which are connected respectively to the first and second input-output of the receiving unit of the packet switching data packets, the input-output addressing of which is connected to the same input the output of the routing register block, the information input-output of which is connected to the first control input-output of the ANV Slave interface controller, the second control input-output of which is connected to the information input-output of the mode / state register block, the fourth status input-output of which is connected to the input- status output of the RMAP protocol shaper, the first and second information inputs / outputs of which are connected respectively to the first information input / output of the ANV Master interface controller and input / output of the packet selector, the input-output of the packet data of which is connected to the input-output of the packet data switching unit of the same name, the inputs and outputs of the ANV bus interface are the same inputs and outputs of the ANV Master interface controller, the second information input-output of which is connected to the information input-output the Slave ANV interface controller, the reset input of which is connected to the reset inputs of the Slave ANV interface controller, RMAP protocol shaper, packet selector, routing register block, re register block the mode / state of the two transfer rate control units and with the reset inputs of each of the two SpaceWire ports and is the input of the initial installation of the device, the local synchronization input of which is connected to the local synchronization inputs of each of the two SpaceWire ports and with the synchronization inputs of the two transfer speed control units, block mode / status registers, routing register block, packet selector, RMAP protocol shaper, ANV Master interface controller and ANV Slave interface controller.

Preferably, the data packet switching unit comprises an adaptive switching unit, a broadcasting unit, a switching matrix, two SpaceWire port controllers, each of which consists of SpaceWire port transmit and receive control units, and a FIFO port controller, consisting of transmit and receive control units, the inputs the reset and local synchronization of the packet switching unit are connected respectively to the inputs of the adaptive routing unit, the broadcasting unit, and the controller receiving and transmitting control units via the FIFO and each of the two SpaceWire port controllers, the first inputs and outputs of the control units for receiving controllers of the first and second SpaceWire ports are the first and second input and output of the receiving unit for switching data packets, the first inputs and outputs of the control units for transmitting controllers of the first and second SpaceWire ports are respectively the first and second input-output of the transmission unit for switching data packets, the second inputs and outputs of the control units for receiving controllers of the first and second SpaceWire ports and the FIFO port are connected respectively respectively, with the first, second, and third inputs and outputs of the switching matrix, the second inputs and outputs of the transmission control units of the controllers of the first and second SpaceWire ports and the FIFO port are connected respectively to the first, second, and third inputs and outputs of the switching matrix, the first inputs and outputs of the blocks the control of reception and transmission of the FIFO port controller are connected to the input-output of packet data of the data packet switching unit, the input-output addresses of the address information of the control units of the first and second controllers the second SpaceWire ports, control units for receiving and transmitting the FIFO port controller, adaptive routing and broadcasting blocks are connected to the input-output addresses of the data packet switching unit, the status input-output of which is connected to the input-outputs of the FIFO port controller receiving and transmitting control units of the same name, blocks control of reception and transmission of controllers of the first and second ports of SpaceWire, adaptive routing and broadcasting blocks, request outputs of control units of reception of controllers of the first and second SpaceWire mouths are connected to the corresponding bits of the request bus, which are connected respectively to the request inputs of the transmission control units of the controllers of the first and second SpaceWire ports, confirmation outputs of the transmission control units of the controllers of the first and second SpaceWire ports are connected to the corresponding bits of the confirmation bus, which are connected respectively to the acknowledgment inputs of the blocks control reception of the controllers of the first and second ports of SpaceWire, the inputs and outputs of the selection of which are connected respectively to the first and the second inputs and outputs of the selection of the adaptive routing unit, the third input-output of the selection of which is connected to the input-output of the selection of the reception control unit of the FIFO port controller, the control inputs and outputs of the control units of the controllers of the first and second SpaceWire ports which are connected respectively to the first and second inputs control outputs of the broadcasting unit, the third and fourth control outputs of which are connected respectively to the control inputs of the transmission control units of the controllers of the first and orogo ports SpaceWire, fifth input-output broadcast regulation block connected to the input-output port regulation reception FIFO control unit controller, the sixth broadcast regulation block output is connected to the input port of FIFO controller regulating the transmission control unit.

The device proposed in the framework of this utility model is intended for organizing high-speed transmission of information from one or an arbitrary set of data acquisition modules (sensors) to a data processor or computer via a duplex serial communication channel - the SpaceWire communication interface, and can be used to create on-board computer systems and networks for use in wide areas, as well as in various embedded applications requiring low power consumption laziness and high speed. The proposed technical solution provides the opportunity to increase the speed of data transfer through the SpaceWire communication channel, that is, the issuance and reception of data in the communication interface device while limiting the growth of energy consumption by dividing all elements of the device into two temporary domains. The first time domain includes transmitter elements in the SpaceWire port of the device that directly issue and operate at the frequency of data output to the communication interface, as well as receiver elements in the SpaceWire port of the device that directly receive data bits from the communication channel and operate at the frequency of received signals from the communication interface . The second time domain, which includes elements of the device that prepares the output data characters and processes the received data characters, operates at the local clock frequency of the device. To increase the throughput of the SpaceWire communication interface, the frequency of data output can be increased several times in comparison with the frequency of local synchronization. Since the number of triggers operating at the maximum data transfer frequency is minimized, this helps to reduce power consumption. This device can be effectively used to create distributed on-board systems for collecting and processing large amounts of data received from sensors. By expanding the functionality of this technical solution, the requirements for the structure of hardware and software of terminal information collection modules are simplified, which provide the connection of sensors to the communication interface of SpaceWire. The complexity of such sensor controllers can be significantly reduced, since their functions of connecting to the SpaceWire communication interface are simplified and can be implemented on the basis of a machine with strict logic. This device provides the ability to independently read data from the sensor, stored in the memory of the data acquisition module (sensor controller), via the ANV bus interface, form data packets in accordance with the SpaceWire standard and send them to one of two or both SpaceWire communication channels for transmission to data processor (s). In addition, in order to fully use the bandwidth of the SpaceWire communication channel to load the data processor into it, it is necessary to switch data streams from more than one sensor. The solution to this problem is provided by connecting the proposed devices in series via SpaceWire links in a bus or ring type configuration, as a result of which it is possible to switch data streams from the required number of sensors to fully load the SpaceWire communication channel to which the data processing processor is connected.

Individual elements of the device can be implemented by standard means from the given field of technology (circuitry solutions), and only the system solution proposed in the framework of this utility model allows to achieve the corresponding technical result, since only the totality of the features proposed in the utility model formula provides these advantages in comparison with analogues of the prior art.

The essence of this technical solution is explained in detail by the description with reference to the drawings, where in FIG. 1 is a structural diagram of a device; FIG. 2 is a block diagram of a packet data switching unit; FIG. 3 is a functional diagram of the SpaceWire port, in FIG. 4 is a functional diagram of a reception control unit; FIG. 5 is a functional diagram of a transmission control unit; FIG. 6 is a state machine graph describing the operating modes of the SpaceWire port; FIG. 7 is a state machine of the reception control unit of the SpaceWire port controller, in FIG. 8 is a state machine of a transmission control unit of a SpaceWire port controller; FIG. 9 is a timing chart for executing RMAP write and read commands; FIG. 10 illustrates examples of generating the path address of SpaceWire data packets; FIG. 11 - examples of network structures using these devices, FIG. 12 is an embodiment of sequentially connecting devices in a “chain” type structure.

As shown in FIG. 1, the proposed device contains a block 1 for switching data packets, two ports 2 and 3 SpaceWire, two blocks 4 and 5 for speed control, two blocks 6 and 7 for generating transmission clock signals, block 8 registers of mode / state, block 9 registers of routing, selector 10 packets , RMAP protocol driver 11, ANV Master interface controller 12, ANV Slave interface controller 13, inputs 14 of the communication channel for receiving the first SpaceWire link, outputs 15 of the communication channel for issuing the first SpaceWire link, inputs 16 for the communication channel for receiving the second SpaceWire link, you odes 17 of the communication channel for issuing the second SpaceWire link, inputs and outputs 18 of the ANV bus interface of the device, input 19 of the initial installation of the device, input 20 of the local synchronization of the device, outputs 21 and 22 of the system interface, inputs 23 and 24 of synchronization of data output, control inputs 25 and 26 state, the first inputs and outputs of reception 27 and transmission 28, the second inputs and outputs of reception 29 and transmission 30, reset input 31, local synchronization input 32, status input-output 33, addressing input-output 34, packet data input-output 35, input-output 36 data, the first information input input-output 37, input-output 38 status, information input-output 39, information inputs-outputs 40 and 41, the first input-output 42 status, the second input-output 43 status, outputs 44 and 45 of the speed change.

Unit 1 switching data packets (see Fig. 2) contains an adaptive switching unit 46, a broadcasting unit 47, a switching matrix 48, two SpaceWire ports 49 and 50, a FIFO port controller 51, and a reception control unit 52 included with each of the controllers 49, 50 and 51, the transmission control unit 53, which is part of each of the controllers 49, 50 and 51, the second input-output 54 of the transmission and 55 transmission of the controller 49 of the first SpaceWire port, the second input-output 56 of the transmission and 57 of the transmission of the second controller 50 SpaceWire ports, second I / O 58 receive and 59 transmit control RA 51 FIFO ports, 60 request bus, 61 acknowledgment bus, first 64 and second 65 selection inputs and outputs, third 66 selection inputs and outputs, first 68 and second 69 control inputs and outputs, third 70 and fourth 71 control outputs, fifth 72 input-output regulation and the sixth 73 output regulation.

The SpaceWire port 2 (3) contains (see FIG. 3) a data output unit 75, a data reception unit 76, a data flow control unit 77, a control unit 78, a flow control symbol acknowledgment output 79, an information symbol acknowledgment output 80, an output 81 requests for the issuance of a flow control symbol, first reset output 82, second reset output 83, third reset output 84, disconnect error output 85, output 86 for flow control character output, input 87 for synchronization of data output, inputs 88 for data and 89 gates, outputs 90 data and 91 gates niya, output 92 ready to issue data, input 93 records, input 94 data for output, input 95 data reading, output 96 data for reception, output 97 data availability for reception, input 98 local synchronization, input 99 reset, output 100 credit errors, symbol encoding error output 101, connection establishment output 102, flow control symbol transmission permission output 103, information symbol output confirmation output 104, data reception permission output 105.

The reception control unit 52 contains (see FIG. 4) a data translation and buffering unit 106, an input interface control unit 107, an output port selection unit 108, an output port request unit 109, a channel switching control unit 110, a received data input 111 (Data_in) , data setting input 112 (Valid_in), ready output 113 (Re_out), data output 114 (Data_out), data setting output 115 (Valid_out), ready input 116 (Re_in), 117 request output, 118 confirmation input, packet header output 119 , output 120 of the current state, output 121 of a sign of deletion, output 122 of the original set of mouths, output 123 signs of receiving grants, output 124 signs of channel termination, output 125 of an erroneous packet address, output 126 of the vector of output ports.

The transmission control unit 53 contains (see FIG. 5) an arbitration unit 127, a status unit 128, a request input 62, a confirmation output 63, a channel shutdown output 129, a current status output 130.

The packet data switching unit 1 is intended for packet switching in accordance with the SpaceWire standard either between the first inputs / outputs of reception 27 and transmission 28 on the one hand and second inputs and outputs of reception 29 and transmission 30 on the other side, or between the first inputs and outputs of reception 27 and transmitting 28 on the one hand and input-output 35 of packet data on the other hand, or, finally, between the second inputs-outputs of receiving 29 and transmission 30 on the one hand and input-output 35 of packet data on the other hand. The first input-output of reception 27 of the data packet switching unit 1 is connected to the input-output of the reception of the first SpaceWire port 2. The first input-output of the transmission 28 of the data packet switching unit 1 is connected to the transmission input-output of the first SpaceWire port 2. The second input-output of the reception 29 of the data packet switching unit 1 is connected to the input-output of the reception of the second SpaceWire port 3. The second input-output of the transmission 30 of the data packet switching unit 1 is connected to the transmission input-output of the second SpaceWire port 3. The packet data input-output 35 of the data packet switching unit 1 is connected to the packet data input-output of the packet selector 10. The reset input of block 1 is the input 19 of the initial installation of the device. The local synchronization input of block 1 is the input 20 of the local synchronization of the device.

Port 2 (3) SpaceWire is designed to receive a data packet from a communication channel and transfer a data packet to a communication channel in accordance with the SpaceWire standard. The data and gating inputs of SpaceWire port 2 (3) are inputs 14 (16) of the communication channel for receiving the first (second) link of the SpaceWire device. The data and gating outputs of SpaceWire port 2 (3) are outputs 15 (17) of the communication channel for issuing the first (second) link of the SpaceWire device. The outputs 21 (22) of the system interface of port 2 (3) SpaceWire are connected to the group of status inputs of the first (second) port of the block 8 of the mode / state registers and to the inputs of the presence of synchronization of the transmission rate control block 4 (5). The reset port 31 input 2 (3) SpaceWire is the input 19 of the initial installation of the device. The input 32 of the local synchronization of port 2 (3) SpaceWire is the input 20 of the local synchronization of the device.

The speed control unit 4 (5) is designed to dynamically control the speed of outputting data bits to the SpaceWire link through port 2 (3) during operation of the device in order to achieve the highest possible throughput of the communication channel 15 (17) of transmission, at which the two devices are connected stably exchange data. The output 44 (45) of the speed change of the speed control unit 4 (5) is connected to the input of the transmission clock generation unit 6 (7). The reset input of block 4 (5) is the input 19 of the initial installation of the device. The local synchronization input of block 4 (5) is the input 20 of the local synchronization of the device.

Block 6 (7) of the formation of the transmission clock signals provides, in accordance with the speed coefficients determined by block 4 (5), the generation of a sequence of Tx_PLL clock signals that specify the clock bit rate of the data bits in the SpaceWire port 2 (3). The output of the transmission clock generation unit 6 (7) is connected to the input 23 (24) of the synchronization of the data output of the port 2 (3) SpaceWire.

Block 8 registers of the mode / state forms the configuration memory of the device and is intended for fixing signs of the state of the blocks of the device and storing software settings that are required to control the operating modes of the device. The first (second) output 25 (26) of the state control unit 8 registers of the mode / state is connected to the input of the state control of the port 2 (3) SpaceWire. The first (second) state input / output 42 (43) of the block 8 of the mode / state registers is connected to the status input / output of the speed control block 4 (5). The third input-output state of the block of registers 8 mode / state is connected to the input-output 33 of the state of the unit 1 switching of data packets. The fourth input-output status block of registers 8 mode / status is connected to the input-output 38 of the state of the shaper 11 of the RMAP protocol. The reset input of block 8 is the input 19 of the initial installation of the device. The local synchronization input of block 8 is the input 20 of the local synchronization of the device. The list of registers of block 8 are given in table. one.

Block 9 routing registers is designed to store the addresses of the terminal nodes of the SpaceWire network used to select routes when switching packets in accordance with the SpaceWire standard. The addressing input-output of the block 9 of the routing registers is connected to the input-output 34 of the addressing contains a block 1 switching data packets. The reset input of the block 9 routing registers is the input 19 of the initial installation of the device. The local synchronization input of block 9 is the input 20 of the local synchronization of the device.

The packet selector 10 is designed to support the functions of the configuration port in this device and allows receiving data packets from the SpaceWire network containing the RMAP command for this device and transmitting data packets containing the response to the RMAP command to the SpaceWire network. The input-output 36 of data of the packet selector 10 is connected to the second information input-output of the shaper 11 of the RMAP protocol. The reset input of the packet selector 10 is the input 19 of the initial installation of the device. The local synchronization input of the selector 10 is the local synchronization input 20 of the device.

The RMAP protocol shaper 11 is designed to interpret the RMAP protocol commands addressed to this device and provides transactions (read / write operations) with the registers of the configuration space of this device or the memory of the terminal node via the ANV bus interface and sending responses to the executed commands. The first information input-output 37 of the shaper 11 of the RMAP protocol is connected to the first information input-output of the controller of the ANV Master interface. The reset input of the driver 11 is the input 19 of the initial installation of the device. The local synchronization input of the driver 11 is an input 20 of the local synchronization of the device.

The ANV Master interface controller 12 provides for splitting the transaction flow into transactions addressed to the device’s internal configuration space and external transactions to the terminal node memory connected to the ANV bus. The second information input-output of the controller 12 of the ANV Master interface is connected to the information input-output 39 of the controller 13 of the ANV Slave interface. The inputs and outputs of the controller 12 of the ANV Master interface are the inputs and outputs 18 of the bus interface of the ANV device. The reset input of the controller 12 of the ANV Master interface is the input 19 of the initial installation of the device. The local synchronization input of the controller 12 of the ANV Master interface is the input 20 of the local synchronization of the device.

The controller 13 of the ANA Slave interface converts single-word and batch transactions arriving on the ANV interface into read and write calls to the synchronous address memory of the device’s internal configuration space. The first control input-output of the controller 13 of the ANA Slave interface is connected to the information input-output 40 of the block 9 of the routing registers. The second control input-output of the controller 13 of the ANA Slave interface is connected to the information input-output 41 of the block 8 of the mode / state registers. The reset input of the controller 13 of the ANV interface Slave is the input 19 of the initial installation of the device. The input of local synchronization the output of the controller 13 of the ANV interface Slave is the input 20 of the local synchronization of the device.

In the data packet switching unit 1, the adaptive switching unit 46 is used to select from a number of equivalent ports the port number to which the data packet will be transmitted at the current time. The status input-output of the adaptive routing unit 46 is connected to the status input 33 of the data packet switching unit 1. The input-output addressing unit 46 adaptive routing is connected to the input-output 34 addressing unit 1 switching data packets. The first input-output of the selection block 46 of the adaptive routing is connected to the input-output 64 of the selection block 52 of the reception control of the controller 49 of the first SpaceWire port. The second input-output of the selection block 46 adaptive routing is connected to the input-output 65 of the selection block 52 of the reception control of the controller 50 of the second SpaceWire port. The third input-output of the selection block 46 adaptive routing is connected to the input-output 66 of the selection block 52 of the reception control of the controller 51 of the FIFO port. The reset input of the adaptive routing unit 46 is the reset input 31 of the data packet switching unit 1. The local synchronization input of the adaptive routing unit 46 is the local synchronization input 32 of the device data packet switching unit 1.

Block 47 broadcasting provides control of the phases of the exchange and change the priority levels of the ports. The status input / output of the broadcasting unit 47 is connected to the status input 33 of the data packet switching unit 1. The addressing input-output of the broadcasting unit 47 is connected to the addressing input 34 of the data packet switching unit 1. The first control input / output of the broadcast unit 47 is connected to the control input / output 68 of the receive control unit 52 of the controller 49 of the first SpaceWire port. The second control input-output of the broadcasting unit 47 is connected to the control input-output 69 of the receiving control unit 52 of the controller 50 of the second SpaceWire port. The third control output of the broadcast unit 47 is connected to the control input 70 of the transmission control unit 53 of the controller 49 of the first SpaceWire port. The fourth control output of the broadcast unit 47 is connected to the control input 71 of the transmission control unit 53 of the controller 50 of the second SpaceWire port. The fifth control input-output of the broadcasting unit 47 is connected to the control input-output 72 of the receiving control unit 52 of the FIFO port controller 51. The sixth control output of the broadcasting unit 47 is connected to the control input 73 of the transmission control unit 53 of the port controller 51.

The switching matrix 48 is a non-blocking cross-switch and provides packet switching between the controllers 49 and 50 of the SpaceWire ports, as well as between them and the controller 51 of the FIFO port. The first input-output of the switching matrix 48 is connected to the second input-output 54 of the block 52 of the reception control of the controller 49 of the first SpaceWire port. The first transmission input-output of the switching matrix 48 is connected to the second input-output 55 of the transmission control unit 53 of the controller 49 of the first SpaceWire port. The second input-output of the switching matrix 48 is connected to the second input-output 56 of the block 52 of the reception control of the controller 50 of the second SpaceWire port. The second input-output of the transfer of the switching matrix 48 is connected to the second input-output 57 of the transmission control unit 53 of the controller 50 of the second SpaceWire port. The third input-output of the switching matrix 48 is connected to the second input-output 58 of the block 52 of the reception control of the controller 51 of the FIFO port. The third input-output of the transfer of the switching matrix 48 is connected to the second input-output 59 of the transmission control unit 53 of the FIFO port controller 51.

The controllers 49 of the first and 50 second ports of SpaceWire are designed to control the reception and transmission of packets through the SpaceWire links connected to SpaceWire ports 2 and 3, respectively. The controller 51 port FIFO is designed to control the reception and transmission of packets for the transport layer generated or received by the shaper 11 of the RMAP protocol. Each of the controllers 49, 50, and 51 includes a reception control unit 52 and a transmission control unit 53.

The reception control unit 52 receives the packet from the input interface of the corresponding port and transfers it to the output interface of one of the ports, the number of which is determined in accordance with the addressing method used. The first inputs and outputs of the reception control unit 52 of the controllers 49 and 50 are respectively the first 27 and second 29 input and output of the reception of the data packet switching unit 1. The first input-output block 52 of the reception control of the controller 51 of the FIFO port is connected to the input-output 35 packet data block 1 switching packet data. The request output of the reception control unit 52 of the controller 49 of the first SpaceWire port is connected to the first bit of the request bus 60. The request output of the reception control unit 52 of the controller 50 of the second SpaceWire port is connected to the second bit of the request bus 60. The request output of the reception control unit 52 of the FIFO port controller 51 is connected to the third bit of the request bus 60. The confirmation input of the reception control unit 52 of the controller 49 of the first SpaceWire port is connected to the acknowledgment bus 61. The confirmation input of the reception control unit 52 of the controller 50 of the second SpaceWire port is connected to the acknowledgment bus 61. The confirmation input of the reception control unit 52 of the FIFO port controller 51 is connected to the acknowledgment bus 61. The reset input of the reception control unit 52 of the controllers 49, 50 and 51 is connected to the reset input 31 of the data packet switching unit 1. The local synchronization input of the reception control unit 52 of the controllers 49, 50 and 51 is connected to the local synchronization input of the data packet switching unit 1. The input-output of the addressing unit 52 of the reception control of the controllers 49, 50 and 51 is connected to the same input-output 34 of the block 1 switching data packets. The input-output state of the block 52 of the reception control of the controllers 49, 50 and 51 is connected to the input-output 33 of the state of the block 1 switching packet data

The transmission control unit 53, in accordance with the requests received from the reception control units 52 of other controllers, selects the input port number from which it receives the next data packet and transfers it to the output interface of its port. The first inputs and outputs of the transmission control unit 53 of the controllers 49 and 50 are the first 28 and second 30 input and output of the transmission unit 1 of the packet data switching, respectively. The request input of the transmission control unit 53 of the controller 49 of the first SpaceWire port is connected to the request bus 60. The request input of the transmission control unit 53 of the controller 50 of the second SpaceWire port is connected to the request bus 60. The request input of the transmission control unit 52 of the FIFO port controller 51 is connected to the request bus 60. The confirmation output of the transmission control unit 53 of the controller 49 of the first SpaceWire port is connected to the first bit of the acknowledgment bus 61. The confirmation output of the transmission control unit 53 of the controller 50 of the second SpaceWire port is connected to the second bit of the acknowledgment bus 61. The confirmation output of the transmission control unit 53 of the FIFO port controller 51 is connected to the third bit of the acknowledgment bus 61. The reset input of the transmission control unit 53 of the controllers 49, 50 and 51 is connected to the reset input 31 of the data packet switching unit 1. The local synchronization input of the transmission control unit 53 of the controllers 49, 50 and 51 is connected to the local synchronization input of the data packet switching unit 1. The input-output of the addressing unit 53 of the transmission control of the controllers 49, 50 and 51 is connected to the same input-output 34 of the block 1 switching data packets. The input-output state of the block 53 of the transmission control of the controllers 49, 50 and 51 is connected to the input-output 33 of the state of the block 1 switching packet data.

In port 2 (3) SpaceWire (see Fig. 3), the data output unit 75 is designed for generating and outputting data symbols from data packets arriving through the data input 94 for output connected to the first (second) input-output of the transmission 28 to the communication interface (30) port 2 (3) SpaceWire, as well as control characters on demand, coming from the output 83 of the request for the issuance of the flow control character of the data flow control unit 77 to the input of the same name of the unit 75. The formats of the characters transmitted via the communication interface are given in Table. 2. The input 93 of the recording block 75 of the data output is connected to the first (second) input-output of the transfer 28 (30) of the port 2 (3) SpaceWire. The output 92 of the readiness of the data output of the data output unit 75 is connected to the first (second) input-output of the transmission 28 (30) of the SpaceWire port 2 (3). Output 92 and inputs 93 and 94 are designed to implement a standard mechanism for writing packet data symbols to a data output unit 75 from a data packet switching unit 1. The recording of packet data symbols in block 75 is clocked from its synchronization input connected to the local synchronization input 98 of SpaceWire port 2 (3). The outputs 86 for the readiness of issuing the flow control symbol and 104 for confirming the issuance of the information symbol of block 75 are connected to the inputs of the data flow control unit 77 of the same name and are intended to implement the lending mechanism necessary for organizing the transmission and reception of data symbols through the communication interface without overflowing the receive buffers of the interacting devices.

The data output unit 75 provides DS-coding of data symbols, control characters and codes and their transmission to the data outputs 90 and gating 91, which are connected to the output 15 (17) of the communication channel for issuing the first (second) SpaceWire link. Data is output at a speed determined by the frequency of the clock signal from the synchronization input of the data output unit 75, connected to the same input 87 of the port 2 (3) SpaceWire. If two or three requests are sent to block 75 for transmitting symbols at the same time, then they are issued to the channel in accordance with the priority: the FCT control symbol has the highest priority, then the Nchar information symbol. If during the sending, for example, FCT, the request to send the flow control symbol is sent again, then after sending the first FCT symbol, the next FCT is generated and issued, in spite of any other requests and the sequence of request installation. If at the time of issuing the current characters in the channel no requests were generated, then the data output unit 75 generates and issues a NULL control code to the channel to support the connection in the SpaceWire link.

Block 76 receiving data provides the initialization of the connection and receiving the bit stream from another device through the inputs 88 of data and 89 gating the communication interface of the device, decoding the received signals and extracting data symbols from the bit stream and transmitting them to block 1 switching data packets through the output 96 of the data for receiving which is connected to the first (second) I / O 28 (30) of the receiving port 2 (3) SpaceWire. The presentation of information in a data packet received in block 1 switching data packets from block 76 receiving data through output 96 of data for reception, is shown in table. 3.

The data readiness output 97 for receiving the data receiving unit 76 is connected to the first (second) input-output 28 (30) of the receiving port 2 (3) SpaceWire. The data reading input 95 of the data receiving unit 76 is connected to the first (second) input-output 28 (30) of the receiving port 2 (3) SpaceWire. Reading packet data symbols from block 76 is clocked from its synchronization input, connected to the local synchronization input 98 of SpaceWire port 2 (3). The output 79 of the reception of the flow control symbol of the data receiving unit 76 is connected to the inputs of the same name of the control unit 78 and the data flow control unit 77 and provides a signal for receiving a control symbol of the flow control. The output 80 of the acknowledgment of the information symbol of the data receiving unit 76 is connected to the inputs of the same name of the control unit 78 and the data flow control unit 77. The output 85 of the disconnect error of the data receiving unit 76 is connected to the same input as the control unit 4 and to the output 21 (22) of the system interface of the port 2 (3) SpaceWire. The output 101 of the character encoding error of the data receiving unit 76 is connected to the input of the control unit 78 of the same name and to the output 21 (22) of the system interface of port 2 (3) SpaceWire. The connection establishment output 102 of the data receiving unit 76 is connected to the same input of the control unit 78 and to the output 21 (22) of the SpaceWire port 2 (3) system interface and is designed to transmit a signal about the detection of a control sequence of bits received from the communication interface from another device and initiating connection with him. The output 105 of the permission to receive data block 76 receiving data, connected to the same input block 77 control the data flow, is designed to notify the presence of sufficient free space in the buffer for receiving data.

The data flow control unit 77 is designed to implement the lending mechanism required when exchanging packet data in duplex mode between two devices through the communication interfaces of the bidirectional SpaceWire link connecting these two devices, taking into account the limited amount of buffer memory for receiving data available for each device in the unit 77 receiving data. The output 81 of the request for the issuance of a flow control symbol of block 77, connected to the same input of the data output unit 75, is intended to initiate the issuance by the flow control block FCT of 75 for the flow control block confirming that there is a free buffer space in the data receiving section 76 for receiving a certain number of data symbols . In the described device, the amount of credit provided when issuing one symbol of flow control, in accordance with the SpaceWire standard, is assumed to be eight. The credit error output 100 of the data flow control unit 77 is connected to the input of the control unit 4 of the same name and to the output 21 (22) of the system interface of the port 2 (3) SpaceWire. The data flow control unit 77 is clocked from the synchronization input connected to the local synchronization input 98 of the SpaceWire port 2 (3).

The control unit 78 is designed to monitor the status of the device upon receipt of signals from the data receiving unit 76 about a change in its status and generation of control signals under the influence of the state machine and the initial setting signal from the reset input connected to the reset input 99 of the SpaceWire port 2 (3). The output 103 of the permission to transmit the flow control symbol of the control unit 78 is connected to the input of the data output unit 75 of the same name and is intended to inform that the state machine of the control unit 78 has switched to a mode permitting the output of flow control symbols. The input 25 (26) of the state control of the port 2 (3) SpaceWire is the same input of the control unit 78. The first 82, second 83 and third 84 reset outputs of the control unit 78 are connected to the reset inputs, respectively, of the data output unit 75, the data reception unit 76, and the data flow control unit 77 and are intended for their resetting. The clocking of the control unit 78 is carried out from the synchronization input connected to the local synchronization input 98 of the SpaceWire port 2 (3).

In the reception control unit 52, the data translation and buffering unit 106 (see FIG. 4) is intended for transmitting data symbols from its input port to the channels of the switching matrix 48 to the transmission control units 53 of the other output ports. The input 111 of the received data of the translation and buffering unit 106 is connected to the inputs of the same name as the input interface control unit 107 and the output port selection unit 108 and is the Data_in input of the reception control unit 52. The data installation input 112 of the data translation and buffering unit 106 is connected to the inputs of the same name as the input interface control unit 107 and the output port selection unit 108 and is the input Valid_in of the reception control unit 52. The ready output 113 is the Reout output of the reception control unit 52. The inputs Data_in and Valid_in and the output Re_out constitute the first (second) input-output 27 (29) of the reception unit 52 of the reception control unit 49 (50) of the first (second) SpaceWire port and the controller 51 of the FIFO port. The data output 114 (Data_out), the data setting output 115 (Valid_out) and the ready input 116 (Re_in) of the data translation and buffering unit 106 are connected to the second input-output 54 (56.58) of the receiving control unit 52. The output 119 of the packet header of the block 106 translation and data buffering is connected to the same input block 107 control the input interface. The reset input of the translation and buffering unit 106 is the reset input 31 of the reception control unit 52 and is connected to the inputs of the input interface control unit 107, the output port selection unit 108, the output port request unit 109 and the channel switching control unit HO. The local synchronization input of the translation and buffering unit 106 is the local synchronization input 32 of the reception control unit 52 and is connected to the inputs of the input interface control unit 107, the output port selection unit 108, the output port request unit 109 and the channel switching unit 110.

The input interface control unit 107 is for determining the current and next state in accordance with the circuit shown in FIG. 7, and issuing the value of the current and previous state to all other blocks. The output 120 of the current state of the input interface control unit 107 is connected to the inputs of the data translation and buffering unit 106, the output port selection unit 108, the output port request unit 109, and the channel switching control unit 110. The output 125 of the erroneous address of the packet is connected to the input-output 33 status of the block 52 of the reception control.

Block 108 selection of output ports is designed to form the correct set of output ports for issuing a received data packet in accordance with the information from the routing table. The output 121 of the delete flag of the output port selection block 108 is connected to the input of the input interface control unit 107 of the same name. The output 122 of the original set of ports of the block 108 of the selection of output ports is connected to the same input of the block 109 of the request for output ports. The output of the address Rt_addr and the output of the installation Rt_valid of the output port selection block 108, the routing information input Rt_data and the readiness input Rt_ready of the output port selection block 108 form the input-output 34 of the address of the reception control unit 52. The output of the initial set of ports Port_nums of the block 108 of the selection of output ports is connected to the input-output 64 (65.66) of the selection of block 52 of the reception control. The correction input Term_p_reg block 108 selection of output ports is connected to the input-output 33 state of the block 52 of the reception control.

The output port request block 109 is designed to generate requests for the output ports in accordance with the current state received from the input interface control unit 107 and the processing phase number received from the broadcast unit 47. The input of the Cur_phase phase number block 109 of the output port requests is connected to the input of the input interface control unit 107 of the same name and connected to the control input / output 68 (70.72) of the reception control unit 52. The output of the Reqs request signals and the output of grant acknowledgment signals Gnt_ack of the block 109 of the output port requests form the output of 117 requests of the reception control unit 52. The input of the Gnts grant signals of the output port request block 109 is the acknowledgment input 118 of the reception control unit 52. The output 123 of the sign of receiving grants of the block 109 of the request for output ports is connected to the same input of the block 110 of the control circuit switching. The output 126 of the output port vector of the output port request unit 109 is connected to the input-output of mode 68 (70, 72) of the reception control unit 52. The input of the signs of the absence of connections Err_reg of the block 109 of the request for output ports is connected to the same input of the block 110 of the control circuit switching and is connected to the input-output 33 of the state of the block 52 of the reception control.

The circuit switching control unit 110 is designed to switch the channels of the switching matrix from the output port transmission control units 53 to this input port reception control unit 52 in accordance with the current state, the eq_port_nums port set vector received from the adaptive group routing unit 46, and the error register state Err_regs ports received from block 8 mode / status registers. The output 124 of the channel sign of the channel switching control unit 110 is connected to the input of the input interface control unit 107 of the same name and to the control input / output 68 (70, 72) of the reception control unit 52. The output control multiplexers back_id block 110 control circuit switching is connected to the second input-output terminal 54 (56, 58) of block 52 of the reception control.

In the transmission control unit 53, the arbitration unit 127 is designed to determine the number of the input port from which the next data packet will be received according to the scheme with dynamic cyclic priorities in accordance with the requests received from the reception control units 52 of these ports. The input of the Reqs request signals of the arbitration unit 127 is connected to the input 62 of the requests of the transmission control unit 53. The input of grant confirmation signals Ack_gnt of the arbitration unit 127 is connected to the input 62 of the requests of the transmission control unit 53. The output of the Gnts grant signals of the arbitration unit 127 is the output of 63 requests from the transmission control unit 53. The output 129 of the channel block of the arbitration unit 127 is connected to the input of the status unit 128 of the same name. The switching control output Forward_in of the arbitration unit 127 is connected to the second transmission input / output 55 (57.59) of the transmission control unit 53. The input of the Cur_phase phase number of the arbitration unit 127 is connected to the input of the state unit 128 of the same name and connected to the control input 68 (70, 72) of the transmission control unit 53. The input of the priority port number of the arbitration unit 127 is connected to the control input 68 (70, 72) of the transmission control unit 53. The reset input of the arbitration unit 127 is a reset input 31 of the reception control unit 53 and is connected to the same input of the status unit 128. The local synchronization input of the arbitration unit 127 is an input 32 of the local synchronization of the transmission control unit 53 and is connected to the same input of the status unit 128.

The state block 128 is designed to determine the current state of the output interface of the port in accordance with the circuit of the state machine shown in FIG. 8. Data input Data, Valid data setting input, and Ready output of state block 127 are connected to the second transmission input-output 55 (57.59) of transmission control unit 53. The output 130 of the current state of the arbitration unit 127 is connected to the input of the arbitration unit 127 of the same name. The output of the Data_out data, the output of the Valid_out data setting, and the Ready ready input of the status block 128 constitute the first input-output 28 (30) of the transmission of the transmission control unit 53 of the first 49 (second 50) port of the SpaceWire controller and the FIFO port controller 51.

The communication interface device SpaceWire operates as follows. In accordance with the SpaceWire standard, the device provides the formation, transmission and switching of data packets. A device containing two SpaceWire ports 2 and 3 performs packet switching between these ports, as well as between them and the packet selector 10, which provides the allocation of RMAP packets for the shaper 11 of the RMAP protocol. RMAP is used by a remote host system (for example, a network administrator) to configure a SpaceWire network, that is, to manage switches, these SpaceWire communication interface devices and terminal nodes that perform, for example, the functions of sensor controllers. Through it, the switches and the claimed devices are configured by setting their operating parameters and setting their routing tables. RMAP can also be used to collect information from terminal nodes connected to SpaceWire communication interface devices. All write and read operations defined in the RMAP protocol are designed so that the sender does not expect to receive acknowledgment packets, and therefore packets containing read and write commands can be sent at any time.

Shaper 11 protocol RMAP provides processing RMAP packets addressed to this device, and sending response RMAP packets. The device provides interaction with the remote host system by executing commands for writing and reading the RMAP protocol, which are generated, for example, by the network administrator, and are executed on this device. In this case, the device supports accessing its configuration memory from the outside, which contains the configuration registers and the routing table, using RMAP protocol commands that are processed by the RMAP protocol generator 11. In addition, using the RMAP write and read commands, the remote host system can access the memory of the terminal node connected to this device via the ANV bus interface.

Ports 2 and 3 of SpaceWire provide the connection of this device to the network through the SpaceWire links. The data packet switching unit 1, which includes (see Fig. 2) two SpaceWire controllers 49 and 50, a FIFO port controller 51 (packet selector 10 is connected to it), provides packet switching in accordance with the SpaceWire standard using a non-blocking switching matrix 48. Packets coming from the SpaceWire network and addressed to this device or terminal node connected to the ANV bus interface 18, the devices are transmitted to the port controller 51 and from there they go through the packet selector 10 to the RMAP protocol generator 11. Packets addressed to other network subscribers are transferred further to the network through ports 2 and / or 3 of SpaceWire. Packets from the shaper 11 of the RMAP protocol through the packet selector 10 and the controller 51 of the FIFO port enter the switching matrix 48 and are transmitted to the network through ports 2 and 3 of SpaceWire. The data packet switching unit 1 supports broadcast mode and adaptive multicast routing.

The ANV bus interface 18 is used by the ANV master interface controller 12 to execute RMAP commands with a logical address other than 0. The commands with logical address "0" are calls to the configuration space of the device itself. Upon receipt of the correct RMAP command in the shaper 11, the ANV master interface controller 12 performs a sequence of transactions on the ANV bus corresponding to this command.

In accordance with the SpaceWire standard, when switching data packets, the device supports directional, logical and regional-logical addressing. Directional addressing is implemented without using a routing table. Valid path values are "0", "1", "2". Packets with addresses "3" - "31" are interpreted as packets with an invalid address and are erased. Logical and regional-logical addressing are implemented using the routing table registers from block 9 routing registers. The routing table includes 4 rows. For each of the lines, an address is set (the addresses of the lines can go in a row) and the value of the line. The addresses of the lines of the routing table are set in the ADDRESS 1 register of the address space of the routing table. In this implementation, the routing table is implemented on the basis of five registers (Table 4).

The ADDRESS 1 register contains the address values (see Table 5) that correspond to the lines of the routing table located in the registers STR1_1 - STR1_4. It is implemented with read and write access.

After the device exits from the reset state, the value of this register is "'0". In the fields Addr1 - Addr4 can be written any values in the range from "32" to "255". Values can go in any order, values should not be repeated. Four registers of routing lines 1 ... 4 (STR1_1 - STR1_4) contain 32-bit values of routing lines corresponding to the addresses Addr1, ..., Addr4 from the register ADDRESS1.

Four registers of routing lines 1 ... 4 (STR1_1 - STR1_4) contain 32-bit values of routing lines corresponding to the addresses Addr1, ..., Addr4 from the ADDRESS register 1. The format of the routing line for each of the registers STR1_1 - STR1_4 is given in Table. 6. They are implemented with read and write access. After the device exits from the reset state, the value of each of these registers is equal to "0".

Broadcast control is carried out using the network links identification register - ID_NET, located in block 8 of the mode / state registers. This two-digit network link identification register is implemented with read and write access. If a terminal node (data processor) is connected to the i-th port of SpaceWire, then the bit i of this register must be set to "0", if the port of another device or another network node, such as a switch, is connected to this port, then the bit i needs to be set in 1". If "0" is set in the i-bit of this register, then broadcasting is allowed for the corresponding SpaceWire i port. If “1” is set in bit i of this register, then broadcasting is prohibited for the i-th SpaceWire port, i.e. packets addressed to more than one link (group of links) will not be transmitted to this port. After the device exits from the reset state, the value of all bits of this register is "0".

Adaptive group routing control is implemented using adaptive group routing registers (ADG_ROUT) from block 8 mode / state registers. Block 8 contains two adaptive multicast routing registers — one for each SpaceWire port. The adaptive group routing register is read and write. The register is designed to store additional information about alternative links for the corresponding SpaceWire port. The device implements group adaptive routing controlled from the routing table when using this additional information in accordance with the SpaceWire standard. The format of the ADG_ROUT register is shown in the Table. 7.

Each ADG_ROUT register contains a superposition of unitary codes of SpaceWire port numbers, alternative to this port specified in the routing table. Group adaptive routing allows you to route a packet along one of a number of alternative channels connecting adjacent switches and / or terminal nodes. Group adaptive routing helps provide support for sharing link bandwidth and / or fault tolerance on a SpaceWire network. The initial value of all bits of the adaptive group routing register after the device exits the reset state corresponds to the fact that each port forms a separate group.

Arbitration Register - SPEC_ARB is available to the host system for reading and writing. This register stores the parameters for port arbitration in the device. To determine the port with the highest priority, the scheme with dynamic cyclic priorities is used by default. For network configurations in which packets never arrive on some ports (due to the fact that this port is not connected, or due to the specifics of the task being solved), a special priority scheme is used so that such a port never gets the highest priority. This allows you to better balance the scheme of changing priorities. Otherwise, the priority system will be unbalanced in that the port immediately following the port through which packets are not received will be the highest priority almost twice.

The SPEC_ARB register allows you to specify the port numbers that must be skipped in the order of priority changes (ports that will never receive the highest priority). The bits of the SPEC_ARB register correspond to the device ports according to their serial numbers (bit 0 corresponds to the controller 49 of the first SpaceWire port, bit 1 - to the controller 50 of the second SpaceWire port, bit 2 - to the controller 51 of the FIFO port). If the corresponding bit is set to "1", then the port will be skipped. The initial value of all bits of the register after resetting the device is "0".

The RMAP protocol generator 11 is responsible for processing the received RMAP packet and executing the RMAP protocol instructions. Using the commands of the RMAP protocol, the organization of reading / writing to the configuration memory of the device is implemented. The list of RMAP commands and response packets is shown in Table. 8.

By the write command, the data received in the RMAP packet will be written to the address specified in it either in the device configuration area or in the memory area of the external terminal node via the ANV bus. When a read command is issued, the RMAP packet contains the address and the number of bytes to be read either from the device configuration area or from the memory area via the ANV interface.

The response packet to the read command contains the required data. In case of an error when executing commands, the error code is contained in the header of the response packet. There may be no reaction to the received packet, if the shaper 11 did not detect signs in the packet that could identify the packet as an RMAP packet. This situation is possible, for example, when the CRC header does not match the expected value (invalid RMAP header).

The RMAP packet formats performed by the driver 11 are shown in Tables 9-16.

In the table. 17 shows the format of the main fields of the received RMAP packet with which the RMAP driver 11 operates. Packets with the path address "0" or with logical addresses for which the zero bit is set to "1" in the routing registers STR1_I are received in the shaper 11 of the RMAP protocol.

If the type of packet received by the shaper 11 is not defined as RMAP, then the packet is erased. If the packet type is defined as RMAP, but this is not an RMAP command, but an RMAP response, then the packet is erased. RMAP protocol shaper 11 executes RMAP commands coming in SpaceWire packets. The package header is checked for validity; if the package contains a data field, the data field is checked for validity.

Upon receipt of a valid RMAP command packet, if the packet has a logical address "0", then it is interpreted as a call to the device configuration space. If the logical address is other than "0", then the command is converted to one or more transactions on the ANV bus through the ANV Master interface controller 12 to access the memory of the served terminal system node.

If the RMAP command is a read command, then from the data read as a result of the execution of the command, the RMAP protocol generator 11 forms a response packet and sends it to the SpaceWire port 2 (3) through the data packet switching unit 1. If the RMAP command is a confirmation record command, then after completion of the command execution, the shaper 11 also generates a response packet and sends it to the SpaceWire network.

When accessing the memory, the contents of the Write / Read Address field located in the header of the RMAP packet is used as the address of the memory cell. This address when batch transferring a data block to memory (BURST) is incremented by "4" to address the next word. It is possible to execute RMAP commands without an address increment. The packet length in the RMAP command according to the protocol description is specified in bytes, so the number of words transferred to the memory will be approximately 4 times less.

If a packet with a CRC header error arrives at the RMAP controller, it is discarded. If a packet with a correct header, but with an incorrect data field CRC, an incorrect data field length, or ending with the symbol of an erroneous end of an EEP packet arrives in the RMAP controller, then the RMAP protocol generator 11 automatically generates a response packet with an error code.

The recipient logical address (DLA) is the address at which the RMAP driver 11 determines that the packet is addressed to one of its components. Shaper 11 considers that the packet is addressed to him and begins to parse the packet if this DLA field contains the address 0 × 00 (rmap_configuration_addr, RCA) or a non-zero address (rmap_logical_addr, RLA). The RCA address is considered the configuration address at which data is sent to / from the device configuration register area. An RLA address, considered an address for accessing memory when data is routed through the ANV bus interface to / from the memory of an external node. The default RLA address is set to 0 × FE, and can be replaced with a new value by accessing this register in the configuration register area with the RMAP command. If the DLA contains a value other than the addresses mentioned, then the entire packet is discarded.

If the DLA contains a valid address, then the protocol identifier byte is analyzed. If the identifier corresponds to the code of the RMAP protocol, then data is processed in accordance with the selected protocol. If the identifier does not comply with the supported protocol (RMAP), then the entire given SpaceWire packet is discarded. After analyzing the identifier, the driver 11 reads the header of the RMAP packet and checks it for the correctness of the CRC checksum. Each RMAP field is allocated a register of the corresponding bit depth (register area RMAP_REGS). If the header checksum is correct, then the correctness of the data in the header fields is checked for the possibility of executing the RMAP command in the shaper 11 of the RMAP protocol. If all the data is correct, then the contents of the RMAP_REGS registers containing all the information about the RMAP command are used by the shaper 11 to execute the command.

The device supports directional addressing as described in the RMAP protocol (see table 18). Former 11 receives a packet without bytes of the path address; these bytes are deleted by the SpaceWire port 2 (3) controller when the packet is delivered to the packet selector 10. Therefore, the CRC of the header is considered only by the fields of the packet from the DLA byte to the Data Length (LS) byte of both the command and response RMAP packets.

The two-bit “Sender Waypoint Address Lengths” (SPAL) value in the “Package Type” field contains information about the format of the “Sender Waypoint Address” (SPA) field. The two-bit SPAL value is interpreted as follows:

- if SPAL = 00b, then SPA bytes are not in the RMAP response command. This is equivalent to logical addressing when working with RMAP commands. Directional addressing is not used and the driver 11 will begin the response packet by the "Sender Logical Address" (SLA) byte.

- if the value of SPAL is not equal to 00b, then this means the use of directional addressing in the RMAP response command. This also indicates that 4 bytes (SPAL = 01b), 8 bytes (SPAL = 10b) or 12 bytes (SPAL = 11b) were allocated in the RMAP command to place the path address from the shaper 11 to the sender.

Placing a travel address in the SPA fields (if any) is subject to the following requirements. All leading null bytes of the SPA field are ignored by the shaper 11 (they must be present in the RMAP command package). An exception is a SPA containing all bytes with a value of 0 × 00. This is treated as a path address containing 1 byte with a value of 0 × 00. This zero byte will be sent first before transmitting the source logical address in the response packet. All other bytes, starting from the first non-equal 0 × 00, to the last byte in the SPA are treated as the SPA address. They will be transferred to the SpaceWire link before the RMAP response packet in the order of their sequence in the SPA field (see table 19).

Shaper 11 of the RMAP protocol sends a response packet with information about the result of the command if the ACK confirmation bit was set in the command type field in the RMAP command. The response packet is sent after completion of the data transfer to memory or upon detection of an error in the received packet. Error codes returned in the response packet are set in the Status field and are shown in Table. twenty.

Shaper 11 of the RMAP protocol in this device acts as the addressee (receiver) of the RMAP command sent by the remote device - the sender (Fig. 9a, b), having received a request to execute the RMAP command from its external node (for example, the network administrator). Shaper 11 of the RMAP protocol, having received the command and checking it for correctness, sets up a memory request (Request for data recording - Fig. 9a / Request for reading data - Fig. 9b). Having accessed the memory (Authorization of data recording, Response of reading data) from the controller 12 of the ANV Master interface, the shaper 11 writes data to the memory of its external node or transfers data from its memory to the SpaceWire link. After the write transaction is completed, the shaper 11 sends a response packet with information about the successful completion of the RMAP command to the remote device - sender.

The data packets that are received and transmitted by the shaper 11 of the RMAP protocol can be 0 ... 2 ²⁴ -1 in length. Performing preliminary buffering with checking CRC data is possible with the length of the data area of the RMAP packet, not exceeding the number of 28 bytes. If the header indicates a larger value than 28, and the “Check data” bit is set, the packet is discarded, and a response packet with error code 9 will be sent to the sender (in Table 20, the buffer does not contain the declared number of bytes for CRC verification).

Regardless of whether or not preliminary data buffering is performed, the bytes of the received (or transmitted) packet are transferred to the memory by transactions, the size of which can be set in the MAX_TRAN register in block 8 of the mode / state registers. The number written to this register sets the maximum number of 32-bit words that will be transferred in one transaction to memory. Thus, the entire packet of received or transmitted data is transmitted in predetermined portions. The last transaction will contain MAX_TRAN or fewer words.

For some RMAP applications, it may be necessary to write / read data without increasing the address when accessing memory, i.e. working with a data group at a fixed address. The RMAP protocol allows this to be done using the “Increment” bit setting in the “Package Type” field (see tab. 10, 12, 14, 16). Data using the RMAP command can be transmitted to a fixed address, while the shaper 11 can use different data transfer modes, the choice of which can be made in the RMAP settings register:

Access to program-accessible registers of the device’s configuration space can be carried out from a remote SpaceWire network device using RMAP commands for writing and reading strictly 4 bytes of data. Attempting to use write and read commands other than 4 bytes of data to access programmable RMAP registers will return an error with code 10 (see table 20). In the logical address field of these commands should be set to "0". If the network administrator is directly connected to the SpaceWire interface of this (configurable) device, then in this case the length of the path address in RMAP packets addressed to this device should be zero (see Fig. 10a). If the network administrator is connected to the SpaceWire interface of this (configurable) device through one or a chain of switches, then the length of the path address in RMAP packets addressed to this device must be other than "0". When forming the address, directional and regional-logical addressing can be used (see Fig. 10b, c). The address must be configured in such a way that when passing the response RMAP packet from the configurable device to the administrator, this address should be completely separated from the packet. If directional addressing is used, then when passing through each switch, the first byte of the header is separated. If regional-logical addressing is used, then the first byte of the header — logical address “57” (see Fig. 10c) may or may not separate depending on the settings of the switch routing table.

Port 2 (3) SpaceWire changes its operating modes in accordance with the state diagram (see Fig. 6) implemented by the control unit 78. The states of the first and second SpaceWire ports are changed under the operational control of the corresponding status registers - STATUS_1 and STATUS_2, located in block 8 of the mode / status registers. It provides an operational fixation of the operation phases and the current state of port 2 (3) SpaceWire. The following registers correspond to each SpaceWire port.

The STATUS register is accessible to the host system (for example, the network administrator) for reading and writing using RMAP protocol commands. Recording to each separate bit of the register is performed according to the signals from the output 21 (22) of port 2 (3) SpaceWire. The reset of a number of bits of the register can be carried out by the host system by writing "1" to them. The format of the status register is given in table. 21.

The operation mode registers MODE_CR1 and MODE_CR2 (for the first and second SpaceWire ports, respectively) are accessible to the host system for reading and writing. After the device exits the reset state from this register, the value 0 will be read until the network administrator writes some value to it. The format of the register is given in table. 22.

The control unit 78 implements the logic of the state machine that performs the function of an automaton that transitions under the influence of input signals to various states and provides the generation of control signals by which the state machine transfers the data output unit 75, the data reception unit 76, and the data flow control unit 77 status, allowing the correct operation of the SpaceWire port as a whole. The formation of time-outs is necessary for the correct functioning of the state machine when establishing and maintaining a connection with the remote side through the SpaceWire communication channel. From the one shown in FIG. Figure 6 of the approximate implementation of the state machine graph shows the need to implement two timeouts T1 and T2. In accordance with the requirements of the SpaceWire standard, the following timeouts are implemented: T1 = 6.4 μs, T2 = 12.8 μs.

The bit rate coefficient registers TX_SPEED1 and TX_SPEED2 are available to the host system for reading and writing. These registers are designed to set the transmission rate coefficient, which is sent to the speed control block 4 (5), which is responsible for generating the transmission clock by block 6 (7) with the required frequency for the first and second SpaceWire ports, respectively. The register format is shown in table. 23

A ten-bit receive rate coefficient register - RX_SPEED is available to the host system for reading and writing. The value 0 × 3 FF of this register corresponds to the value of 800 Mbps in the SpaceWire link. The value 0 × 00 of this register corresponds to the value 0 Mbit / s in the link. The remaining speed values in the link SpaceWire reflects a direct relationship between the register value and the real speed in the link. The value of the RX_SPEED register is updated every 2048 cycles of the local frequency of the device (100 MHz) in accordance with the estimate of the current reception rate. When the speed changes during this period in 2048 cycles, the register state will correspond to some adjacent speed value between the speed at which data was transmitted in the SpaceWire link and which was switched in the link.

Data timeout register - SWITCH_CONN_TOUTS is available to the host system for reading and writing. This register stores data timeout values. The G_DAT_TOUT field sets the value of the global period for calculating data timeouts. If the value of this field is "0", then the counting mode of all data timeouts is disabled. The counting period is set in microseconds in the main mode (field T_MODE = 1) and in cycles of the local frequency of the device in debug mode. If the main counting mode is used, then in the field MAIN_KOEFF10 of another register SWITCH_CONN_TOUTS2 it is necessary to set the value of the coefficient of the local frequency of the device. The format of the register SWITCH_CONN_TOUTS is shown in Table 24. The initial value of all bits of the register after resetting the device is "0".

The timeout value is set in the L_CONN_TOUT field, after which it is considered that when the connection was established in AutoStart mode, the transition to the specified base speed was successful and data can be transmitted via this channel. This timeout is calculated in the periods specified in the G_DAT_TOUT field.

In the L_SYMB_TOUT field, the value of the timeout period for waiting for a data symbol (waiting for receiving or sending the next packet symbol) is set. This timeout is calculated in the periods specified in the G_DAT_TOUT field. The resolution of the timeout mechanism when receiving a data symbol is carried out by setting the register RIT_SONM_TOUTS2 in the "1" field R_SYMB_F. The resolution of the timeout mechanism when receiving a data symbol is carried out by setting the register TIT_SYMB_F of the register SWITCH_CONN_TOUTS2 to "1".

The timeout register SWITCH_CONN_TOUTS2 is accessible to the host system for reading and writing. The format of the register SWITCH_CONN_TOUTS2 is shown in the table. 25. The initial value of all bits of the register after the device exits the reset state is "0". The field MAIN_KOEFF10 indicates the value of the local frequency coefficient of the device. Local frequency coefficient MAIN_KOEFF10 = LCLK (MHz) / 10. For example, if the local frequency is 100 MHz, then in this field you must specify the value 10.

Timeout flag register - SWITCH_WAIT_FLS is available to the host system for reading and writing. Flags are stored in this register, indicating that timeouts have elapsed waiting for the reception or transmission of data characters. The format of the register SWITCH_WAIT_FLS is shown in the table. 26.

The initial value of all bits of the register after the device exits the reset state is "0". Flags from the reception control units 52 of the controllers of the first and second ports 49 and 52 of SpaceWire are recorded in the REC_FLS field. If the timeout period has elapsed for receiving the next packet symbol, the corresponding bit is set to "1" (bit 0 - from the controller 49 of the first port, bit 1 - from the controller 50 of the second port). Flags from the transmission control units 53 of the controllers of the first and second ports 49 and 52 of SpaceWire are recorded in the TRANS_FLS field. If the timeout period has elapsed for the next packet symbol to be sent, the corresponding bit is set to "1" (bit 2 from the controller 49 of the first port, bit 3 from the controller 50 of the second port). To reset the i bit, you need to write the value "1" in the i bit of this register.

In the data receiving unit 76 of the SpaceWire port 2 (3) in the received bit stream, the SpaceWire decoder recognizes data symbols, control symbols, and codes in accordance with the encoding shown in the table. 1, and informational and channel symbols are distinguished from them, since the symbols transmitted through the SpaceWire link are divided into channel and informational symbols. Information symbols include the data symbol (Nchar) and end-of-packet symbols (EOP, EEP). Channel symbols (FCT, ESC) together with the NULL control code are used to control the status of the SpaceWire communication channel and are not transmitted to the reception control unit 52 of their port 50 (49) SpaceWire. NULL code is designed to preserve the activity of the communication channel and is constantly transmitted if the link is not busy transmitting other characters. The control unit 77 is informed of their reception or termination of reception to influence the machine state. Upon receipt of the FCT symbol, the data receiving unit 76 informs the data flow control unit 77 (which should increase by eight its counter determining the transfer credit). The acceptance of all control symbols (FCTs) is also transmitted to the state machine to the control unit 78 from the output 79 of the acknowledgment of receipt of the flow control symbol. To control the lending mechanism, a data reception permission signal is also used at the output 31 of the data receiving unit 76, which informs the data flow control unit 77 of the presence of eight free cells in the buffer space of the data receiving unit 76.

The data receiving unit 76 may be in one of the following states:

- Reset. The data receiving unit 76 does nothing.

- Launch. The data receiving unit 76 is started and is awaiting receipt of the first bit.

- Received a bit. The data receiving unit 76 received the first bit. The disconnect detection mechanism is enabled. Block 76 receive data can only accept NULL codes.

- Received NULL code. The data receiving unit 76 received a NULL code and can receive a NULL code, FCT symbols, and information symbols. A mechanism for detecting disconnect and coding errors (including parity and extension errors) is included.

The received Nchar information symbols are buffered in the data receiving unit 76 (see FIG. 5), from which through the first 27 (second 29) input-output are read into the data packet switching unit 1 under the control of the receiving control unit 52 of the corresponding SpaceWire port controller 49 (50) . The data output from the buffer of the data receiving unit 76 from the output 96 is ensured according to the “first received, first read” principle, accompanied by a data ready signal at the data ready output 97 for receiving and if there is a read signal at the data reading input 95 of the data receiving unit 76. At the same time, byte reading of received data packets is ensured, separated by control characters of the end of the packet.

The SpaceWire encoder in the data output unit 75, in accordance with the DSW encoding rules of the SpaceWire standard, generates the gating signals S accompanying the data signals D. The bit streams of the data signals D along line 90 and the gating signals S along line 91 are transmitted to the communication channel (see FIG. 3) is carried out by the data output unit 75 at any speed specified by the synchronization frequency of the data output at the input 87 of port 2 (3) SpaceWire.

The data output unit 75 receives data packets from the transmission control unit 53 of its SpaceWire port controller 49 (50) in the form of a sequence of 8-bit data ending with a sign of the end of the packet. Each data byte is accompanied by a zero control flag in accordance with table. 2. Eight data bits before being output are packed in the data output unit 75 into a separate 10-bit Nchar data symbol. A single control flag serves as a sign of the end of the packet and means the need to issue the symbol of the end of the packet (EOR). When the data output unit 75 is ready to transmit another information symbol, it sets the ready signal to the output unit 53 at the output 92 (see FIG. 3). According to the set ready signal, block 53 sets eight data bits together with a control flag at data input 94 for output and generates a write signal to input 93 of the device system interface. The data output unit 75, having received the information symbol, removes its ready signal at the output 92. If there are no information symbols or FCT symbols for transmission, the data output unit 75 sends NULL codes to the channel. The data output unit 75 (side A) transmits information symbols only if there is free space on the side B in the buffer of the data receiving unit 76. The availability of free space is determined by sending, on the B side, the flow control FCT symbol, indicating that there is a space for eight information symbols in the buffer 52 of its data receiving unit 2.

The data output unit 75 on the A side is also responsible for sending FCT symbols when the buffer in the data receiving unit 76 is free to receive eight information symbols. At the same time, the data reception unit 76 (side A) generates a data reception permission signal at the output 105 only when there is a place for eight information symbols in its receive buffer (not reserved for reception by the previously transmitted FCT symbols). Then, the data flow control unit 77 generates a request for sending the FCT symbol at the output 81. The data output unit 75 can transmit FCT symbols only if it is in the Connection state (Transmit FCTs / NULLs) or the Operating mode (Transmit FCTs / Nchars / NULLs).

The data output unit 75 may be in one of four states (see Fig. 6):

- Reset. The data output unit 75 does nothing.

- Transmission of NULL codes. The data output unit 75 sends only NULL codes. It is not ready to transmit information symbols and does not transmit FCT symbols.

- Transmission of FCT characters / NULL codes. The data output unit 75 sends FCT symbols or NULL codes and is not ready to transmit information symbols.

- Transmission of FCT characters / Nchars / NULL codes. Normal operation of the data output unit 75. It sends FCT characters, NULL codes, and information characters (Nchars).

After a reset or an error in the channel, the device is in the “Reset” state, while the data and gating signals are set to “0”. After the transition to the Start state, the data output unit 75 starts transmitting NULL codes. When issuing the first NULL code, the character control bit must first be transmitted. The value of this bit shall be zero. Therefore, the state of the signal at the gate output 91 of the data output unit 75 will first change.

If the issued information symbol contains a control flag equal to one, then this means a sign of the end of the packet. The end of packet sign indicates that the previous byte of data issued was the last in the packet. In this case, the data output unit 75 generates and issues the EOR control symbol code to the channel.

By default, during initialization, the device is set to automatically establish a connection at a speed of 10 Mbit / s. The connection will be automatically established when automatic connection is enabled in a second, remote device. To configure the connection, the device uses the MODE_CR1 and MODE_CR2 registers (see Table 22) located in the block 8 of the mode / state registers at the addresses 0 × 448 and 0 × 44C for the first (2) and second (3) SpaceWire ports, respectively. Setting the LinkDisabled bit of the MODE_CR register to zero prevents the connection from being established. Setting the seventh bit of AUTO_SPEED of register MODE_CR to "1" enables automatic connection setup. When the first AutoStart bit is set in the MODE_CR register, the device will be in the Ready state until a NULL code is received via the SpaceWire link from the second device. When the second LinkStart bit is set in the MODE_CR register, the device will go into the “Start” state and start sending NULL codes to the link. The default values for these bits are AutoStart = 0, LinkStart = 1. To establish a connection, one of the devices must be in LinkStart state, and the other in AutoStart or LinkStart. The connection is established at a speed of 10 Mbit / s, then there is a transition to the basic transmission rate.

To configure the transmission speed, two TX_SPEED1 and TX_SPEED2 registers are used in the device (see Table 23), located in block 8 mode / state registers at 0 × 450 and 0 × 454 addresses for the first (2) and second (3) SpaceWire ports, respectively . The connection is established at a speed of 10 Mbit / s, then there is a transition to the basic transmission rate. The value of the transmission rate coefficient is set in the register TX_SPEED in bits 0..7 (TX_SPEED.SEL). The value of the coefficient of the transmission speed necessary to configure the desired speed depends on the used PLL circuit in block 6 (7) of the formation of the transmission clock signals.

Thus, the introduction of the second SpaceWire port into this device makes it possible for several system applications of such a two-port SpaceWire communication interface device. When designing network structures, the presence of two SpaceWire ports in the device allows achieving two goals at the lowest cost: either improving the reliability of data transmission channels, or increasing throughput when transmitting large data streams from high-speed sensors, or both. In FIG. 11a shows a simple example of a structure where SpaceWire links connect two device ports directly to a data processor (for example, ELVIIS MULTIFORCE MC24RT) that has integrated SpaceWire ports. In the terminal node, which acts as the sensor controller, the data generated by the sensor is accumulated in the memory of the terminal node. At the request of the processor, data is read from the memory of the terminal node via the ANV bus interface to the device, from which they are transferred to the data processor in the form of RMAP packets via SpaceWire links. In FIG. Figure 11b shows an example of a structure in which a SpaceWire network based on switches and hubs provides both reliable connection of a group of devices to a data processor and a high total throughput for transmitting packets with data from high-speed sensors through SpaceWire links. The most effective features of the device are used in the formation of cascade structures. In FIG. 12 shows a group of devices forming a chain (daisy-chain), in which two SpaceWire ports of each device are connected to neighboring devices in the chain. The extreme devices in the chain can connect to the switch ports, or directly to the data processor.

Taking into account the fact that a controller with a control unit based on strict logic is enough to control the sensor’s operation, the use of the SpaceWire dual-port communication device in this case is an effective option that is justified both from a technical and economic point of view, and for on-board systems is the most appropriate.

The technical result of this solution is to expand the scope of the SpaceWire communication interface device due to the expansion of the device’s functionality: it is possible to build various network configurations by connecting the SpaceWire communication interface devices with two ports in series. At the same time, the ability to implement data transfer from an arbitrary set of sensors to one SpaceWire port of the data processor is achieved, fully using its bandwidth to load the data acquisition and processing system as fully as possible.

The proposed device has significant functional advantages over known analogues.

Claims (2)

1. SpaceWire communication interface device for use in a communication system that combines at least one computer or data processor with one or more terminal nodes by connecting devices in series through the SpaceWire communication interface, moreover, in the SpaceWire communication interface device containing the SpaceWire port, which includes a data output unit, a data reception unit, a control unit and a data flow control unit, the output of a request for issuing a flow control symbol of which connected to the input of the data output unit of the same name, the output of which the flow control symbol is ready to be connected to the input of the data flow control unit of the same name, the acknowledgment inputs of the flow control symbol and the acknowledgment of the information symbol of which are connected respectively to the inputs of the control unit and the outputs of the data reception unit of the same name, the output of the character encoding error which is the output of the character encoding error of the port system interface and is connected to the input of the same name ohm of the control unit, the first and second reset outputs of which are connected to the reset inputs of the data output unit and the data receiving unit, the data and gating inputs of which are inputs of the SpaceWire port receive channel, the SpaceWire port output channel are data and gate outputs the input of the synchronization of the data output of which is the input of the synchronization of data output of the system interface of the port, the input of reading the data of the system interface of the port receiver a variable input of the data receiving unit, data outputs for receiving and data readiness for receiving which are the corresponding outputs of the port receiver system interface, the credit error of the port system interface is the output of the data flow control unit of the same name and connected to the control unit input of the same name, the third reset output of which is connected with the reset input of the data flow control unit, the inputs for confirming the issuance of an information symbol and the permission for receiving data of which are connected with the same name the outputs of the data issuing unit and the data receiving unit, the port system interface reset input is the control unit reset input, the port transmitter system interface readiness output output is the same output as the data output unit, the recording and data inputs for issuing the port system interface are the corresponding inputs of the unit data output, the input of the local synchronization of the port is connected to the inputs of the local synchronization of the control unit, data flow control unit, data reception unit , of a data output unit, the flow control symbol enable signal input of which is connected to the control unit output of the same name, the data reception unit disconnection error output is connected to the control unit input of the same name and is the port system interface disconnect error output, the connection system port interface connection establishment output is the connection establishment output data receiving unit and is connected to the control unit input of the same name, characterized in that a second SpaceWire port, a switching unit, is inserted into it data packets, two transmission rate control blocks, two transmission clock generation blocks, a mode / status register block, a routing register block, a packet selector, an RMAP protocol shaper, an ANV Master interface controller and an ANV Slave interface controller, and the system interface outputs of each of the two ports SpaceWire are connected respectively to the status input groups of the same name port of the mode / status register block, and are also connected respectively to the inputs of the presence of synchronization of speed control units передачи transmissions, whose change rate outputs are connected respectively to the inputs of the transmit clock generation blocks, whose outputs are connected to the data output synchronization inputs of each of the two SpaceWire ports, in each of which the status control inputs of the control unit are the inputs of the same name of each of the two SpaceWire ports and are connected respectively with the first and second outputs of the state control unit of the registers of the mode / state, the first and second inputs and outputs of the state of which are connected respectively to the inputs- the status outputs of each of the speed control units, the third status input / output unit of the mode / status register block is connected to the status input / output of the data packet switching unit, the first and second transmission inputs and outputs of which are connected respectively to the same input-outputs of each SpaceWire port, the inputs are the receiving outputs of which are connected respectively to the first and second input-output ports of a data packet switching unit, the addressing input-output of which is connected to the input-output of the routing register block of the same name II, the information input-output of which is connected to the first control input-output of the ANV Slave interface controller, the second control input-output of which is connected to the information input-output of the mode / state register block, the fourth state input-output of which is connected to the conditioner input-output of the conditioner RMAP protocol, the first and second information inputs / outputs of which are connected respectively to the first information input / output of the ANV Master interface controller and to the input / output of packet selector data, input-output the packet data of which is connected to the input-output block of the data packet switching unit, the inputs and outputs of the ANV device bus interface are the inputs and outputs of the ANV Master interface controller of the same name, the second information input-output of which is connected to the information input-output of the ANV Slave interface controller, the reset input which is connected to the reset inputs of the ANA Slave interface controller, RMAP protocol shaper, packet selector, routing register block, mode / state register block, two control units The transmission speed and with the reset inputs of each of the two SpaceWire ports is the input of the initial installation of the device, the local synchronization input of which is connected to the local synchronization inputs of each of the two SpaceWire ports and to the synchronization inputs of two transmission speed control units, a block of mode / state registers, and a block routing registers, packet selector, RMAP protocol shaper, ANV Master interface controller and ANV Slave interface controller. 2. The device according to claim 1, characterized in that the data packet switching unit comprises an adaptive switching unit, a broadcasting unit, a switching matrix, two SpaceWire port controllers, each of which consists of SpaceWire port receiving and transmitting control units, and a FIFO port controller, consisting of reception and transmission control units, the reset and local synchronization inputs of the packet switching unit being connected respectively to the inputs of the adaptive routing unit, broadcasting unit, reception control units, etc. FIFO port controller and each of the two SpaceWire port controllers, the first inputs and outputs of the control units for the controllers of the first and second SpaceWire ports are the first and second input and output of the receive packet data switching unit, the first inputs and outputs of the control units for transmitting the first and second controllers SpaceWire ports are respectively the first and second input-output of the data packet switching unit, the second inputs and outputs of the control units for receiving controllers of the first and second SpaceWire ports and FIFO ports are connected respectively to the first, second and third inputs / outputs of the switching matrix, the second inputs and outputs of the transmission control units of the controllers of the first and second SpaceWire ports and FIFO ports are connected respectively to the first, second and third inputs and outputs of the switching matrix, the first inputs - the outputs of the control units for receiving and transmitting the FIFO port controller are connected to the input-output of packet data of the data packet switching unit, the inputs and outputs of the address information of the reception and transmission control units The first controllers of the first and second SpaceWire ports, control units for receiving and transmitting the FIFO port controller, adaptive routing and broadcasting units are connected to the I / O addressing of the data packet switching unit, the status input / output of which is connected to the I / O of the control unit for receiving and transmitting the controller FIFO ports, reception and transmission control units for controllers of the first and second SpaceWire ports, adaptive routing and broadcasting blocks, request outputs of reception reception control units the ditch of the first and second SpaceWire ports are connected to the corresponding bits of the request bus, which are connected respectively to the request inputs of the transmission control units of the controllers of the first and second SpaceWire ports, the confirmation outputs of the transmission control units of the controllers of the first and second SpaceWire ports are connected to the corresponding bits of the confirmation bus, which are connected respectively with acknowledgment inputs of control units for the controllers of the first and second SpaceWire ports, the selection inputs and outputs of which are connected to responsibly, with the first and second inputs and outputs of the adaptive routing unit selection, the third input-output of which is connected to the input-output of the selection of the control unit for receiving the FIFO port controller, the control inputs and outputs of the control units for receiving controllers of the first and second SpaceWire ports which are connected respectively to the first and the second inputs and outputs of the regulation of the broadcasting unit, the third and fourth outputs of the regulation of which are connected respectively to the control inputs of the transmission control units to the controllers of the first and second SpaceWire ports, the fifth input-output of the broadcast control unit is connected to the input-output of the control unit of the reception control unit of the FIFO port controller, the sixth output of the control of the broadcast unit is connected to the control input of the transmission control unit of the FIFO port controller.

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