CN111224877A - VL query method and device of AFDX switch - Google Patents
VL query method and device of AFDX switch Download PDFInfo
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- CN111224877A CN111224877A CN201911255035.9A CN201911255035A CN111224877A CN 111224877 A CN111224877 A CN 111224877A CN 201911255035 A CN201911255035 A CN 201911255035A CN 111224877 A CN111224877 A CN 111224877A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
- H04L45/74591—Address table lookup; Address filtering using content-addressable memories [CAM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/70—Virtual switches
Abstract
The invention provides a VL query method and a VL query device of an AFDX (avionics full Duplex switched Ethernet) switch, which are used for VL matching query of the AFDX switch and comprise the following steps: the CAM table dual-port RAM module and the round-robin control module support N dual-port RAM units with the depth of M. The CAM table dual-port RAM module stores at least 4096 pieces of configuration information, the configuration information comprises an effective link number, one piece of configuration information occupies the depth of one dual-port RAM unit, and the dual-port RAM unit provides the configuration information stored in different depths in each clock cycle in a round-robin mode. And the round-robin control module is used for sending a read control enabling signal and round-robin position information to the CAM table dual-port RAM module and carrying out round-robin output on the effective link number stored in the dual-port RAM unit. The VL query method and the VL query device of the AFDX switch have higher flexibility, meet the query that a single port supports 4096 VLs to the maximum extent, and better adapt to the routing requirements under various situations.
Description
Technical Field
The invention belongs to the technical field of airborne networks, and relates to a VL query method and a VL query device of an AFDX switch.
Background
AFDX switched network technology has been gradually applied to onboard systems as a deterministic communication technology, and as a statically configured network routing technology, its switching function is specified to meet the basic requirements of 4096 Virtual Link (VL) routing information.
In the prior art, to ensure the frame switching performance of each port, each port is usually adopted to support 256 VL routes, and the number of VL routes supported by all ports meets 4096 requirements.
However, there is a demand for an increase in port configuration VLs, and as VL routes supported by each port increase, frame switching performance per port decreases.
Disclosure of Invention
The technical problem solved by the invention is as follows: the realization method can support 4096 VL matching information of the single exchange port, can also give out a matching result quickly, meets the exchange function requirement of ARINC 664P7 protocol, and is well suitable for the routing requirement under various conditions.
The technical scheme of the invention is as follows:
the invention provides a VL inquiry method of an AFDX (avionics full Duplex switched Ethernet) switch, which is used for a VL inquiry device of the AFDX switch, and the VL inquiry device comprises a CAM (computer memory access) table dual-port RAM module, wherein the CAM table dual-port RAM module comprises N dual-port RAM units with the depth of M, at least 4096 pieces of configuration information are stored in the RAM module, the configuration information comprises an effective link number, one piece of configuration information occupies the depth of one dual-port RAM unit, the dual-port RAM units provide the configuration information stored in different depths in each clock period in a round-robin mode, and N and M are positive integers; the method comprises the following steps:
acquiring a virtual link number;
making the value of the counter count be 0, and adding 1 to the value of the counter count in each clock cycle;
when the received virtual link number enabling information is valid, comparing the virtual link number with N valid link numbers provided by the N double-port RAM units in the current clock cycle, and when no valid link number is consistent with the virtual link number, comparing the virtual link number with the N valid link numbers provided by the N double-port RAM units in the next clock cycle until the value of count reaches M' -1 or the valid link number is consistent with the virtual link number;
when the value of the count does not reach M' and an effective link number is consistent with the virtual link number, outputting the address of the effective link number consistent with the virtual link number;
wherein M 'is the number of configuration information stored in the dual-port RAM unit which stores the most configuration information, and M' is a positive integer smaller than M; the method comprises the steps that the received virtual link number enabling information is effective between a first time and a second time, the first time is the time when the virtual link number is analyzed from the AFDX frame, and the second time is the frame ending time of the AFDX frame.
Optionally, the configuration information further includes link number enabling information; before determining that the valid link number is consistent with the virtual link number, the method further comprises:
determining that the link number enabling information indicates that the valid link number is valid.
Optionally, the method further includes:
and when the value of the count reaches M', outputting matching failure information, wherein the matching failure information is used for indicating that the virtual link number to which the matching failure information belongs is invalid.
Optionally, the apparatus further comprises a round-robin control module;
the round-robin control module is used for sending a read control enabling signal and round-robin position information to the dual-port RAM unit, wherein the read control enabling signal is used for indicating the dual-port RAM unit to carry out round-robin output on the effective link number stored in the dual-port RAM unit from the round-robin position in the dual-port RAM unit.
One aspect of the present invention provides a VL query apparatus for an AFDX switch, including: a CAM table double-port RAM module and a VL inquiry module; wherein the content of the first and second substances,
the CAM table dual-port RAM module comprises N dual-port RAM units with the depth of M, at least 4096 pieces of configuration information are stored in the CAM table dual-port RAM module, the configuration information comprises an effective link number, one piece of configuration information occupies the depth of one dual-port RAM unit, the dual-port RAM unit provides the configuration information stored in different depths in each clock period in a round-robin mode, and N and M are positive integers;
the VL query module is used for acquiring a virtual link number; making the value of the counter count be 0, and adding 1 to the value of the counter count in each clock cycle;
when the received virtual link number enabling information is valid, comparing the virtual link number with N valid link numbers provided by the N double-port RAM units in the current clock cycle, and when no valid link number is consistent with the virtual link number, comparing the virtual link number with the N valid link numbers provided by the N double-port RAM units in the next clock cycle until the value of count reaches M' -1 or the valid link number is consistent with the virtual link number;
when the value of the count does not reach M' and an effective link number is consistent with the virtual link number, outputting the address of the effective link number consistent with the virtual link number;
wherein M 'is the number of configuration information stored in the dual-port RAM unit which stores the most configuration information, and M' is a positive integer smaller than M; the method comprises the steps that the received virtual link number enabling information is effective between a first time and a second time, the first time is the time when the virtual link number is analyzed from the AFDX frame, and the second time is the frame ending time of the AFDX frame.
Optionally, the configuration information further includes link number enabling information; and the VL inquiry module is further used for determining that the link number enabling information indicates that the effective link number is effective before determining that the effective link number is consistent with the virtual link number.
Optionally, the VL query module is further configured to, when the value of the count reaches M', output matching failure information, where the matching failure information is used to indicate that the virtual link number to which the matching failure information belongs is invalid.
Optionally, the apparatus further comprises a round-robin control module;
the round-robin control module is used for sending a read control enabling signal and round-robin position information to the dual-port RAM unit, wherein the read control enabling signal is used for indicating the dual-port RAM unit to carry out round-robin output on the effective link number stored in the dual-port RAM unit from the round-robin position in the dual-port RAM unit.
The invention has the beneficial effects that: the switching function in the ARINC 664P7 protocol at least supports 4096 VL configurations, supports single-switching port to quickly inquire 4096 VL matching information, and is excellently suitable for routing requirements in various situations.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a VL query method and apparatus for an AFDX switch according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a VL query module according to an embodiment of the present invention.
Detailed Description
The technical solution is further explained in detail with reference to the drawings.
The invention provides a VL query method and a VL query device of an AFDX switch, wherein the VL query device comprises the following steps: the system comprises a CPU address decoding and reading-writing module, a CAM table double-port RAM module, a polling control module, a VL inquiry module and an MAC IP core.
Fig. 1 is a schematic diagram of a VL query method and apparatus of an AFDX switch according to an embodiment of the present invention, and fig. 2 is a schematic diagram of a VL query module according to an embodiment of the present invention, and a CPU address decoding and reading/writing module, a CAM table dual-port RAM module, a polling control module, a VL query module, and the like are explained below with reference to fig. 1; a detailed description is given of the VL query module in conjunction with fig. 2.
Taking the 24-port AFDX switch as an example, the switch comprises: a CAM table dual port RAM module of 16 dual port RAM cells of 256 depths.
The working mechanisms of the CPU address decoding and reading/writing module, the CAM table dual-port RAM module, the polling control module, the VL query module, the MAC IP core, and the like will be further described with reference to fig. 1.
Firstly, it is stated that the ARINC 664P7 protocol specifies that the AFDX network adopts 10/100Mbps rate, and in the existing MAC IP core, the receiving port frequency is 25MHz, and the data width is 8bit, that is, the rate requirement of maximum 100Mbps is satisfied. In this design, the VL query method and apparatus employs a 125MHz clock frequency.
The CPU address decoding and read-write control module has the functions as follows: in the initialization stage of the switch, respectively writing configuration information (including enable bit and VLID information) into a CAM table dual-port RAM module; specifically, the configuration information content corresponding to each address in the dual-port RAM unit includes: enable bit 1bit and VLID information 16 bit.
The polling control module has the main functions of: after the switch finishes initialization, a first command and a current address are sent to the CAM table dual-port RAM module, and all units can output all contents in the RAM units to all ports in a round-robin manner from the current address after receiving the first command; meanwhile, the polling control module also outputs the current address to the VL inquiry module.
VL inquiry module, main function is: comparing the output content of the current CAM table dual-port RAM module with the VLID submitted by the MAC IP core, and outputting the successfully matched address for the application of the subsequent function;
the MAC IP core has the main functions of: receiving and analyzing an AFDX frame input by the port, and submitting VLID information to a VL query module in time for VL matching query;
the VL query module in the port is further described with reference to fig. 2.
The port mainly comprises: VL query module and MAC IP core. Each AFDX switch port includes a VL query module and a MAC IP core, and the interface relationship thereof is as shown in fig. 2: the VL inquiry module receives a rev _ vlid signal (a virtual link number of an AFDX frame is received) and a rev _ vlid _ en (a current virtual link number valid signal) signal from the MAC IP core; an address signal cam _ addr (current address) from the polling control module; data signals RAM _ x _ data from a plurality of CAM table dual port RAM cells (x is more than or equal to 0 and less than or equal to N); the match success signal cam _ match and the match address signal cam _ match _ addr are output. In addition, due to the uncertainty of the arrival timing at each port of the received frame, the VL inquiry module will maintain a counter count, which is incremented by 1 starting from 0 when rev _ vlid _ en arrives. Wherein the VL query module comprises: VL matching and contrast control. A VL matching function for matching with N ram _ x _ data simultaneously; and the contrast control function is used for performing the function control on the VL matching according to rev _ vlid _ en and the counter count.
With the above information, the work flow of the VL query module is as follows:
the method comprises the following steps: waiting for rev _ vlid _ en to be valid (an AFDX switch port sends AFDX frame data to an MAC IP core, when the MAC IP core receives the valid frame data, a rev _ vlid _ en signal and a rev _ vlid signal are screened out from the valid frame data, and the rev _ vlid _ en is used for indicating whether the rev _ vlid signal is valid or not), if so, entering the second step, and if not, waiting;
step two: acquiring rev _ vlid, starting matching with ram _ x _ data, and entering a fifth step if a certain ram _ x _ data is successfully matched with the currently received rev _ vlid; otherwise, entering a step three;
wherein, once the enable bit rev _ vlid _ en is invalid, go to step five;
step three: adding 1 to the count of the matching counter, judging whether the current count returns to 0 again, if so, entering a fifth step, and otherwise, entering a second step;
step four: if the matching fails, keeping the output cam _ match to be 0;
step five: and successfully matching, acquiring an address signal cam _ addr of current polling control, calculating a matching address cam _ match _ addr according to the double-port RAM unit matched with the current VLID, and outputting a cam _ match value of 1.
The invention has the beneficial effects that: the switching function in the ARINC 664P7 protocol at least supports 4096 VL configurations, supports single-switching port to quickly inquire 4096 VL matching information, and is excellently suitable for routing requirements in various situations.
Claims (8)
1. A VL inquiry method of an AFDX switch is characterized in that the VL inquiry device is used for the AFDX switch and comprises a CAM table dual-port RAM module, the CAM table dual-port RAM module comprises N dual-port RAM units with the depth of M, at least 4096 pieces of configuration information are stored in the RAM module, the configuration information comprises an effective link number, one piece of configuration information occupies the depth of one dual-port RAM unit, the dual-port RAM unit provides the configuration information stored in different depths in each clock cycle in a round-robin mode, and N and M are positive integers; the method comprises the following steps:
acquiring a virtual link number;
making the value of the counter count be 0, and adding 1 to the value of the counter count in each clock cycle;
when the received virtual link number enabling information is valid, comparing the virtual link number with N valid link numbers provided by the N double-port RAM units in the current clock cycle, and when no valid link number is consistent with the virtual link number, comparing the virtual link number with the N valid link numbers provided by the N double-port RAM units in the next clock cycle until the value of count reaches M' -1 or the valid link number is consistent with the virtual link number;
when the value of the count does not reach M' and an effective link number is consistent with the virtual link number, outputting the address of the effective link number consistent with the virtual link number;
wherein M 'is the number of configuration information stored in the dual-port RAM unit which stores the most configuration information, and M' is a positive integer smaller than M; the method comprises the steps that the received virtual link number enabling information is effective between a first time and a second time, the first time is the time when the virtual link number is analyzed from the AFDX frame, and the second time is the frame ending time of the AFDX frame.
2. The method of claim 1, wherein the configuration information further comprises link number enabling information; before determining that the valid link number is consistent with the virtual link number, the method further comprises:
determining that the link number enabling information indicates that the valid link number is valid.
3. The method of claim 1, further comprising:
and when the value of the count reaches M', outputting matching failure information, wherein the matching failure information is used for indicating that the virtual link number to which the matching failure information belongs is invalid.
4. The method of claim 1, wherein the device further comprises a round-robin control module;
the round-robin control module is used for sending a read control enabling signal and round-robin position information to the dual-port RAM unit, wherein the read control enabling signal is used for indicating the dual-port RAM unit to carry out round-robin output on the effective link number stored in the dual-port RAM unit from the round-robin position in the dual-port RAM unit.
5. A VL inquiry apparatus of an AFDX switch, comprising: a CAM table double-port RAM module and a VL inquiry module; wherein the content of the first and second substances,
the CAM table dual-port RAM module comprises N dual-port RAM units with the depth of M, at least 4096 pieces of configuration information are stored in the CAM table dual-port RAM module, the configuration information comprises an effective link number, one piece of configuration information occupies the depth of one dual-port RAM unit, the dual-port RAM unit provides the configuration information stored in different depths in each clock period in a round-robin mode, and N and M are positive integers;
the VL query module is used for acquiring a virtual link number; making the value of the counter count be 0, and adding 1 to the value of the counter count in each clock cycle;
when the received virtual link number enabling information is valid, comparing the virtual link number with N valid link numbers provided by the N double-port RAM units in the current clock cycle, and when no valid link number is consistent with the virtual link number, comparing the virtual link number with the N valid link numbers provided by the N double-port RAM units in the next clock cycle until the value of count reaches M' -1 or the valid link number is consistent with the virtual link number;
when the value of the count does not reach M' and an effective link number is consistent with the virtual link number, outputting the address of the effective link number consistent with the virtual link number;
wherein M 'is the number of configuration information stored in the dual-port RAM unit which stores the most configuration information, and M' is a positive integer smaller than M; the method comprises the steps that the received virtual link number enabling information is effective between a first time and a second time, the first time is the time when the virtual link number is analyzed from the AFDX frame, and the second time is the frame ending time of the AFDX frame.
6. The apparatus of claim 5, wherein the configuration information further comprises link number enabling information; and the VL inquiry module is further used for determining that the link number enabling information indicates that the effective link number is effective before determining that the effective link number is consistent with the virtual link number.
7. The apparatus according to claim 5, wherein the VL query module is further configured to, when the value of count reaches M', output matching failure information, where the matching failure information is used to indicate that the affiliated virtual link number is invalid.
8. The apparatus of claim 5, further comprising a round-robin control module;
the round-robin control module is used for sending a read control enabling signal and round-robin position information to the dual-port RAM unit, wherein the read control enabling signal is used for indicating the dual-port RAM unit to carry out round-robin output on the effective link number stored in the dual-port RAM unit from the round-robin position in the dual-port RAM unit.
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