CN101001199A

CN101001199A - Data processing method of high speed multidigit parallel data bus

Info

Publication number: CN101001199A
Application number: CNA200610011164XA
Authority: CN
Inventors: 王志忠; 刘衡祁; 陈颖
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2006-01-11
Filing date: 2006-01-11
Publication date: 2007-07-18

Abstract

This invention discloses a data process method for high speed multi-bit parallel data buses, which divides a multi-bit parallel data bus into multiple clock domain transmissions in the same frequency and phase with the reference clock at the transmission end, the receiving end utilizes the FIFO queue of the read clock and write clock in the same frequency and phase with the reference clock as the buffer storage to recover the multi-bit parallel data bus, the data lines in the clock domains are equal to the clock lines.

Description

A kind of data processing method of high speed multidigit parallel data bus line

Technical field

The present invention relates to data communication system, particularly a kind of method of handling the high speed multidigit parallel data bus line is effectively finished the processing of bus frequency up to the multi-bit parallel data of hundreds of megahertzes.

Background technology

Data communication system develops to high-speed broadband day by day, bandwidth is that 10,000,000,000 and tens thousand of million communication system is non-rare, be in 10,000,000,000 routers of network core position or processing and the exchange that switch is responsible for data, network processing unit carries out the classification of packet or cell, processing such as route and traffic management, switching network carries out the clog-free exchange of data, communication means between network processing unit and the switching network can have several modes, a kind of is differential lines at a high speed, but this mode needs to increase in addition string and converting unit, need encode to data, and a clock and data recovery procedure will be arranged, system complexity is higher, realizes difficult.Another kind method is directly to adopt the data/address bus of multi-bit parallel to carry out the transmission of data, and the transmission speed of data/address bus can reach hundreds of megahertzes.But transmission and reception how to finish data reliably on printed wiring board (PCB) become a problem.In the data/address bus of parallel transmission,, require each data wire consistent, to satisfy the consistency of phase place with the track lengths of clock on PCB in order to guarantee well to sample to data at receiver side.But the parallel data bit wide surpasses 32 or more the time, is difficult to accomplish longer transmission such as every data lines on the circuit board.

Summary of the invention

The object of the present invention is to provide a kind of data processing method of high speed multidigit parallel data bus line, solve the multi-bit parallel data/address bus and the problem of longer transmission such as on PCB, can't realize, and then solved in the broadband system problem of data communication between the data processing unit, improve reliability of data transmission.

To achieve these goals, the invention provides a kind of data processing method of high speed multidigit parallel data bus line, at transmitting terminal the multi-bit parallel data/address bus is divided into clock zone transmission a plurality of and reference clock frequency homophase together, the receiving terminal utilization is read clock and is write clock and all reduce described multi-bit parallel data/address bus with the fifo queue of the same frequency of reference clock homophase as buffer memory, and the data wire and the clock line of each clock zone inside are isometric.

The data processing method of above-mentioned high speed multidigit parallel data bus line specifically comprises the steps:

The multi-bit parallel data/address bus is divided into the steps of many groups, and each set of dispense one clock and of deriving is used for the frame delimiter of the original position of definition of data frame, and the data wire and the clock line of packets inner are isometric;

The step of grouped data and corresponding frame delimiter being got at the rising edge of tranmitting data register or trailing edge;

Grouped data is after data wire and clock line transmission, the described clock of deriving that receiving terminal one fifo queue utilizes described grouped data correspondence writes described grouped data as writing clock, and judges according to described frame delimiter and to utilize receive clock as reading the clock dateout after receiving all described grouped datas;

The described clock of deriving, tranmitting data register and receive clock and reference clock are with the frequency homophase.

The data processing method of above-mentioned high speed multidigit parallel data bus line, wherein, the described clock of deriving, tranmitting data register and receive clock are produced according to reference clock by the zero-lag clock driver.

The data processing method of above-mentioned high speed multidigit parallel data bus line, wherein, receiving terminal begins the grouped data of correspondence is write described fifo queue after receiving described frame delimiter.

The data processing method of above-mentioned high speed multidigit parallel data bus line, wherein, first active data signal alignment of described frame delimiter and corresponding grouped data.

Compare with prior art, the present invention directly utilizes parallel bus to carry out the transmission of wideband data, after packet, utilizes FIFO to reduce at receiving terminal, has improved reliability of data transmission.

Description of drawings

Fig. 1 is the schematic diagram of deriving of clock;

Fig. 2 is a packet schematic diagram of the present invention;

Fig. 3 is the phase relation schematic diagram of clock of the present invention and data;

Fig. 4 is the handling process schematic diagram of receiving terminal FIFO among the present invention.

Embodiment

The data processing method of high speed multidigit parallel data bus line of the present invention comprises the steps:

The data/address bus partiting step, data/address bus is divided into several clock zones, the part of each clock zone transmission multi-bit parallel data/address bus, guarantee longer transmission such as the data wire of each clock zone inside and clock line simultaneously, guarantee the consistency on the phase place, so just can be in the correct sampled data of receiving terminal, the bit wide of tentation data bus is the M position in the present invention, and it is divided into the N group;

The clock partiting step, at transmitting terminal, reference clock produces N with the synchronous clock of frequency through the zero-lag clock driver, is divided into N different clock zone, is used for the data in the synchronous described grouping;

Datum plane definition step, N after the above-mentioned division different clock zone is defined as datum plane, comprising clock signal, data-signal and a frame delimitation signal SOF who is used to Frame to delimit, this frame delimitation signal has been indicated the beginning of data, and the SOF in each grouping comes into force simultaneously;

The reduction of data step, at receiving terminal, clock signal and data-signal are through the transmission of PCB, all produced certain time-delay, owing to only guaranteed the signal lead length unanimity in the grouping, can not guarantee the consistency of its phase place between each grouping, clock line in any one grouping all is difficult to satisfy the requirement of the settling time and the retention time of data-signal, can not be with sample data-signals in all each grouping of a single clock, reduction of data step of the present invention utilizes following method to realize accurately sampled data signal and with its reorganization:

Utilize the clock signal of each datum plane sample the respectively data-signal and the frame delimitation signal on notebook data plane, utilize a FIFO (first in first out) formation then, the data that are input as the notebook data plane of sampling respectively through the clock signal of each datum plane of this fifo queue are write the clock signal of clock for this datum plane; The output signal of this fifo queue with the control of the clock of transmitting terminal clock homology under export, and the data/address bus that finally is reduced into original M position is handled for follow-up processing unit.

Further specify below in conjunction with accompanying drawing.

Fig. 1 is the schematic diagram of deriving of clock.

As shown in Figure 1, reference clock REFCLK produces several and reference clock with the clock of homophase frequently behind clock driver, one of them is used at receiving terminal as reference clock (RX_REFCLK), one is used at transmitting terminal as reference clock (TX_REFCLK), and other N is used for each packet (RCLK_1, RCLK_2 ... RCLK_N).

Fig. 2 is the grouping schematic diagram of data, as shown in Figure 2, data/address bus is divided into N group fifty-fifty, and clock signal of each set of dispense and frame delimiter are with the original position of definition of data frame.

Fig. 3 is the phase relation schematic diagram of clock and data, as shown in Figure 3, data-signal is got at the rising edge of reference clock, satisfy certain settling time (Tsetup) and retention time (Thold), RCLK_ is for transmission arrives the clock signal of receiving terminal through PCB, and RCLK_ compares with reference clock certain transmission delay (Tdelay).

Fig. 4 is the handling process schematic diagram of receiving terminal FIFO among the present invention, as shown in Figure 4, in a single day receiving terminal receives the write operation that frame delimitation signal SOF promptly begins (also comprising corresponding with it data-signal certainly) FIFO, data-signal is write FIFO, it writes the clock (RCLK_1 of clock for each grouping, RCLK_2 ... RCLK_N), treat all SOF that divide into groups all to have received, and corresponding data are write the read operation that FIFO then begins all FIFO (every group of corresponding FIFO) simultaneously, reading clock is RX_REFCLK, and the data of reading are reconfigured, handle for follow-up processing unit.

The data processing method specific implementation of high speed multidigit parallel data bus line of the present invention may further comprise the steps:

Step 1 is divided into some groups with the parallel data bus line of multidigit, and every group is defined as a data plane, comes the beginning of the designation data term of validity, SOF signal and first active data signal alignment with a Frame delimitation signal (SOF);

Step 2, produce several and reference clock (REFCLK) with the clock of deriving of homophase frequently with a zero-lag clock driver, one of them is used for the reference clock (RX_REFCLK) of receiving terminal, a reference clock (TX_REFCLK) that is used for transmitting terminal, produce the clock of deriving in addition each datum plane, be used for receiving terminal sampled data (RCLK_n, n is 1,2 ... N), in each datum plane inside, transmitting terminal is got data-signal and frame delimitation signal (SOF) at the rising edge or the trailing edge of this clock of deriving; Because the signal in each packet is realized the track lengths unanimity on the PCB, do not require the track lengths unanimity of whole data/address bus.As long as can guarantee the signal lead length unanimity in the packet, then can allow long PCB cabling;

Step 3 at receiving terminal, is utilized a fifo queue (FIFO), and a clock with the reference clock homology is used to control the output of FIFO;

Step 4, the method that data reconfigure, under the effect of frame delimitation signal, utilize FIFO read-write clock with characteristics frequently, in case valid data write FIFO, promptly start the read operation of FIFO, and read FIFO in data and be reassembled into the data/address bus consistent later on, handle for follow-up processing unit with form before the packet.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims

1, a kind of data processing method of high speed multidigit parallel data bus line, it is characterized in that, transmitting terminal is divided into clock zone transmission a plurality of and reference clock frequency homophase together with the multi-bit parallel data/address bus, the receiving terminal utilization is read clock and is write clock and all reduce described multi-bit parallel data/address bus with the fifo queue of the same frequency of reference clock homophase as buffer memory, and the data wire and the clock line of each clock zone inside are isometric.

2, the data processing method of high speed multidigit parallel data bus line according to claim 1 is characterized in that, specifically comprises the steps:

The multi-bit parallel data/address bus is divided into many groups, and each set of dispense one clock and of deriving is used for the frame delimiter of the original position of definition of data frame, and the data wire and the clock line of packets inner are isometric;

3, the data processing method of high speed multidigit parallel data bus line according to claim 2 is characterized in that, the described clock of deriving, tranmitting data register and receive clock are produced according to reference clock by the zero-lag clock driver.

According to the data processing method of claim 2 or 3 described high speed multidigit parallel data bus lines, it is characterized in that 4, receiving terminal begins the grouped data of correspondence is write described fifo queue after receiving described frame delimiter.

5, according to the data processing method of claim 2 or 3 described high speed multidigit parallel data bus lines, it is characterized in that first active data signal alignment of described frame delimiter and corresponding grouped data.

6, the data processing method of high speed multidigit parallel data bus line according to claim 5 is characterized in that, the described frame delimiter of each grouped data comes into force simultaneously.